JPH02210249A - Method and device for inspecting appearance - Google Patents

Abstract

PURPOSE:To enhance scanning efficiency and a speed for inspecting appearance by successively scanning plural areas arranged in a matrix direction on an object to be inspected and starting the scanning for a next row with an area adjacent to a scanning final area as a head. CONSTITUTION:A Ztheta stage 2 is placed on an XY stage 1 and a semiconductor wafer 3 is placed on the stage 2 as the object to be inspected. An optical recognition means is obtained by constituting a line sensor 71 of a CCD driven with clock pulses. The wafer 3 is irradiated with light from an illuminating light source 4 through a half mirror 6 and an objective lens 5 and detecting light which reaches the sensor 71 is converted into a binary image signal by a signal processing circuit 8 and inputted in an image storage circuit 14 and a signal comparison circuit 9. When the scanning of one row is completed in the case of the scanning of the sensor 71, the detection signal of the final area of the previous row is read out in a reverse direction by a storage circuit 14 so that the head area of the scanning of the next row may be an area which is the nearest to the final area. Thus, the scanning efficiency and the speed for inspecting the appearance are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a technique that is effective when applied to pattern defect inspection or foreign matter inspection on semiconductor wafers, photomasks, magnetic disks, optical disks, etc.

[Conventional technology]

As a conventional pattern defect inspection technique of this type, the method shown in FIGS. 8 to 10 is known. Hereinafter, these conventional techniques will be explained based on the drawings.

FIG. 8 shows what is called a two-lens two-chip comparison method, and in the figure, a semiconductor wafer 3 as an object to be inspected is placed on a Zθ stage 2 placed on an XY stage 1. . Above this semiconductor wafer 3,
Similarly, a pair of one-dimensional light receiving elements 7 are arranged via a pair of objective lenses 5 and a half mirror 6. An illumination light source 4 such as a halogen lamp is arranged on the side of the half mirror 6, and the illumination light from the illumination light source 4 is refracted by the half mirror 6, passes through the objective lens 5, and is directed onto the semiconductor wafer 3. After reaching the target, the half mirror 6 is used as the detection light.
It has a structure in which the light passes through and reaches the one-dimensional light receiving element 7. The detection lights received by both one-dimensional light receiving elements 7 are compared as detection signals in a signal comparison circuit 9 via each signal processing circuit 8, and patterns are compared. At this time,
If both detection signals do not match and there is a difference between the patterns, it can be determined that one of the patterns is defective.

Figure 9 shows a technique called the design data comparison method.
Pattern defects on the semiconductor wafer 3 are detected by comparing the pattern obtained from the semiconductor wafer 3 with design data stored in the design data pattern generation circuit 10 in advance.

In FIG. 9, the same reference numerals as in FIG. 8 indicate mechanisms having the same functions as those described in FIG.

In FIG. 10, the TV left camera 3 is used. In this method, the image data recognized by the TV left camera 3 is temporarily stored in the TV image storage circuit 11, and then an adjacent chip area on the semiconductor wafer 3 is imaged by moving the xY stage 1. This image data is stored in a TV image storage circuit 12 separate from the above, and image data from both TV image storage circuits 11 and 12 is stored in a signal comparison circuit 9.
By comparing the images, differences in image patterns are detected and pattern defects are determined.

[Problem to be solved by the invention]

However, the inventors have discovered that the prior art shown in FIGS. 8 to 1O has the following drawbacks.

First, the two-lens two-chip comparison method shown in FIG. 8 is said to have good inspection efficiency because it is possible to compare two chip areas at the same time. It is difficult to align the characteristics of independent optical systems, and when comparing chip regions located relatively far apart, it is difficult to match the inspection conditions for each region.

Furthermore, if there are subtle variations in characteristic distribution on the semiconductor wafer, it is difficult to compare patterns with high accuracy.

In the method shown in Figure 9, it is necessary to prepare a huge amount of design data in advance, and based on this design data, a basic pattern to be expected must be created. The processing at each stage increased and was not practical.

In the method using the TV left camera in FIG. 10, after a pattern on a predetermined chip area is imaged by the TV left camera 3,
Move the XY stage l by a predetermined amount and move the TV left camera 3.
In order to repeat the process of stopping directly above an adjacent chip area and imaging the pattern of this chip area, the χY stage moves and stops frequently, which wastes inspection time and requires high-speed inspection processing. was difficult.

From this point of view, there is a technique described in Japanese Patent Application Laid-Open No. 62-267649 by the present applicant, in which images of adjacent chip areas are sequentially stored in a memory (storage means) and compared. It could not be said that sufficient consideration was given to improving efficiency.

The present invention has been made with attention to the above-mentioned problems, and its purpose is to provide a technique that can improve inspection efficiency in visual inspection.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when an area on the object to be inspected is scanned in the row or column direction by the optical recognition means, if the scanned area is the last area of the row or column, the next area adjacent to the last area is scanned. The scanning of the next row or column is started using the leading area belonging to the row or column as the subsequent area, and the detection signal obtained by scanning this leading area is read out from the storage means in a direction opposite to the writing direction. This is compared with the detection signal of the final area.

In order to achieve this, an optical recognition means that can be moved relatively in the row or column direction on the object to be inspected, and a detection signal from the optical recognition means can be written and read out in forward and reverse directions. The structure of the visual inspection apparatus includes a storage means and a comparison means for comparing two or more detection signals obtained from two or more areas.

[Effect]

According to the above-mentioned means, even when scanning of one row or column is completed when scanning the optical recognition means, the detection signal of the last area of the row or column before the storage means is read out in the reverse direction. Since the leading area of the scanning of the next row or column can be the area closest to the final area, the scanning efficiency can be increased and the inspection speed of the visual inspection can be improved.

Moreover, the inspection speed can be further increased by continuously moving the scanning of the optical recognition means with respect to the object to be inspected.

〔Example〕

FIG. 1 is an explanatory diagram showing a scanning locus in a visual inspection according to an embodiment of the present invention, FIG. 2 is a block diagram showing a visual inspection apparatus according to an embodiment of the present invention, and FIG. 3 is a diagram showing the present embodiment. FIG. 4 is an explanatory diagram showing the state of area division on the test chip;
FIG. 5 is an explanatory diagram showing the scanning locus in the prior art corresponding to FIG. 1, FIG. 6 is an explanatory diagram for defect determination, and FIG. 7 is a plane showing the chip arrangement on the semiconductor wafer, which is the object to be inspected. It is a diagram.

The visual inspection apparatus of this embodiment has a Zθ stage 2 placed on an XY stage 1, as shown in FIG.
A semiconductor wafer 3 as an object to be inspected is placed on the Zθ stage 2. A line sensor 71 as an optical recognition means is arranged above the semiconductor wafer 3 via an objective lens 5 and a half mirror 6. Such a line sensor 71 is, for example, a 1024-pixel CCD driven by two-phase or four-phase clock pulses (
Charge Coupled Device).

An illumination light source 4 such as a halogen lamp is arranged on the side of the half mirror 6, and the illumination light from the illumination light source 4 is refracted by the half mirror 6, passes through the objective lens 5, and is directed onto the semiconductor wafer 3. After reaching the line sensor 71, the detection light passes through the half mirror 6 and reaches the line sensor 71.

The line sensor 71 is converted into a binarized or multi-valued image signal by the signal processing circuit 8, inputted to the image storage circuit 14, and then outputted to the signal comparison circuit 9 as a detection signal.

As shown in the block diagram of FIG. 3, the image storage circuit 14 includes an input image register 15, an image memory 16 as a storage means, and address generation circuits 17a and 17b1 that provide addresses to the image memory 16.
ad) and write timing, a timing generation circuit 18, an output image register 19, and the like.

The image signal input from the signal processing circuit 8 is first held in the input image register 15, and then written into the image memory 16 based on the address instructed by the address generation circuit 17H.

Further, the image signal (image data) written in the image memory 16 in this manner is read out by the address generation circuit 17b based on the address specified by the address generation circuit 17b, and then held in the output image register I9.

Note that the write and read timings and the control of the address generation circuits 17a and 17b described above are both performed by the timing generation circuit 18. Here, the address generation circuits 17a and 1'7b are both constituted by reversible counters, and are controlled by up/down signals that are inverted depending on the scanning direction, which will be described later.

Next, the necessity of reversibly reading and writing data in the image memory 16 will be explained.

As shown in FIG. 4, chips (areas) are placed on the semiconductor wafer 3.
When A to C are arranged, the vertical width m of the chip that can be image recognized by scanning one line is limited by the recognizable width of the line sensor 71. Therefore, when such a line sensor 71 is used, chips A-C are divided into strip-shaped regions (divided regions) a-h in the scanning direction, and
It is efficient to scan each area a to h.

FIG. 5 shows a case in which chips arranged in rows and columns on an actual semiconductor wafer 3 are scanned. In the figure, only six chips are shown to simplify the explanation. When performing the above scanning on each of the chips A to F, first, the area a of the lower chip is scanned by the line sensor 71 by moving the XY stage 1 from right to left in the figure, and then the area a of the adjacent chip B is scanned. Detection signal B obtained from area a of chip B by continuously scanning area a to the left
-a is compared with the previous detection signal A-a of chip A. Next, the detection signal C-a obtained by scanning the area a of the chip C
is compared with the detection signal B-a. In this way, patterns are compared between areas a between adjacent chips in sequence.

After completing the scanning of all areas a of each chip in the row direction of the lower row in this way, the upper chip D-F is scanned, but at this time, the last chip C of the lower row and the first chip of the upper row are scanned. When comparing with chip D, the scanning direction must also be from right to left in the figure in order to match the direction of the detection signal. For this purpose, it was necessary to move the XY stage 1 largely as shown by the dashed line in the figure. Therefore, when a large number of chips are arranged at a high density on the semiconductor wafer 3, the equipment performs many unnecessary operations, which hinders efficient visual inspection. .

Furthermore, in the above case, when the scanning line moves from the lower stage to the upper stage, the chip C and the chip D are located at separate positions on the semiconductor wafer 3.
Therefore, depending on the state of variation in the characteristic distribution on the semiconductor wafer 3, it may be difficult to compare the detection signals. In other words, it has been required to perform pattern comparison between adjacent chips even when scanning lines change.

Regarding this point, in this embodiment, reading and writing of data to the image memory 16 is performed by the address generation circuit 17a, as described above.
Positive direction (same direction as writing direction) by control of 17b
Since readout is possible in both the reverse direction (the direction opposite to the writing direction), scanning of the line sensor 71 as shown in FIG. 1 is possible. That is, after scanning the a area of chip C (■→■), when moving to the upper row, the chip F located in the vicinity of this chip C is scanned as the first chip (■→■). . At this time, area a of chip F is scanned from right to left in the figure. Since the detection signal C-a of the chip C to be compared with this is scanned from left to right in the same figure, the detection signal C-a is read out from the image memory 16 in the opposite direction from the writing. . This makes it possible to compare the detection signal F-a obtained from the chip F with the detection signal C-a. After completing the scanning of all the areas a of the upper chips F-D in this way (■→■), the scanning moves to the lower row again, and this time the scanning of the areas A-C-F of each chip A-C-F is completed. ～D starts in the order shown by the dashed line (■−■→■
→■).

It should be noted that the movement of the XY stage 1 for scanning does not necessarily have to be at a constant speed; in the figure, ■ to ■ move at a constant speed for inspection, then ■ to ■ move at high speed, and ■ ~■
The scanning range in which no image is captured by the line sensor 71 may be moved at a high speed, such as moving at a constant speed, moving at a high speed from 1 to 2, and moving at a constant speed from 2 to 3.

Next, the principle of defect determination in this embodiment will be explained with reference to FIG.

Assume that there is a defect X in region C of chip B in FIG. First, the line sensor 71 scans the area C of the chip A, which is the previous area, by moving the XY stage 1, and the image signal (detection signal A-c) regarding the area C recognized by the line sensor 71 is processed by signal processing. In the circuit 8, it is passed through the input image register 15 as a binary or multivalued digital signal, and then sent to the address generation circuit 17al.
:Thus, the image memory 16 is stored based on the specified address.
will be written to.

Subsequently, when the line sensor 71 scans the next area C of the chip B, the image signal (detection signal B-c) regarding the next area C passes through the signal processing circuit 8 and is sent to the signal comparison circuit 9 and the image signal. It is output to the memory circuit 14. At this time, the signal comparison circuit 9 uses the detection signal previously written in the image memo 'J16, 6. -c is being read. In this signal comparison circuit 9, the detection signal A-c and the detection signal B-c
are compared. At this time, in FIG. 6, since the defect X exists in the area C of the chip B, the detection signal A-C and the detection signal B-c do not match. is recorded. Specifically, a flag may be set in a control means (not shown) or the like.

Subsequently, in the same manner as described above, the area C of the chip C is scanned and the detection signal C-c obtained thereby is compared with the detection signal B-c. In this case as well, in this embodiment, since the two signals do not match, information on the mismatch is recorded in the same manner as above. In this way, the detection signals A-c, B-c,
If C-c continuously mismatches, it is detected that the defect X exists in the area C of the second chip B. In addition, when inconsistent information is obtained continuously as described above, it is further detected whether or not the inconsistent coordinates are at the same position each time of comparison, and finally chip B is determined.
Defect X in area C is determined.

FIG. 7 shows the scanning order when the above steps are performed for the entire chip area of the semiconductor wafer 3. In the figure, the numbers written inside the chips indicate the order of scanning.

That is, in the figure, all chips are tested in the order of 5t-326. Here, the first chip S1 and the last chip S26
, the number of chips to be compared is one by one (31 is S
2. Since 525)L does not exist in S26, the defect determination described in FIG. 6 cannot be made. Therefore, before starting the inspection on the wafer 3, chips other than S2 adjacent to chip Sl, for example, chip S9, are first scanned, and after scanning the last chip S26, chips other than S25 adjacent to chip S2, For example, the chip 318 may be scanned.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, although a case has been described in which a CCD line sensor is used as the optical recognition means, other image sensors or even a TV camera may be used as long as high-speed image capture is possible.

In the above explanation, the invention made by the present inventor was mainly applied to the field of application, which is the so-called appearance inspection of semiconductor wafers, particularly pattern defect inspection, but the present invention is not limited to this. It is also applicable to foreign matter inspection on wafers and to visual inspections other than those mentioned above.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

According to the present invention, even when scanning of one row or column is completed when scanning the optical recognition means, by reading out the detection signal of the last area of the row or column before the storage means in the reverse direction, The starting area of the next row or column scan can be the area closest to the final area above, so
Scanning efficiency can be increased, and the inspection speed of visual inspection can be improved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a scanning locus on a chip of a semiconductor wafer in visual inspection according to an embodiment of the present invention; FIG. 2 is a block diagram showing a visual inspection apparatus according to an embodiment of the present invention; FIG. 3 is a block diagram showing the signal processing system in the image storage circuit of the embodiment, FIG. 4 is an explanatory diagram showing the state of area division on the test chip of the embodiment, and FIG. 5 is for explanation of the present embodiment. FIG. 6 is an explanatory diagram showing the scanning locus in the prior art; FIG. 6 is an explanatory diagram for defect determination in the embodiment; FIG. 7 is a plan view showing a semiconductor wafer as an object to be inspected used in the embodiment; to FIG. 10 are block configuration diagrams showing pattern inspection apparatuses in the prior art. 1...XY stage, 2...Zθ stage, 3...
- Semiconductor wafer, 4... Illumination light source, 5... Objective lens, 6... Half mirror 7... Dimensional light receiving element, 8...
...Signal processing circuit, 9...Signal comparison circuit, 10...
Design data pattern generation circuit, 11... Image storage circuit, 12... Image storage circuit, 13... Camera, 14.
...Image storage circuit, 15...Manual image register, 16
...Image memory, 17a...Address generation circuit, 1
7b... Address generation circuit, 18... Timing generation circuit, 19... Output image register, 71... Line sensor, A-F... Chip, 81-S26... Chip, a-h ···region. Agent Patent Attorney Kazudai Tsutsui 1 Figure 2 a-h: Kinya j Imafune Kokan Figure Figure Figure Figure Figure Figure Figure Figure

Claims (1)

[Claims] 1. While sequentially scanning a plurality of regions consecutively arranged in the matrix direction on the object to be inspected in the row or column direction using optical recognition means, A visual inspection method in which a subsequent area is scanned while writing the detected detection signal into a storage means, and the detection signal from the subsequent area is compared with a previous detection signal read from the storage means, the method comprising: If the area is the last area of a row or column, start scanning the next row or column with the first area belonging to the next row or column adjacent to the last area as the next area, and scan this first area. A detection signal obtained by scanning the area is compared with a detection signal of the final area read out from the storage means in a direction opposite to the writing direction. 2. The above-mentioned optical recognition means continuously scans the entire area of a part of the divided area divided into strips, and then repeats the same scanning for other divided areas, thereby scanning the entire surface of the object to be inspected. 2. The visual inspection method according to claim 1, further comprising performing the following steps. 3. An appearance inspection device that determines pattern differences by comparing two or more detection signals obtained by scanning a plurality of areas continuously arranged in a matrix direction on an object to be inspected, which an optical recognition means that is relatively movable on the object in the row or column direction; a storage means that can write a detection signal from the optical recognition means and read it in forward and reverse directions;
A visual inspection device comprising a comparing means for comparing two or more detection signals obtained from two or more regions. 4. The appearance inspection apparatus according to claim 3, wherein the optical recognition means is a line sensor composed of a CCD.