JPH02206841A - Virtual machine system - Google Patents

Abstract

PURPOSE:To speed up a response time with respect to interruption by permitting a VM quest to logic-operate the value of a mask bit which is set/reset in accordance with a processing content in the middle of execution and the value of an interruption request from a VM timer device. CONSTITUTION:A register 1 holds a VM quest number in the middle of execution at present. A register 2 holds the number of the VM quest in a high priority degree, which processes a VM real time interruption processing, namely, the VM quest in which VM timer interruption is held. The register 1 is rewritten whenever the VM quest to be processed is switched, and the register 2 is rewritten whenever the VM quest in the high priority degree is changed. A comparator 3 always compares the contents of the registers 1 and 2. The coincident output '1' shows that the VM quest in the middle of execution at present is that in the high priority degree, which executes the real time processing which has to hold the VM timer interruption.

Description

[Detailed Description of the Invention] [Summary] In order to switch and operate multiple operating systems and VM guests, which are subordinate programs thereof, in one computer system, a timer interrupt mechanism for switching VM guests in a time-sharing manner, and a timer interrupt mechanism for switching VM guests in a time-sharing manner, Regarding virtual computer systems equipped with a VM real-time interrupt mechanism for switching VM guests in real time in response to interrupt requests from sources other than timers, the remaining processing that was previously interrupted from the time an interrupt request is made until the processing for this interrupt request is executed is The purpose is to eliminate the time required for execution, and disables VM timer interrupts when the mask bit that indicates whether interrupts are enabled or disabled for the process being executed by the VM guest is in a state that indicates that interrupts are not allowed. It was configured as follows.

[Industrial application field]

In order to switch and operate multiple operating systems (O8) and VM guests that are subordinate programs in one computer system, the present invention provides a timer interrupt mechanism for switching VM guests in a time-sharing manner, and a The present invention relates to a virtual computer system including a VM real-time interrupt mechanism for switching VM guests in real time in response to an interrupt request.

[Conventional technology]

Due to recent improvements in computer performance, virtual computers (7M) have reached a practical level. Along with this, the usefulness of VM has been recognized, and efforts have been made to effectively utilize VM in various fields.

Furthermore, as virtual computers have come into general use, there is a demand for realizing virtual computers more efficiently and reducing overhead.

For this reason, a VM mechanism is provided to efficiently operate the VM monitor, which is a VM @ control program, but the VM mechanism is not suitable for systems that perform online processing or real-time processing.
When applying this, it is also necessary to realize high-speed interrupt responses to external events.

To explain in more detail, in order to operate a processor system, an operating system (hereinafter referred to as
O81) is used, and in particular, multitasking is realized by O8 in order to make more effective use of limited computer resources.

This multitasking processing is realized by dividing the computer processing (job) requested by the user into a series of task combinations to which CPU time is given, and then switching and executing a plurality of jobs using this task as a unit.

In order to manage the status of this task and allocate the CPU appropriately, O8 creates a control block for each task that stores the status of the task in a small area on the main memory, and logically stores the block in a certain order. Create a queue connected to

This queue consists of an "executable queue" which is a chain of tasks that can be executed immediately, a "queue waiting for ■10 processing" which consists of tasks that cannot proceed to the next step until the I10 process is completed, and a queue that is connected to other tasks. There is a "synchronization queue" consisting of tasks that are stopped because they require synchronization.

When executing computer processing, the O8 takes out the first task from the "executable queue" and assigns a CP to this task.
Allocate U time and execute the process. If this running task requests O8 to wait for I10, the execution of that task is interrupted and connected to the "■10 queue", and the next task is taken from the "executable queue". allocate CPU time.

In this way, the O8 allocates CPU execution time to executable tasks, but when there are no more executable tasks, the wait state bit of the program status word (hereinafter referred to as PSW) is set to "1" and the instructions in the CPU are The process is stopped and this CPU is placed in a standby state. If a task to be processed such as an interrupt occurs, the wait bit of this PSW is set to "0" and the operation is restarted.

There are many types of O8 that differ depending on the processing purpose, and the appropriate O8 is selected and used depending on the purpose of use of the computer system, but recently, multiple O8
A virtual computer system (VM mechanism) that allocates CPU resources on a time-sharing basis to programs under the VM system has come into practical use.

In order to perform this time-sharing allocation, a VM timer, which is a timer interrupt mechanism dedicated to the VM mechanism, is provided.
When this VM timer generates an interrupt to the computer at a fixed time interval of, for example, 20 milliseconds, control of the CPU is transferred from the currently executing O3 and the VM guest, which is a program under it, to the VM monitor. It goes without saying that the interrupt time interval of this VM timer is not limited to the above-mentioned 20 milliseconds, but may be adjusted to an optimum interval for the computer system.

Furthermore, in systems that require a high-speed response to interrupt requests due to external events, the O8 and the VM guest, which is a program under it, that should handle this interrupt (VM real-time interrupt) are determined in advance, and when the interrupt request occurs, At this point, the VM guest targeted by this interrupt has CPU
If no time has been allocated, a mechanism is provided that immediately generates a VM real-time interrupt and transfers control to the VM monitor without waiting for the VM timer interrupt.

However, since interrupts by the VM timer occur at fixed time intervals as described above, regardless of the operation of the VM guest, for example, when the VM is in the process of responding to an external event that requires a high-speed response, A timer interrupt may occur and the CPU may be taken over.

4 to 6 are for explaining the above-described virtual computer system, and FIG. 4 is a block diagram showing the internal configuration of the virtual computer system related to the present invention.

In FIG. 4, the instruction unit IU extracts and interprets microinstructions and data from the control storage C8 that stores microprograms or the local storage LS that is used as a rework area that stores logical register data. It controls the execution of the program, and inside it is provided a psw register PSWR that stores the above-mentioned psw.
The contents of W will be explained in detail later.

The storage control unit (SU) is connected to a system bus/memory control device (not shown) via a bus/memory control device interface IF, and receives instruction fetch requests from the instruction unit IU and operands from the execution unit EU or instruction unit IU. It receives a fetch store request and executes it, reads the instruction code from the instruction address and transfers it to the instruction unit IU, receives an operand address from the instruction unit IU and transfers the operand to the execution unit EU, and executes the instruction code from the instruction address. It performs processing such as storing execution results of operands and the like in an external storage device (not shown) via the interface IP.

The execution unit (EU) includes an arithmetic unit, a shifter, etc., and executes arithmetic operations in response to instructions from a microprogram from the instruction unit IU, and is provided with a work register WR for this purpose.

When an exception occurs in the address conversion in the storage control unit SU or an arithmetic exception occurs in the execution unit EU, the instruction unit IU is notified of the exception and an interrupt is requested, and the bus/memory control unit interface IU is notified of the exception.
F notifies the instruction unit rU of a 110 interrupt request or an external interrupt request.

On the other hand, in order to operate as a virtual machine system, a VM timer VT is provided for selectively operating the VM guest in a time-sharing manner as described above, and the interrupt request and interrupt request instructions from this VM timer VT are provided. Interrupts to unit 1-IU are handled by PSW as shown in Figure 5.
is controlled according to the state of the control bit.

That is, FIG. 5 shows the program status word register PSW provided in the instruction unit IU.
The bit assignment in R is shown, and this register includes the instruction address, main memory access key, wait bit, exception mask, external mask, I10 mask, and dynamic address conversion function (Dynami (Addr
Bits for controlling the ess Translation (DAT) are provided, and these bits are rewritten by the instruction unit IU under instructions from O8.

The 110 interrupt request from the bus/memory controller interface IF, the external interrupt request, and the exception interrupt request from the storage control unit (SU) or execution unit 1-EU are sent to these interrupts in the program status word register PSWR. Correspondingly provided bit values "0", 11" which are set to "1" when these interrupts are enabled, and AND circuits AI, Ai
, A3, and an interrupt request is made to the instruction unit (U) via the OR circuit 0 which takes the logical sum of the outputs.

However, an interrupt request from the VM timer VT for switching the O8 and the programmable controller under the O8 at regular intervals is unconditionally sent from the OR circuit O to the instruction unit IU to issue an interrupt request.

When the instruction unit I-IU receives this interrupt request, it executes the interrupt processing program from the beginning after completing the processing being executed under the control of the microprogram, such as machine language instruction processing and interrupt processing, and executes the interrupt processing program. The program analyzes the cause of the interrupt and performs processing according to the specifications of each interrupt.

FIGS. 6(a) and 6(b) are time charts conceptually showing the relationship between the processing being executed in this instruction unit and interrupts, and FIG. When there is an interrupt from the VM timer while 7M guest 1 is running, it returns to the VM monitor and switches to O3, which should be executed in the next period.
When this switching is completed, the execution of VM guest 2, which is a program under the other O8, is started, and the
The VM guest is switched every time there is an interrupt from the M timer.

In the same figure (b), when the 7M guest 1, which has a high priority, is executing processing with interrupts from others prohibited at time 1°, as shown by the bold line, a timer interrupt from the 7M timer occurs at time t2. 7M guest 1 interrupts the process being executed by this timer interrupt, returns to the VM monitor, and then processes VM guest 2.

Time t during the period when this VM guest 2 is executing the process
, an external event occurred in 7M guest 1 with high priority and V
￥When a real-time interrupt request is made, VM guest 2
interrupts the process and hands over the CPU to the VM monitor, and this VM monitor hands over the CPU to the 7M guest 1 that made the above interrupt request at time t4.

The 7M guest 1, which obtained the CPU, executes the process that was interrupted by the interrupt from the VM timer, and responds to the VM real-time interrupt that was requested as an interrupt from time t when the interrupted process was finished to time t. Start processing.

[Problem to be solved by the invention]

As mentioned above, if a timer interrupt from the VM timer takes up CPU time while a high-priority VM guest is executing a process with interrupts disabled, that process will be interrupted and the CPU will be reassigned to that VM guest. The rest of the processing will be executed when the

Therefore, an extra waiting time from t4 to t is required from the occurrence of an external event until the processing of an interrupt based on this external event is started.

An object of the present invention is to reduce the time required to execute the remainder of the previously interrupted process from when an interrupt request is made until the process for this interrupt request is executed.

[Means to solve the problem]

In order to run multiple operating systems and VM guests, which are their subordinate programs, simultaneously on one computer system, we have a timer interrupt mechanism for switching VM guests in a time-sharing manner, and a timer interrupt mechanism that switches VM guests in real time based on interrupt requests from sources other than the timer. In a virtual machine system equipped with a VM real-time interrupt mechanism for switching the VM timer interrupt, when the mask bit indicating whether interrupts are enabled or disabled for the process being executed by the VM guest is in a state indicating that interrupts are not allowed, the VM timer interrupt is disabled. configured to prohibit it.

[For production]

FIG. 1 is a diagram showing the principle of the present invention, and shows the value of a mask bit M that is set and reset depending on the content of the process being executed by a VM guest, and the value of an interrupt request from outside the VM timer mechanism. By performing a logical operation using a logic circuit such as an AND circuit, the interrupt request from the VM timer is permitted or disallowed depending on the state of the mask bit M.

FIG. 2(a) is a time chart showing an example of the operation according to the present invention for a VM real-time interrupt, which is the same as the time chart shown in FIG. For this purpose, the conventional operation example shown in FIG. 6(b) is reprinted in the same figure (bl).

In the present invention, at the same time that the VM guest 1 starts processing to disable interrupts at time t, the above mask bit M
is set to, for example, "O" to indicate that interrupts are disabled.

Referring to FIG. 2(a) above, when the mask bit M is "0" in this way, the VM timer T starts '' at time t2.
Even if an interrupt request of 1 level arrives, the output from the logic circuit shown as an AND circuit, that is, V to the CPU.
The M timer interrupt request is not output, so the CPU executes a series of processes until the end without interrupting the process being executed, and sets the mask bit M to "1" when the process is completed.

If mask bit M is set to “1” in this way,
If there is a VM timer interrupt request from VM timer T during execution of processing, the output of the above logic circuit becomes "1", and this output moves the CPU to the processing of the 7M monitor, and further transfers the processing to the VM guest 2. can be directed to processing.

In this way, when a VM real-time interrupt occurs to VM guest 1 with a high priority at time t while VM guest 2 is executing processing, the CPU processing is transferred to this VM guest 1 via the VM monitor. Real-time interrupt processing begins, but at this time VM guest 1
The previous process that required interrupts to be disabled has finished, so
Processing for this VM real-time interrupt is immediately executed.

〔Example〕

FIG. 3 shows one embodiment of the present invention, showing a VM timer interrupt mask circuit added to the VM timer interrupt mechanism.

Register 1 is a register that holds the number of the VM guest currently being executed, and register 2 is a register that holds the number of the VM guest that is currently executing.
This is a register that holds the number of a VM guest for which a timer interrupt is pending.Register 1 is rewritten each time the VM guest to be processed is changed, and register 2 is rewritten when the high priority VM guest number is changed.

The comparator 3 constantly compares the contents of these registers 1 and 2, and the output "1" indicates a high priority for the currently executing VM guest to process a real-time interrupt that should hold the VM timer interrupt. This indicates that the product is of high quality.

VMs with high priority and VM timer interrupts should be held pending
For example, 110 is stored in the program status word register (PSWR) 4 provided corresponding to the guest.
Mask bits are provided for each type of interrupt request, such as interrupts, external interrupts, and bus interrupts.
A mask bit corresponding to a process in which the currently executing VM guest does not permit a VM timer interrupt is set to "O", and a mask bit corresponding to a type of process that allows a VM timer interrupt is set to "1".

The real-time interrupt mask register 5 contains the above PSWR.
A VM timer interrupt mask bit is provided which corresponds to each of the mask bits 4 and 4 and is set by an operator or the like, and by setting this bit to "1", the VM timer interrupt is set to be suspended.

A specific explanation will be given by taking as an example a case where the bit 51 shown at the left end in the diagram of the VM timer interrupt mask register 5 is set to "1" so that the VM timer interrupt is suspended while the 110 interrupt is being executed.

While the CPU is processing the 110 interrupt, the PS
Mask bit 41 of WR4 is set to O'',
This mask bit 4. The value of is supplied to the inverting input terminal from the AND circuit 61, which outputs "l" as a logical product with "1" of the mask bit 5 of the M timer interrupt mask register 5.
is output, and after passing through the OR circuit 7, this output is sent to the AND circuit 8.
is supplied to one input terminal of

At this time, if the VM guest that the CPU is processing is a VM guest that should hold this VM timer interrupt, register 1 that holds the number of the VM guest that is being processed and the number of the VM guest that should hold the VM timer interrupt. Since the values stored in the holding registers 2 are the same, the comparator circuit C outputs "1" due to this coincidence, and is supplied to the other input terminal of the AND circuit 8.

Therefore, from the inverting output terminal of this AND circuit 8, “
0'' is output and the AND circuit 10 is cut off, so the timer interrupt request from the VM timer mechanism 9 is blocked by the AND circuit 10 and is not supplied to CPtJ.
No VM timer interrupt occurs.

When the CPU finishes processing the VM guest that is currently being executed and becomes able to execute other processing, the 110 interrupt is also allowed and the I10 mask bit 41 of PSWR4 becomes l", so the above AND circuit is executed. The output of 6. is “O
”, and this “0” level output is supplied to one input terminal of the AND circuit 8 via the OR circuit 7.

Therefore, from the inverting output terminal of this AND circuit 8, “
Since the output at the 1" level is supplied to one input terminal of the AND circuit 10 and this AND circuit 10 becomes conductive, the VM timer interrupt request from the VM timer mechanism V is passed through the second AND circuit 10. The CPU is supplied with V
M timer interrupt occurs.

〔Effect of the invention〕

As explained above, according to the present invention, the VM guest
It is possible to prevent delays in the execution of VM real-time interrupt response processing that occur when processing that was interrupted by an M-timer interrupt is executed before VM real-time interrupt processing, making the response time for VM real-time interrupts fast and stable. It is possible to achieve extraordinary effects.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a time chart showing interrupt processing according to the present invention in comparison with conventional interrupt processing. FIG. 3 is a diagram showing an embodiment of the present invention. 5 is a diagram showing an example of a virtual computer system to which the present invention is applied, FIG. 5 is a time chart showing an example of conventional interrupt request control, and FIG. 6 is a time chart showing an example of conventional interrupt processing. VM guest mask bit...

Claims (1)

[Claims] In order to switch and operate multiple operating systems and VM guests that are subordinate programs thereof in one computer system, there is provided a timer interrupt mechanism for switching VM guests in a time-sharing manner, and interrupts from other than the timer. In a virtual computer system equipped with a VM real-time interrupt mechanism for switching VM guests in real time upon request, a mask bit indicating whether interrupts are permitted or not permitted to the processing being executed by the VM guest is in a state indicating that interrupts are not permitted. A virtual computer system characterized in that timer interrupts are prohibited at certain times.