JPH02206223A - Frequency synthesizer - Google Patents

Frequency synthesizer

Info

Publication number
JPH02206223A
JPH02206223A JP1026143A JP2614389A JPH02206223A JP H02206223 A JPH02206223 A JP H02206223A JP 1026143 A JP1026143 A JP 1026143A JP 2614389 A JP2614389 A JP 2614389A JP H02206223 A JPH02206223 A JP H02206223A
Authority
JP
Japan
Prior art keywords
voltage
circuit
pass filter
output
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1026143A
Other languages
Japanese (ja)
Inventor
Koichi Hasegawa
浩一 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1026143A priority Critical patent/JPH02206223A/en
Publication of JPH02206223A publication Critical patent/JPH02206223A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

PURPOSE:To attain low power consumption in a lock state by inputting a pulse outputted from a phase comparator to a select circuit to switch a power supply for a frequency divider and a circuit holding a voltage of a switching low pass filter of a phase locked loop. CONSTITUTION:When a phase locked loop circuit is in operation, a pulse signal is outputted from a phase comparator 4 and the signal is supplied to a select circuit 8. A signal bringing the switches 10, 11 into nonconductive the switch 12 into a conductive state is outputted from the select circuit 8 when the pulse state, i.e., the width is a prescribed value or below. Thus, an output voltage of a low pass filter 5 is inputted to a voltage holding circuit 9 by the switch 12 and it is inputted to a voltage controlled oscillator 1. Thus, even when a loop circuit is interrupted, the same frequency as the lock state is able to be oscillated. Then the phase locked loop is implemented intermittently and the power consumption is reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は移動部線装置や携帯無線装置といった低消費漕
力化された無線装置に適し必要なときのみ動作させるよ
うにした間欠動作を行う周波数シンセサイザに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention is suitable for wireless devices with low power consumption, such as mobile line devices and portable wireless devices, and performs intermittent operation that operates only when necessary. Regarding frequency synthesizers.

〔従来の技術〕[Conventional technology]

従来の位相ロックループ周波数シンセサイザ回路は第2
図に示すように構成されていた。
Traditional phase-locked loop frequency synthesizer circuits
It was configured as shown in the figure.

この回路は電圧制御発振器1の出力を分周器2で1Ji
lし、さらにマイコンからのデータによ、て分周比が設
定されるプログラマブルディバイダ3によ。て分周され
、この信号が位相比較器4の一方の入力に与えられる。
This circuit divides the output of voltage controlled oscillator 1 into frequency divider 2 by 1Ji.
1, and further by a programmable divider 3 whose frequency division ratio is set according to data from the microcomputer. This signal is applied to one input of the phase comparator 4.

この位相比較器4の他方の入力には水晶発振器6によっ
て作られた発振周波数を固定分周器7によって分周され
た基準周波数が与えられる。この位相比較器4の出力端
子からは2つの入力信号の位相差による電圧が出力され
、ローパスフィルタ5に入力されたのち電圧制御発振器
1に帰還され、入力信号と電圧制御発振器1による発振
周波数差、位相差を無くするように電圧制御発振器1の
発振周波数を変化させロック状態となり、マイコンから
のデータに基づいた必要な周波数を得ることが出来る。
The other input of the phase comparator 4 is given a reference frequency obtained by dividing the oscillation frequency generated by the crystal oscillator 6 by a fixed frequency divider 7. The output terminal of the phase comparator 4 outputs a voltage due to the phase difference between the two input signals, which is input to the low-pass filter 5 and then fed back to the voltage controlled oscillator 1. , the oscillation frequency of the voltage controlled oscillator 1 is changed to eliminate the phase difference, and a locked state is achieved, thereby making it possible to obtain the required frequency based on data from the microcomputer.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の位相ロックループ周波数シンセサイザは以上のよ
うに構成されているので、電池I!源により動作させる
ような携帯無線装置等に使用する場合には、消費電力を
少なくしなければならず、この回路を間欠的に働かせる
ことが必要であるという問題点があった。
Since the conventional phase-locked loop frequency synthesizer is configured as described above, the battery I! When used in a portable radio device or the like that is operated by a power source, power consumption must be reduced, and there is a problem in that the circuit must be operated intermittently.

本発明は上記のような問題点を解消するためになされた
もので、間欠的に位相ロックループを働かせることによ
り低消費!力比できる周波数シンセサイザを得ることを
目的とする。
The present invention was made to solve the above-mentioned problems, and reduces power consumption by intermittently operating a phase-locked loop! The purpose is to obtain a frequency synthesizer that can perform power ratio.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る周波数シンセサイザは位相比較器より出力
されるパルスをセレクト回路に入力し、分周器の電源の
開閉を行うスイッチを設け、位相ロックループの開閉を
行うスイッチ及びローパスフィルタの出力電圧を保持回
路へ送り込むためのスイッチを設け、されら上記のスイ
ッチはセレクト回路の出力信号により制御するようにし
たものである。
The frequency synthesizer according to the present invention inputs the pulse output from the phase comparator to a selection circuit, and is provided with a switch that opens and closes the power supply of the frequency divider, and a switch that opens and closes the phase-locked loop and the output voltage of the low-pass filter. A switch is provided for sending the signal to the holding circuit, and the above-mentioned switch is controlled by the output signal of the select circuit.

〔作用〕[Effect]

本発明における周波数シンセサイザはセレクト回路によ
り、分周器の電源の開閉、位相ロックループの開閉ロー
パスフィルタの17圧を保持する回路の開閉を行い、ロ
ック状態での低消費電力化を図る。
The frequency synthesizer according to the present invention uses a select circuit to open/close the power supply of the frequency divider, open/close the phase lock loop, and open/close the circuit holding the 17 voltage of the low-pass filter, thereby reducing power consumption in the locked state.

〔実施例〕〔Example〕

以下、本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明による周波数シンセサイザの構成を示す
ブロック図で、図において、8はセレクト回路で、位相
比較器4からのパルス状態を入力し、位相ロックループ
回路を制御するための信号を出力する。9は電圧保持回
路で、位相ロックループ回路がロック状態にある時ロー
パスフィルタ(5)からの出力電圧を保持し、電圧制御
発振器lに与えるものである。10 、11.12  
はスイッチで、セレクト回路8からの出力信号により制
御される。
FIG. 1 is a block diagram showing the configuration of a frequency synthesizer according to the present invention. In the figure, 8 is a select circuit that inputs the pulse state from the phase comparator 4 and outputs a signal for controlling the phase-locked loop circuit. do. Reference numeral 9 denotes a voltage holding circuit which holds the output voltage from the low-pass filter (5) when the phase-locked loop circuit is in a locked state and supplies it to the voltage controlled oscillator l. 10, 11.12
is a switch, which is controlled by an output signal from the select circuit 8.

なお、他の符号は前記従来のものと同一である。Note that the other symbols are the same as those in the prior art.

なお、この構成の特徴はローパスフィルタ5の出力m圧
を保持出来る電圧保持回路9を設け、ローパスフィルタ
5と位相比較器4との間、分周器2とその電源Vccと
の間、ローパスフィルタ5とで圧保持回路9との間にそ
れぞれスイッチ10.11.12  を設け、位相比較
器4からのパルス信号を受は入れ、その状態によりスイ
ッチの開閉を行うための制御信号を出力するセレクト回
路8を設けていることである。
The feature of this configuration is that a voltage holding circuit 9 capable of holding the output m voltage of the low-pass filter 5 is provided, and the low-pass filter Switches 10, 11, and 12 are provided between the 5 and the pressure holding circuit 9, respectively, and receive the pulse signal from the phase comparator 4, and output a control signal for opening and closing the switch depending on the state of the switch. The circuit 8 is provided.

次に動作について説明を行う。スイッチ10.11は通
常導通状態にあり、前記従来のものと同一の動作を行う
。そして、この時のスイッチ12は遮断状態にある。
Next, the operation will be explained. Switches 10.11 are normally conductive and operate in the same manner as in the prior art described above. At this time, the switch 12 is in a cutoff state.

位相ロックループ回路が動作をすると、位相比較器4か
らはパルス状の信号が出力されており、この信号がセレ
クト回路8に与えられる。この位相比較器4からのパル
ス信号は位相ロックループ回路がロック状態になった時
にはひげ状のパルスになる。従。て、このセレクト回路
8ではこのパルスの状態つまり幅を一定以下の場合にス
イッチ10.11  を遮断、12を導通状態にする信
号が出力される。されによって、位相ロックループはス
イッチ11により遮断されるが、スイッチ12によりロ
ーパスフィルタ5の出力電圧が電圧保持回路9へ入力さ
れ、それが電圧制御発振器1へ入力される。
When the phase-locked loop circuit operates, a pulse-like signal is output from the phase comparator 4, and this signal is given to the select circuit 8. The pulse signal from the phase comparator 4 becomes a whisker-like pulse when the phase lock loop circuit is in a locked state. Follow. The select circuit 8 outputs a signal that turns off the switches 10 and 11 and makes the switches 12 conductive when the state or width of this pulse is below a certain level. Accordingly, the phase-locked loop is cut off by the switch 11, but the output voltage of the low-pass filter 5 is inputted to the voltage holding circuit 9 by the switch 12, and then inputted to the voltage-controlled oscillator 1.

よって、ループ回路が遮断状態でもロック状態と同じ周
波数が発振可能となる。逆に、セレクト回路8に入力さ
れているパルス信号の幅が一定以上になれば、スイッチ
10.11  が導通、12が遮断状態となり、従来と
同一の動作をとることが出来る。
Therefore, even when the loop circuit is in the cutoff state, it can oscillate at the same frequency as in the locked state. Conversely, when the width of the pulse signal input to the select circuit 8 exceeds a certain level, the switches 10 and 11 become conductive and the switches 12 become cut off, allowing the same operation as the conventional one.

よ。て、こむ、にまり位相ロックループが間欠的に行な
われることになり、各回路のうちで、消費電力の大きい
回路は分周器2であり、消費電力の低減が可能になる。
Yo. Therefore, the phase-locked loop is performed intermittently, and among the circuits, the frequency divider 2 consumes the most power, making it possible to reduce the power consumption.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、周波数シンセサイザを
間欠的に動作する位相ロックループ回路を持つように構
成したので、低消費電力化が得られる効果がある。
As described above, according to the present invention, since the frequency synthesizer is configured to have a phase-locked loop circuit that operates intermittently, there is an effect that power consumption can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1四は本発明の一実施例である周波数シンセサイザの
構成を示すブロック閤、第2図は従来の周波数シンセサ
イザの構成を示すブロック図である。 1・・・町圧制御発振器、2.7・・・分周器、3・・
・プログラマブルディバイダ、4・・・位相比較器、I
5・・・・ローパスフィルタ、6・・・水晶発振器、8
・・・セレクト回路、9・・・電圧保持回路、10・・
・電源スイッチ、11 、12  ・・・スイッチ。 なお1図中、同一符号は同一、または相当部分を示す。
14 is a block diagram showing the configuration of a frequency synthesizer according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional frequency synthesizer. 1... Town pressure control oscillator, 2.7... Frequency divider, 3...
・Programmable divider, 4...phase comparator, I
5...Low pass filter, 6...Crystal oscillator, 8
...Select circuit, 9...Voltage holding circuit, 10...
・Power switch, 11, 12...switch. In Figure 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 入力電圧によって制御される電圧制御発振器と、該発振
器の出力を分周する分周器と、マイコンからのデータに
より分周比を換えることのできるプログラマブルディバ
イダと、水晶発振器によって作られる基準周波数と、該
周波数を分周する固定分周器と、該固定分周器の出力と
前記プログラマブルディバイダからの出力とを比較し位
相差に応じて信号を出力する位相比較器と、該位相比較
器の出力信号に応じて充放電されるコンデンサを有する
ローパスフィルタと、該ローパスフィルタの出力電圧に
より上記電圧制御発振器の発振周波数が制御される位相
ロックループを間欠的に動作させるようにした周波数シ
ンセサイザ回路において、前記ローパスフィルタの出力
電圧を保持出来る電圧保持回路と、前記位相比較器と前
記ローパスフィルタとの間に配置され位相ロックループ
を開閉できるスイッチと、前記電圧制御発振器の出力を
分周する分周器の電源を開閉する電源スイッチと、前記
ローパスフィルタと電圧保持回路との間に配置されロー
パスフィルタの出力電圧を電圧保持回路へ送り込むため
のスイッチと、前記位相比較器からの出力パルス状態に
よって上記各々のスイッチの開閉指示を行うセレクト回
路とを備えたことを特徴とする周波数シンセサイザ。
A voltage controlled oscillator controlled by an input voltage, a frequency divider that divides the output of the oscillator, a programmable divider whose frequency division ratio can be changed based on data from a microcomputer, and a reference frequency created by a crystal oscillator. a fixed frequency divider that divides the frequency; a phase comparator that compares the output of the fixed frequency divider with the output from the programmable divider and outputs a signal according to a phase difference; and an output of the phase comparator. A frequency synthesizer circuit configured to intermittently operate a low-pass filter having a capacitor that is charged and discharged in accordance with a signal, and a phase-locked loop in which the oscillation frequency of the voltage-controlled oscillator is controlled by the output voltage of the low-pass filter, a voltage holding circuit that can hold the output voltage of the low-pass filter; a switch that is placed between the phase comparator and the low-pass filter and that can open and close a phase-locked loop; and a frequency divider that divides the output of the voltage-controlled oscillator. a power switch for opening and closing the power supply; a switch disposed between the low-pass filter and the voltage holding circuit for sending the output voltage of the low-pass filter to the voltage holding circuit; A frequency synthesizer comprising: a select circuit for instructing opening/closing of a switch;
JP1026143A 1989-02-03 1989-02-03 Frequency synthesizer Pending JPH02206223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1026143A JPH02206223A (en) 1989-02-03 1989-02-03 Frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1026143A JPH02206223A (en) 1989-02-03 1989-02-03 Frequency synthesizer

Publications (1)

Publication Number Publication Date
JPH02206223A true JPH02206223A (en) 1990-08-16

Family

ID=12185322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1026143A Pending JPH02206223A (en) 1989-02-03 1989-02-03 Frequency synthesizer

Country Status (1)

Country Link
JP (1) JPH02206223A (en)

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