JPH02206221A - Output noise suppression circuit - Google Patents

Abstract

PURPOSE:To suppress the generation of output noise by adding a 1st resistor, a capacitor and a P-channel transistor(TR) to an output line for an input inverter to bring the point of peak occurrence of a potential rise to a point just before a voltage at an output pad reaches an H level. CONSTITUTION:A level of TRs 21, 22 being components of an output inverter 20 follows to a change in a level of a line l and changes with a delay after a level of the line l changes. Through the use of the property above, a resistor R1 and a capacitor C1 are adjusted to cause a peak of a voltage rise on the line l attend with the turning-on of a TR 31 when a level of an output pad 5 nearly reaches a level Vcc. The level of the line l is raised just before the level of the output pad 5 reaches the level Vcc to suppress the current supplied from the output pad 5. Thus, even when the level of the output pad 5 reaches the level Vcc at a point of time t3, no overshoot takes place.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output noise suppression circuit that suppresses the generation of output noise in an output buffer.

[Prior Art] The main cause of output noise in ICs such as general-purpose ICs and gate arrays is due to parasitic inductance components in tow lines ahead of output pads and wiring outside the IC. If there is an inductance component in the wiring, when di/dt is large enough to cause a current to start flowing, the inductance component will have the effect of blocking that flow, and when the current that was flowing becomes 0 or increases. When -di/dt increases, as when the current reaches a constant value,
There is an effort to maintain the current before the change. Therefore,
In a logic circuit that handles pulsed output waves, overshoot and undershoot occur at the rising edge and falling edge of a rectangular wave, respectively, and the waveform is disturbed, resulting in noise. In order to reduce the noise caused by such open neat and undershoot components, it is necessary to reduce the amount of current flowing from the output buffer or remove this noise inside the chip.

[Problems to be Solved by the Invention] However, the method of reducing the current value from the output buffer has the problem that although the noise is reduced, the drive ability is reduced. Transistor threshold voltage (approximately 1.
It was not possible to remove noise below OV). Therefore, conventionally, IC users have devised their own measures to counter these noises on the outside of the chip.

The present invention has been made to eliminate the above-mentioned problems, and an object of the present invention is to provide an output noise suppression circuit that can suppress the generation of output noise.

[Means for Solving the Problems] The output noise suppression circuit of the present invention includes an input inverter made of P-channel and N-channel transistors that receives an output signal from a chip, and an input inverter that connects the output of the input inverter to an external connection. A circuit added to an output buffer consisting of an output inverter made of P-channel and N-channel transistors leading to the output pad of the circuit, between the VCC line and the output line C of the L input inverter. A first resistor and a capacitor connected in series are connected with the resistor facing the VCC line, and the gate of a P-channel transistor is connected to the connection point of the first resistor and capacitor. a drain connected to the VCC line, a source of the transistor connected to the line Q, and a second transistor connected in series between the line C and the ground line;
a resistor and a capacitor are connected with the resistor facing the ground line, the gate of an N-channel transistor is connected to the connection point of the second resistor and the capacitor, and the drain of the transistor is connected to the line g. and connecting the source of the transistor to the ground line,
It is characterized by:

[Function] By adding a first resistor, a capacitor, and a P channel transistor to the output ink of the input inverter, when the output signal from the chip rises from 1 to H level, the A peak potential rise occurs to prevent a rapid level change from H to L. By making this peak occur just before the voltage at the output pad settles to the H level, the current flowing to the output pad during this period is suppressed, so that no overshoot occurs.

In addition, by adding a second resistor and capacitor and an N-channel transistor, when the output signal from the chip rises from level I to level L, there is a sudden level change from L to level 1 on the line. A peak of potential drop occurs to prevent this. By setting this peak to occur just before the voltage at the output pad settles to the L level, the current flowing to the output pad during this period is suppressed, so that undershoot does not occur.

[Embodiment] FIG. 1 shows an embodiment of an output buffer to which the output noise suppression circuit of the present invention is applied.

10 is an input inverter that receives the output signal from the chip, and is composed of a P-channel transistor 11 and an N-channel transistor 12. The drain of transistor 2 is connected to the VCC line (+5■), and the source of transistor 12 is grounded. The source of transistor 11 and the drain of transistor 12 are connected to each other to form the output line Q of the input inverter IO.

20 is an output buffer that receives the signal on the line Q and leads it to the output pad P, and is connected to a P-channel transistor 2.
1 and an N-channel transistor 22.

Then, a resistor R5 and a capacitor C2 are connected in series between the VCC line and the line ρ of the input inverter 10, with the resistor R8 facing the VCC line, and the gate of the P-channel transistor 3I is connected. is connected to the connection point P between the resistor R2 and the capacitor Ct, the drain of the transistor 31 is connected to the VCC line, and the source of the transistor 31 is connected to the line Q.

Further, a resistor R8 and a capacitor C2 connected in series are connected between the line ρ and the ground line, with the resistor R2 facing the ground line, and the gate of the N-channel transistor 32 is connected to the second resistor. R2 and the connection point P of the capacitor Ct, the drain of the transistor 31 is connected to the line g, and the transistor 32
The source of is connected to the ground line.

Next, the operation of the above circuit will be explained with reference to the time chart of FIG.

When the output signal from the chip is "L", transistor +1 is on and transistor 12 is off, so line Q is at VCC level ("I"), and transistor 21 is off and transistor 22 is on, so the output is Pad P is “
Suppose that the output signal rises from L to I at time to.At this time, the on/off states of transistors 11 and 12 are reversed, and the line ρ suddenly changes to L level. Pulled by the level change of line Q from H to L, point 21 changes from H to L. When point P drops to a predetermined level, transistor 3■ changes from OFF to ON. Switch to
As shown at time points t1 to t, the line Q, which is falling to the L level, is raised to the H level.

However, since the point P is pulled up to VCC by the resistor R3, it rises to the VCC side with the time constant τ1=R1·C8. Also, transistor 31 is turned on and line Q
As the level of P increases, the potential at point P also increases. When the potential at point 21 rises by 1 to a certain level, transistor 31 is turned off, and the potential at line ρ changes by 1 at time t.
, ~t3~, it again goes to the L level.

On the other hand, the transistors 21 and 22 of the output inverter 20 change following the change in the potential of the line Q, but in reality, the output pad 5 usually has a capacitance of 20PF or more, so the potential of the line g changes. changes with a delay. Utilizing this characteristic, the resistor R1 and the capacitor are connected so that when the potential of the output pad 5 approaches VCC (near time t), a peak of the voltage rising north on the line Q occurs as the transistor 31 turns on. Adjust the value with C4. In this way, by increasing the voltage on line Q just before the potential on output pad 5 reaches VCC, the current supplied from output pad 5 is suppressed.
Even when the potential of the output pad 5 reaches VCC at time t3, open NEET no longer occurs.

Next, the case when the output signal falls from H to L will be described.

At this time, transistor 11 is turned on, and transistor! 2 is turned off, and the potential of line C rises rapidly. When the potential at the 21 points is raised to a certain level due to the rise of this potential, the transistor 32 is turned on from off, and the rising level of line g is brought back to the L level. Since the point P2 is connected to the ground line through a resistor Rt, the time constant τ, = R8・C
3, it drops to the L level side, and the transistor 32
The potential at the 22 points also decreases when the switch is turned on. In this way, when the potential of the 22 points drops to a certain level, the transistor 32 is turned off, and the potential of line a then drops to the L level.

In this case as well, by adjusting the values of the resistor R7 and the capacitor C2, the output pad 5 No undershoot occurs even when the voltage reaches the L level.

Thus, line Q, which is the input of output inverter 20
I) By adjusting the 8th position, the current to the output pad 5 is suppressed near the time t when the voltage of the output pad changes,
In other periods, a normal amount of current is allowed to flow, so that it is possible to suppress the occurrence of overshoot and undershoot at the rise and fall of the voltage without reducing the drive ability.

FIG. 2 shows an embodiment of a three-state output buffer to which the output noise suppression circuit of the present invention is applied.

Output line B of the NAND circuit 41 and the NOR circuit 42
The output line ρ is connected to the gates of each of the P-channel and N-channel transistors 51 and 52 in the output inverter 50, and the NAND circuit 41 has a
The output signal from the chip and the inverted signal TRI of the three-state control signal are input to the NOR circuit 42, and the NOR circuit 42 has the following functions:
The output signal and the three-state control signal TRI are manually input.

Then, a resistor R1+ and a capacitor CI+ connected in series are connected between the line B and the ground line, with the resistor R0 facing the ground line, and the gate of the N-channel transistor 61 is connected to the first resistor. and the connection point of the capacitor, and the drain of the transistor 61 is connected to the line 121, and the transistor 61
The source of is connected to the ground line, and a resistor R1, connected in series between the VCC line and the line l1,
and the capacitor C1ffi, and the resistor R11 is connected to the VC
At the same time, the gate of the P-channel transistor 62 is connected to the connection point of the resistor R12 and the capacitor Cat, the drain of the transistor 62 is connected to the VCC line, and the source of the transistor 62 is connected to the line Connected to l2.

In FIG. 2, when line Q1 rises from L level to H level, capacitor C+ + resistor R11 and transistor 61 act as an output noise suppression circuit, and
When line g1 falls from T to L level, resistor R, capacitor CI2, and transistor 62 act as an output noise suppression circuit, and its operation is the same as the output noise suppression circuit in FIG.

[Effects of the Invention] As explained above, the present invention adjusts the human power potential to the output inverter 20 in the output buffer to reduce the current to the output pad 5 just before the voltage of the output pad reaches a steady state. Since the voltage is suppressed and a normal amount of current is allowed to flow during other periods, it is possible to suppress the occurrence of overshoots and undershoots at the rise and fall of the voltage without reducing the drive capability.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit diagram showing an embodiment of an output buffer to which the output noise suppression circuit of the present invention is applied, and FIG. 2 is a three-state circuit diagram to which the output noise suppression circuit of the present invention is applied. FIG. 3, which is a circuit diagram showing one embodiment of the output buffer, is a time chart showing the operation of the output buffer shown in FIG. 5...Output pad, lO...Input inverter, 20°50...Output inverter,! 1, 21, 31, 51
．． 62...P channel transistor, 12, 22,
32°52.61...N channel transistor, R
,,R,. R11+ Rlt...Resistance, C1, Ct, C+
+, Clt...capacitor.

Claims (2)

[Claims] (1) P channel and N channel that receive the output signal of the chip
A circuit added to an output buffer consisting of an input inverter made of channel transistors, and an output inverter made of P-channel and N-channel transistors that leads the output of the input inverter to an output pad for external connection. A first resistor and a capacitor connected in series are connected between the V_C_C line and the output line l of the input inverter, with the resistor facing the V_C_C line, and the gate of the P-channel transistor is connected. is connected to the connection point of the first resistor and the capacitor, the drain of the transistor is connected to the V_C_C line, the source of the transistor is connected to the line I, and a series connection is made between the line I and the ground line. The second connected
A resistor and a capacitor are connected with the resistor facing the ground line, the gate of an N-channel transistor is connected to the connection point of the second resistor and the capacitor, and the drain of the transistor is connected to the line l. An output noise suppression circuit characterized in that the source of the transistor is connected to the ground line. (2) The output line l_1 of the NAND circuit and the output line l_2 of the NOR circuit are respectively connected to the gates of the P-channel and N-channel transistors in the output inverter, and the NAND circuit is connected to the output signal from the chip. , and an inverted signal of a three-state control signal are input to the NOR circuit, and the output signal and
A three-state control signal is input, and when the three-state control signal is L, the output pads are switched on to H and L in response to the H and L output signals, and when the three-state control signal is H, , a circuit added to a three-state output buffer whose output pads are switched off from H and L, the circuit including a first resistor and a capacitor connected in series between the line l_1 and the ground line; The gate of the N-channel transistor is connected to the connection point of the first resistor and capacitor, and the drain of the transistor is connected to the ground line l_1.
A second resistor and a capacitor are connected in series between the V_C_C line and the line l_2, and the source of the transistor is connected to the ground line.
At the same time, the gate of the P-channel transistor is connected to the connection point of the second resistor and capacitor, and the drain of the transistor is connected to the V
_C_C line, and a source of the transistor is connected to the line l_2.