JPH02205324A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit having a high degree of integration and excellent operating characteristics by collecting the threshold voltage of MOS type elements in one integrated circuit within a tolerance even when electron beam lithography is adopted for forming an internal wiring, etc. CONSTITUTION:The internal wirings of an integrated circuit including MOS type elements (FETs) 1 are formed through lithography selectively applying a high energy beam such as an electron beam, ion beam, x-rays, gamma-rays or the like, and a high energy beam is applied only by quantity collecting the distribution of the threshold voltage Vth of the FETs 1 within a range required for imparting specified characteristics into an integrated circuit region containing a region not exposed to a high energy beam in a lithography process. The Vth of the FETs 1 after heat treatment can be converged within a tolerance regarding the Vth of the FETs 1 in the integrated circuit of a lot at that time when dosage is brought to 5X10<-4>C/cm<2> or more. Accordingly, the dispersion of Vth can be eliminated, thus further improving the degree of integration of the integrated circuit.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a processing method for adjusting the threshold voltage distribution of a MOS type element in a MOS type integrated circuit, and the present invention relates to a processing method for adjusting the threshold voltage distribution of a MOS type element in a MOS type integrated circuit. The first aspect of the present invention is to narrow down and realize predetermined characteristics of an integrated circuit, and the first aspect of the present invention is to form internal wiring of an integrated circuit including MOS type elements using high-frequency radiation such as electron beams, ion beams, X-rays, or γ-rays. The threshold voltage of the MOS type device is determined by irradiating an integrated circuit area including a region not exposed to the high-energy beam in the lithography process with the high-energy beam after performing lithography in which energy beams are selectively irradiated. The distribution of
The second aspect of the present invention is a configuration including convergence within a range required for imparting predetermined characteristics to the integrated circuit. When carried out by lithography that selectively irradiates radiation, the MO generated by irradiation/non-irradiation with the high-energy radiation
This configuration includes introducing impurities in advance into the element region of the integrated circuit in accordance with the amount of high-energy radiation exposure so as to compensate for the dispersion of the threshold voltage of the type 5 element.

[Industrial application field]

The present invention relates to a processing method for adjusting the threshold voltage distribution of a MOS type element in a MOS type integrated circuit, and in particular, to deal with the dispersion of the threshold voltage of the MOS element caused by lithography using high energy radiation, and to adjust the distribution range of the threshold voltage of the MOS element. It is related to the processing method that narrows the

The miniaturization of elements and wiring is essential for higher integration of integrated circuits, and it is necessary to rely on lithography that uses short wavelength energy beams such as electron beams and X-rays to realize these fine patterns. This is widely recognized by those skilled in the art.

However, integrated circuits are made using field-effect devices (typically M
When constructed using OS transistors (hereinafter referred to as FETs), there is a difference in device operating characteristics, especially threshold voltage and mutual conductance, between FETs that have been irradiated with high-energy rays during lithography processing and FETs that have not. There is a problem that occurs.

This situation is schematically shown in FIGS. 5(a) and 5(b). As shown in FIG. 5(a), the substrate 5 on which the FET is formed
An AN layer 53 and a resist layer 54 are deposited on the substrate 1 with an insulating layer 52 interposed therebetween, and are selectively irradiated with an electron beam. If the resist is n-type, developing it will leave only the area irradiated with the electron beam, so if you use this as a mask to selectively etch the A2 layer, the A1. Wiring 53'
is formed.

With the above processing, the electron beam exposed FET22 and non-irradiated FET23
There are differences in characteristics between the two. FE within one integrated circuit
If there are variations in the T threshold, etc., elements may turn on or off.
The off timing becomes uneven, causing circuit delays and malfunctions.

This problem is particularly noticeable in electron beam lithography, where crystal defects occur in the St single crystal that is the FET forming substrate due to electron beam irradiation, and the energy level of the crystal defects is
It is believed that this affects the operating threshold of

As a treatment to eliminate such levels, the integrated circuit board is heated in a hydrogen atmosphere. For example, by heating the integrated circuit board to 1000°C in Hz Nz,
~ The above level completely disappears. However, such high-temperature processing cannot be performed after the A2 wiring is formed, and there is a need for a processing method that eliminates defect levels without exposing the substrate to high temperatures.

[Conventional technology]

To recover from damage caused by exposure to electron beams, A1. The substrate after wiring formation is heated to 400 to 500° C. in an Hz Nz atmosphere. Although this low-temperature treatment does not completely eliminate defect levels, it has been thought that it restores device characteristics to an extent that is acceptable for practical use.

[Problem to be solved by the invention]

However, as a result of detailed tests and studies conducted by the inventors, it has been found that although the mutual conductance of the FET is completely recovered by the above-mentioned low-temperature heat treatment, a non-negligible difference remains in the threshold voltage (vtb). found.

To give a specific example, in an integrated circuit composed of FETs with a gate length of 0.8 μm, A! During wiring patterning, there is a difference in V of about 0.1 .mu. between FETs that are irradiated with electron beams and FETs that are not irradiated with electron beams.

If the device size is large, this difference can be corrected in advance at the device design stage, but in the case of a minute device such as a submicron device, 1. Even if the variation in V is small and the above degree is large, the relative ratio is large and the area tolerance in device design is also small, so it cannot be dealt with by such processing alone. It becomes something that does not exist.

An object of the present invention is to maintain the V voltage of MOS type elements in one integrated circuit within an allowable range even when electron beam lithography is adopted for forming internal wiring etc. in the formation of integrated circuits including MOS type elements. The object of the present invention is to provide a processing method for integrating semiconductor devices into semiconductor devices, thereby realizing a semiconductor integrated circuit with a higher degree of integration and excellent operating characteristics.

[Means to solve the problem]

In order to achieve the above object, the first aspect of the present invention is to selectively use high-energy beams such as electron beams, ion beams, X-rays, or γ-rays to form internal wiring of integrated circuits including MOS type elements. irradiating the integrated circuit area, including areas not exposed to the high-energy radiation in the lithography process, to the extent required to impart the desired properties to the integrated circuit. M.O.S.
The high-energy beam is irradiated in an amount that aggregates the distribution of the threshold voltage of the MOS type element. When carried out by lithography that selectively irradiates the high-energy beam, the MO generated by irradiation/non-irradiation with the high-energy beam
In order to compensate for variations in the threshold voltage of the S-type element, impurities are introduced in advance into the element region of the integrated circuit in an amount corresponding to the amount of exposure to the high-energy radiation.

[For production]

FIG. 4 is a diagram illustrating the situation in which the Vtk of the FET changes before and after the irradiation, as well as during subsequent heat treatment, when a MOS type integrated circuit is selectively irradiated with an electron beam, using actual measured values. This measurement forms an n-channel FET and determines the state of the substrate surface as A! Three wafers from the same lot, which were similar during wiring formation, were irradiated with electron beams at different doses as described later, and then heat treated at 450° C. in H, -N.

In the figure, the mark is the VLh of the FET before electron beam irradiation,
For all three wafers with different doses, 0.5
Since the voltage is distributed in an extremely narrow range of around 2V, the variation in voltage from wafer to wafer can be ignored.

I Xl0-'C/cmz (7) for the first wafer
When the electron beam was irradiated with an amount of t'-z, Vth was centered around approximately 0.08V, as shown by the X mark in the figure.
The value varied over a wide range, but by applying the heat treatment described above, the value recovered to a value within a rather wide range centered around 0.46 square, as indicated by the circle in the figure.

The dose of the electron beam to the second wafer is 5×10−
'C/cm'', but in this case after irradiation (7) V
t h changes to about 0.02V and decreases to 0.02V by heat treatment.
It has recovered to around 43V. Furthermore, the dose of the electron beam for the third wafer is IXl0-'C/cm'', but in the second case the V after irradiation changes to about 0.02V,
It was restored to about 0.44 V by heat treatment.

From the above actual measurement data, F
It can be seen that when the dose of ET is 5X10-'C/cn+'' or more, the value of FET after heat treatment converges to a substantially constant value.
cm'', the Vth after recovery is closer to the initial value, and it is estimated that the influence of electron beam irradiation remains in proportion to the dose.

The present invention is based on the above-mentioned novel findings, and in the first invention, after performing a lithography process using a high-energy beam, for example, an electron beam, an element that has not been irradiated with an electron beam in the process. By additionally irradiating the formation region with an electron beam, the damage of the FET after heat treatment is brought to an acceptable range.

At this time, the electron beam may be selectively irradiated only to the area not irradiated with the electron beam at the beginning, but the entire wafer may be additionally irradiated with the electron beam. This method utilizes the fact that when the amount of exposure exceeds a specific value, the value of V after the change converges to a relatively narrow range.

The second invention is a process that is effective when the electron beam irradiation is relatively weak and the V of the FET is distributed in proportion to the exposure, and it is possible to predict the amount of change in V that varies depending on the electron beam exposure. However, by increasing or decreasing the channel doping amount of the FET in accordance with the predicted value, the flaw is finally converged to a predetermined range.

It is well known to those skilled in the art that the strength of a FET is affected by the impurity concentration in the channel region, and channel doping is the process of adding impurities to the channel region by a method such as ion implantation in order to adjust Vth to a predetermined value. It is to introduce. Usually boron (B) is used for n-channel FETs.
) is doped, and if the amount of B doped is increased, ① shifts to the positive side.

As mentioned above, when the amount of electron beam irradiation increases, V shifts to the negative side, so in regions where the amount of electron beam irradiation is greater, increasing the amount of B doping reduces the FET of the entire wafer. It is possible to converge the distribution of the current to a narrower range.

〔Example〕

FIG. 1 is a schematic diagram showing the processing of the first invention corresponding to claim (1). In the same figure, the rectangle with symbol 1 indicates an FET, which is an n-channel FE that constitutes an integrated circuit.
Assume that T is arranged in a matrix as shown in the figure.

As shown by diagonal lines in Figure (a), when an electron beam exposure area 2 occurs during patterning for forming Af wiring, the irradiation area 3 to which electron beam irradiation is additionally applied is shown in Figure (b). As shown by diagonal lines, the area may be complementary to the shaded area in FIG.

In order to perform additional electron beam irradiation in a complementary manner as shown in the figure (B), it is possible to invert and use the electron beam irradiation data for lithography. In the case of irradiation, it is also possible to use X-ray irradiation instead. No matter which process is adopted, there is no need to prepare a new mask.

The following experiment was conducted to clarify the effects of the above example.

A MOS type integrated circuit including a FET with a channel length of 1 μm is formed using a normal process including An wiring formation by electron beam lithography, and the chips are divided into two groups and one group of chips is subjected to an acceleration voltage of 30 KeV and a dose of I. Xl0-'C
/cm", and the other groups of chips were irradiated with an electron beam of 4 cm in Hz Nz without additional irradiation.
Heat treatment was performed at 50°C.

As a result, the V distribution of FETs in each chip was as shown in the histogram of FIG. 2. In the figure, (a) shows the FET of the chip without additional irradiation.
In contrast, the FET of the chip subjected to additional irradiation has a narrow distribution as shown in (b). as,
All FETs are concentrated in a relatively small area.

The above results show that by additional irradiation with the electron beam, the FET's vt
This shows that the b distribution can be converged within a predetermined range.

Next, a second embodiment corresponding to claim (2) will be described. Since the process of this embodiment also relates to the process of forming an FET, it will be explained according to the process of manufacturing an n-channel FET shown in FIGS. 3(a) to 3(e).

In FIG. 3(a), a P-type St substrate 11 has a 0.8 μm SiOz film 12 formed by selective oxidation and a 0.8 μm thick SiOz film 12 formed by thermal oxidation.
A gate insulating film 13 of 0 rv is formed, and a resist layer 14 is further selectively provided. When B is ion-implanted into this under the conditions of 40 K e V and 3 The area is injected.

Next, the resist layer 14 is peeled off, and as shown in FIG.
40 K e V, l XIO"cm-
B is ion-implanted again under the conditions of ``.This ion-implantation process corresponds to normal channel doping, but as a result of the previous ion implantation, a higher concentration of B is doped into the device region that will later be irradiated with an electron beam. It means that it was done.

Next, as shown in the same figure (C), poly-Si
Formation of gate 15, S/ by ion implantation of n-type impurity
Formation and heat treatment of D region 16, deposition of first insulating layer 17 and opening of contact window, formation of contact electrode 18,
Complete the FET.

Thereafter, as shown in FIG. 4(d), a second insulating layer 19, a /1 layer 20, and a resist layer 21 are formed and developed by selectively irradiating with an electron beam. The conditions for electron beam irradiation are 20 K.
e V, 5
0' is formed.

The substrate was coated with a protective oxide film (not shown), and H, -N
, by performing heat treatment at 450''C, FET22 in the electron beam exposed region and FET2 in the low channel doped region
3 and ■The variation is ±0. It is formed as an element with close characteristics within the OIV. On the other hand, when the channel doping amount is made uniform, the variation in V is ±0.04
It also reaches V.

When forming an integrated circuit having two layers of upper wiring, that is, when electron beam irradiation is required twice, in addition to the above treatment, I
By performing B ion implantation of O"cm-",
As in the above embodiment, the variation in voltage was ±0. We were able to keep it within OIV. When the channel doping is changed to two stages for two times of electron beam irradiation, the variation in
0.02V, and the variation in V was ±0.05V when no change was made.

As already mentioned, the amount of change in V due to exposure to electron beams tends to be saturated, so by adjusting the amount of channel doping in about three steps, the FET's
It is possible to converge the problem.

An example of processing conditions when the FET is a p-channel is as follows. The substrate is n-type, the thickness of the gate oxide film is 20 nm,
When the gate electrode is made of n-type polySt, B ion implantation is performed as a channel dope at 40KeV, 5XIO"cm-
An additional implantation of 40 KeV, 3 XIO cm - was performed in the region subjected to electron beam irradiation in the lithography. This process yielded good results similar to those of the n-channel case.

In addition, an example of processing when lithography is performed using X-rays instead of electron beams is as follows.The X-rays are sourced from a baradium target and an electron beam impact power of 10KW.
When the exposure condition is 500 mJ/cm", B ion implantation as in the above example results in lXl0"cm-" (
7) Channel F-ft X'lA to area covered by 3x10
By performing additional doping of "cn+-", the variation in Vtk becomes ±0.01 V or less.When no additional doping is performed, the variation in Vtk is ±0.035 V.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to eliminate the variations in density caused by exposure to high-energy radiation during lithography processing, so finer patterns can be used and the degree of integration of integrated circuits can be increased. It becomes possible to improve the performance.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram showing the process of the first invention, and Figure 2 is a schematic diagram showing the process of the first invention.
Figure 3 is a diagram illustrating the process of the second invention, Figure 4 is a diagram showing the effect of the invention of FE.
Figure 5 is a diagram showing the state of change in T, and Figure 5 is a diagram showing the electron beam exposure state of FET. In the figure, 1 is the FET. 2 is an electron beam exposure area, 3 is an additional irradiation area, 11 is a p-type St substrate, 12 is a SiOg film, 13 is a gate insulating film, 14 is a resist, 15 is a poly-Si gate, 16 is an S/D area, 17 is a Insulating layer, 18 is contact electrode, 19 is insulating layer, 20 is /1 layer, 20' is A2 wiring, 21 is resist, 22 is exposed FET. 23 is a non-irradiated FET. 51 is a Si substrate, 52 is an insulating layer, 53 is a /1 layer, and 54 is a resist. Fig. 2 shows the effect of the first invention Fig. 4 shows the VL & transition situation of FET Fig. 4 A schematic diagram showing the processing of the first invention Fig. 1 Illustrative diagram Figure 3 (Part 1)

Claims (2)

[Claims] (1) After forming internal wiring of an integrated circuit including a MOS type element by lithography that selectively irradiates with high-energy rays such as electron beams, ion beams, X-rays, or γ-rays, In an integrated circuit area including a region not exposed to high-energy radiation, the amount of said MOS type elements is concentrated to be within the range required to impart predetermined characteristics to said integrated circuit. A method for manufacturing a semiconductor device, characterized by irradiating it with high-energy radiation. (2) When internal wiring of an integrated circuit including a MOS type element is formed by lithography that selectively irradiates the high-energy beam, the MO generated by irradiation/non-irradiation with the high-energy beam;
A method for manufacturing a semiconductor device, characterized in that an amount of impurity corresponding to the amount of high-energy radiation exposure is introduced into the element region of the integrated circuit in advance so as to compensate for the dispersion of the threshold voltage of the S-type element.