JPH02205115A - Semiconductor circuit device - Google Patents

Abstract

PURPOSE:To miniaturize a MOS transistor and to attain fast and low power consumption by setting the highest voltages to be applied on a BiCMOS logic circuit and between the source and drain of the MOS transistor comprising the CMOS logic circuit less than a source voltage, and also, setting all of them at the same level. CONSTITUTION:When an input voltage goes to a high level and a load charging bipolar transistor(BTR) 13 is turned off, the MOS TR 15 is turned on, and the voltage at the base terminal of the BTR 13 goes to (VBE). The drain terminal of the MOS TR 11 is connected to the base terminal of the TR 13, and the voltage at the drain terminal of the MOS TR 11 goes to VBE. Since the source voltage VCC is applied on the source terminal, the voltage less by VBE than the source voltage VCC is applied between the source and drain of the MOS TR 11. When the input voltage goes to a low level and the BTR 13 is turned on, the output voltage goes to a value VCC-VBE less by the base/emitter forward directional voltage V of the BTR 13 than the source voltage VCC.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor circuit device, and more specifically to a semiconductor circuit device having a composite circuit of MOS transistors and bipolar transistors or a MOS-driven bipolar output type logic circuit. Related to circuit devices.

[Conventional technology]

Conventionally, various composite circuits (IlkiCMOS circuits) that utilize the low power consumption of CMOS transistors and the high load driving ability of bipolar transistors have been considered.

One of them, as shown in Figure 5, was published by VEE Transactions on Electron Devices, Volume 16, No.
E-transaction ON ELECTRON
DEVICES, VOL, ED-16, &11. NO
This is the circuit shown in Fig. 8 of V, 1'9g9ri P2S5). In the tIl, 1 is PMOS
￥MOS transistor゛□Source is connected to power supply +V, gate is connected to input terminal IN, drain is NPN transistor 3
connected to the base of

2 is an NMOS transistor whose drain is connected to the output terminal OUT, whose gate is connected to the input terminal IN, and whose source is connected to the base of the NPN transistor 4.

The collector of the NPN transistor 3 is connected to the power supply Vc, and the emitter is connected to the output terminal OUT.

The collector of the NPN transistor 4 is connected to the output terminal OUT, and the emitter is connected to the common potential point or ground potential point (GN
D).

The operation of this circuit is as follows. Now input terminal IN
When is low level (11L I+ level), NMOS
Transistor 2 is turned off and NPN transistor 4 is also turned off. On the other hand, the PMOS transistor 1 is turned on, and the base current is supplied to the NPN transistor 3 through the PMOS transistor 1.
turns on.

As a result, the load (not shown) from the NPN transistor 3 is
A charging current flows to the output terminal OUT, and the output terminal OUT becomes a high level (1
1H" level). Next, the input terminal IN is set to "
When the level is "H", PMOS transistor 1 is turned off and NPN transistor 3 is also turned off.
The MOS)-run lister 2 is turned on, the base current is supplied to the NPN transistor 4 through the NMOS)-run lister 2, and the NPN transistor 4 is turned on. As a result, the charge stored in the load is discharged through the NPN transistor 4, and the output terminal OUT becomes ll L
Switch to level 11. The output voltage level of this circuit is shifted by the base-emitter voltage V BEQI TV BEQ2 of the NPN)-run listers 3, 4. That is, the "H" level becomes (Vc - VBEQI), and the "IJL" level becomes V BEQ2.

Incidentally, with the ultra-high integration of LSIs, reducing power consumption has become a major issue, and as a countermeasure to this problem, it is considered inevitable to lower the internal mold original voltage (3.3 V or less).

As described above, in the B i CM OS gate circuit, the logic amplitude is reduced by about 1.6V due to the level shift of the output voltage. For this reason, when the power supply voltage becomes low, the ratio of the logic amplitude to the power supply voltage becomes extremely small, and the primary stage MOS gate circuit or B1CMOS gate circuit cannot be driven sufficiently, and the delay time tp- suddenly increases.

On the other hand, complementary MOS (hereinafter referred to as CMOS) is composed of an N-channel MOS transistor and a P-channel transistor.
It is called. ) Since there is no level shift of the output voltage in the gate circuit, the delay time increases even if the power supply voltage becomes low.
CMOS gate circuits are not very large. For this reason, for example, at a power supply voltage of 3.3■, the B1CMOS gate circuit is
It is not as fast as an S gate circuit, and on the contrary, a CMOS gate circuit is expected to be faster at a lower power supply voltage.

On the other hand, as shown in Japanese Patent Laid-Open No. 59-205828, for example, there is a logic circuit composed of a composite circuit consisting of a MOS transistor and a bipolar transistor, which has the same function as this logic circuit, and By connecting the logic circuit in parallel with another logic circuit made up of MOS transistors, the output signal can be completely reduced to llL level or ``H'' level.
``There are things that are configured to be on the level.

[Problem to be solved by the invention]

According to the circuit of the prior art, the input capacitance of the circuit increases compared to that of a logic circuit composed only of composite circuits, so this increase in human power capacitance increases the input capacity of the circuit in the previous stage in order to The problem is that the speed decreases, and ultimately the overall speed decreases.

The purpose of the present invention is to reduce the power supply voltage even when the glA ll+ voltage of the transistor becomes low due to the reduction in the power supply voltage (3.3 V or less).

+3 with sufficient high speed compared to CMOS gate circuit
An object of the present invention is to provide a semiconductor circuit device having an i CM OS gate circuit.

[Means to solve the problem]

A feature of the present invention is that in a composite circuit of an 11ic MOS logic circuit and a CMOS logic circuit, the forward voltage of the diode is used to match the high level of the output voltage with the high level of the input terminal, and the MOS forming the logic circuit The maximum voltage applied between the source and drain of the transistor should be lower than the power supply voltage.

And they are all equal.

Another feature of the semiconductor circuit device of the present invention is an N-channel MOS
One or more bipolar transistors are added to a CMOS inverter circuit consisting of transistors and P-channel MOS transistors.In a CMOS/bipolar composite circuit, the high level voltage of the output signal matches the high level voltage value of the input signal. The power supply voltage is set higher than the high level voltage of the input signal so that the Mo5t-run lister source that drives the bipolar transistor is set.
The highest voltage applied between the trains and between the source and gate is set to the high level voltage of the human input signal.

[Effect]

In the 13i CMOS logic circuit, it was connected to the base of a bipolar transistor Q13 for charging the load. A diode in series with the base charge extraction MOS transistor M15! ] 17 are provided. The forward voltage of the diode is the base voltage of the bipolar transistor Q13.
Equal to emitter forward voltage VIE.

When the input voltage becomes high level and the load charging bipolar transistor Q13 turns OFF, the base charge extracting MOS transistor M15 turns ON, and due to the forward voltage of the diode D17 connected in series with it, the bipolar transistor Q13 turns OFF. Tran.

The voltage at the base terminal of Lister Q13 is VBE.A MOS transistor for driving a bipolar transistor.
The drain terminal of M is connected to this base terminal, and M
The voltage at the drain terminal of the OS transistor is also VaI! bawl. Since the power supply voltage Vc is applied to the source terminal, a voltage lower than the power supply voltage Vc by VBE is applied between the source and drain of the MOS transistor 11.

When the input voltage becomes low level and the load charging bipolar transistor Q13 is turned on, the output voltage becomes a value Vc-VBE lower than the power supply voltage Vc by the base-emitter forward voltage VBE of the bipolar transistor. The drain terminal of the MOS transistor 12 that drives the load discharge piponilla transistor Q14 is connected to the output terminal, and the voltage at the drain terminal is also Vc-VIE. At this time, since the MOS transistor 16 which extracts the base charge of the load discharging bipolar transistor Q14 is ON, the potential of the source terminal of the MOS transistor 12 becomes Ov. Therefore, the voltage applied between the source and drain of the IMOS transistor M12 is also Vc - VBE
becomes.

In a CMOS inverter circuit composed of a PMOS transistor and an NMOS transistor, the source terminal of the PMOS transistor is connected to the cathode terminal of a diode, and the anode terminal of the diode is connected to a power supply voltage Vc. Set the forward voltage of the diode to VBE. This allows PMOS.

When the NMOS is OFF, a voltage of Vc - VBE is applied between each source and drain.

As mentioned above, by making the source-drain size of the MOS transistors constituting BiCMOS logic circuits and CMOS logic circuits the same and lower than the power supply voltage, the MOS transistors can be made smaller (gate (length, gate oxide film, etc.), high speed and low power consumption can be achieved.

If the voltages applied between the source and drain of the MOS transistor are different, the MOS transistor must be designed to withstand the largest voltage, which makes it impossible to reduce the size of the transistor, making it impossible to achieve high speed and low power consumption.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, 11 is a PMOS transistor whose source is connected to a power supply. The power supply voltage Vcc is the input signal I
The base-emitter forward voltage VBε (approximately 0.8 V) of the NPN transistor 13 driven by the PMOS transistor 11 is set higher than the IH'' level.

20 is a limiter circuit that applies 5V to the input terminal INo.
The voltage drops to Vcc (4.2V) by the 18-pin diode. Further, the 5V supplied to the input terminal INo passes through the diodes 18' and 19 and drops to approximately 3.4V, and is supplied to the input signal circuit 21, where it is output as an "H" level signal (approximately 3.4 V) or "L" level signal. A level signal is supplied to input terminal IN. The gate of the PMOS transistor 11 is connected to the input terminal IN, and the drain is connected to the base of the NPN transistor 13. 12 is an NMOS transistor, the drain is connected to the output terminal OUT, the gate is connected to the input terminal IN,
The source is connected to the base of NPN transistor 14. The collector of the NPN transistor 13 is connected to the power supply +V, and the emitter is connected to the output terminal OUT. NPN
)-The collector of the run lister 14 is connected to the output terminal OUT, and the emitter is connected to the ground potential point (GND).

Reference numeral 15 is a base charge extracting NMOS transistor whose drain is connected to the base of the NPN transistor 13, whose gate is connected to the input terminal, and whose source is connected to the anode side of the diode 17. The cathode side of the diode 17 is connected to GND. 16 is a base charge extracting NMOS)-run lister whose drain is connected to the base of the NPN transistor 14, its gate is connected to the output terminal, and its source is connected to GND. 22 is a load.

The operation of this circuit is as follows. Input terminal IN is “L”
+t level, NMOS transistor 12 is OFF
, and the NPN transistor 14 is also turned off. On the other hand, the PMOS)-run lister 11 is turned on, and the PMOS
A base current is supplied to the NPN transistor 13 through the transistor 11, and the NPN)-run lister 13 is turned on.
becomes. As a result, the load 2 is transferred from the NPN transistor 13.
2 flows, and the level of the output terminal OUT becomes (+
V-VBE: the input signal's ll HI+ level voltage).

The charge extraction NMOS 16 turns on before the output terminal reaches the LL HI+ level, and the NPN transistor 14
The charge stored at the base of flows through it to GND. Therefore, the NPN transistor 14 is completely turned off.
The time it takes for the output voltage to reach the ll HI+ level can also be shortened.

When the 11L” level of the input signal is Ov, the PM
When the OS transistor 11 is on, a voltage equal to the IIH" level of the input signal plus VBE is applied between the gate and source. Normally, the withstand voltage between the gate and source is designed to be higher than this, so there is no problem. If this is likely to be a problem, the input signal It L 13 level may be set to Vap, and the design may be made such that PMOSII is turned on even with the gate voltage Vag.

Next, when the input terminal IN is at II HIT level, PM
The OS transistor 11 is turned off, and the NPN transistor 13 is also turned off. On the other hand, the NMOS transistor 12 is turned ON, and the base current is supplied to the NPN transistor 14 through the NMOS transistor 12.
The PN transistor 14 is turned on. As a result, load 2
The charges stored in the NPN transistor 14 are discharged through the NPN transistor 14 until the level of the output terminal OUT reaches the base-emitter forward voltage VBE of the NPN transistor 14! Current flows, but after that the NPN transistor 14 is cut off. That is, the LI L 11 level of the advancement terminal OUT becomes VBE.

When the PMOS transistor 11 is turned off, the source of this transistor is (input signal 'H' level + VBB
) voltage is applied. Turning off PMOS transistor 11
At the same time, the PMOS transistor 15 turns on, so the drain potential of the PMOS transistor 11 would be Ov if there was no diode 17, but
7, it becomes equal to the forward voltage Vo of this diode.

Therefore, if you design it so that vBE=VD, PMO
Only the II Hlj level of the input signal is applied between the source and drain of the S transistor 11. That is, the highest voltage applied between the source and drain of the MOS transistor can be set to the ``H'' level of the input signal.

FIG. 2 shows the input/output characteristics of the conventional composite circuit shown in FIG. 5 and the composite circuit according to the present invention shown in FIG. In the figure, the broken line indicates the input/output characteristics of the conventional circuit, and the power supply voltage is Vc. The solid line shows the input/output characteristics of the circuit according to the present invention, and the power supply voltage Vcc=VC+VBE. This second
As can be seen from the figure, in the composite circuit of the present invention, the output 11H7 level can be switched up to the "H" level of the input signal, and the ztL" level can be switched up to VIE, making it possible to increase the logic amplitude and increase the speed compared to the conventional circuit.

Figure 3 shows the circuit of the present invention shown in Figure 1 and the B circuit shown in Figure 5.
iCMOS basic gate basic length - 8 circuit This shows the dependence of the delay time of the S gate circuit on the power supply voltage.In the circuit of the present invention, even if the power supply voltage Vc becomes 3.3 V or less, the CMOS
Sufficient high speed performance is achieved compared to gate circuits.

Furthermore, even when the value of the power supply voltage is the same between the circuit of the present invention and the conventional circuit, the maximum voltage applied between the source and drain of the MOS transistor constituting the circuit of the present invention is only VBE compared to that of the conventional circuit. Since it is small, the MOS transistor can be designed to be small, so high speed and low power consumption similar to that shown in FIG. 3 can be achieved.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. The circuit on the left side of the broken line indicated by 100-100' in FIG. 0 is exactly the same as the embodiment shown in FIG. That is, the gate circuit shown in the embodiment of FIG. 1 drives the CMo5 inverter circuit on the right side of the broken line 100-100'. 101 is a PMOS transistor, and 102 is an NMOS transistor. 103 is a diode with a forward voltage drop VBε, and the P important region side is connected to the power supply Vcc, and the power supply voltage is the "H" L/bevel of the input signal supplied to the input terminal IN (approximately 3.4 V). The VBE is set higher than that of the previous model. 1o4 is the load.

The operation of this circuit is as follows. Input terminal IN is “L”
” level, the output terminal 0UT1 has the ``H'' level of the input signal.
"Level voltage (approximately 3.4 V) appears. At this time, PM
OS transistor 101 is OFF, NMOS transistor 5:z-
When the lister 102 is turned on, the charge stored in the load 104 is discharged through the NMOS transistor 102, and the potential of the output terminal OUT2 falls to the GND potential.

Next, when the input terminal IN is at “H” level, the output terminal 0
UT2 becomes "L" level, that is, Vap.

At this time, the NMOS transistor 102 is turned off, and the PMOS
Transistor 101 is turned on. Then, a charging current flows to the load 104 through the PMOS transistor, and the level of the output terminal 0UT2 rises to (Vcc-VaI!="H" level voltage of the input signal).

Also, the highest voltage applied between the source and drain of the MOS transistor is the "H" level voltage of the input signal (approximately 3
．． 4 V), the MOS transistor can be designed to operate with the highest performance at this voltage.

FIG. 6 shows an example of the cross-sectional structure of a device applied to the CMOS/Polar composite circuit of the present invention.
In the figure, 300 is a P-type substrate, on which N÷buried layer 301. A P/buried layer 302 is formed, and an N-type epitaxial layer 303 (NWELL) is formed thereon. Reference numeral 304 denotes PWELL, in which the N-type epitaxial layer formed on the P◆ buried layer is made into P-type by ion implantation of boron or the like.

The NMOS transistor has a PWELL 304 as a substrate, a source and a drain formed of the N◆10 layer 06, and a gate formed of polysilicon 309. PMOS
The transistor is NWELI.

With 303 as a substrate, the P soil layer 308 is used as a source.

A drain is formed, a gate is formed of polysilicon 309, 310 is an electrode on the cathode side of the diode, and a P soil layer 318 is the anode of the diode.

The NPN transistor is a vertical NPN transistor in which the NWELL 303 is the collector, the P base diffusion layer 305 is the base, and the N soil layer 307 is the emitter.

〔Effect of the invention〕

According to the present invention, when the source-drain breakdown voltages of the MOS' transistors constituting the logic circuit are the same, the internal power supply voltage can be made higher than in the conventional circuit, thereby increasing the logic amplitude and increasing the speed.

Furthermore, even when the same internal power supply voltage is used, in the present invention, the maximum voltage applied between the source and drain of the MOS transistor that drives the bipolar transistor of the BiCMOS logic circuit is CMOS
It can be made equal to the maximum voltage applied between the source and drain of the MOS transistor of the logic circuit, and can be made smaller than the internal power supply voltage. Therefore, these MOS transistors can be designed to be small (gate length, gate oxide film, etc.), resulting in higher speed and lower power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the first embodiment of the present invention, FIG. 2 is an input/output characteristic diagram of the circuits shown in FIGS. 1 and 5, and FIG.
Fig. 5 is a characteristic diagram showing the relationship between the delay time and power supply voltage of the circuit of Fig. 5 and the CMOS gate circuit, Fig. 4 is a circuit diagram showing the second embodiment of the present invention, and Fig. S is a conventional CMOS/bipolar composite circuit. A diagram showing an example of a circuit, FIG. 6 is a CMO according to the present invention.
1 is a cross-sectional view of a device structure showing an example of a device applied to an S-bipolar composite circuit. 11.101...PMOS transistor, 12°10
2...NMOS transistor, 13.14...NP
N bipolar transistor, 15.16...Base charge extraction MOS transistor, 17゜18゜19゜103...Diode, 22゜Fig. N (V) 100'

Claims (1)

[Claims] 1. N-channel MOS transistor and P-channel MOS
A CM in which one or more bipolar transistors are added to a CMOS inverter circuit composed of transistors.
In the OS/bipolar composite circuit, the power supply voltage is set higher than the high level voltage of the input signal so that the high level voltage of the output signal matches the high level voltage value of the input signal, and the bipolar transistor is driven. A semiconductor circuit device characterized in that the highest voltage applied between the source and drain and between the source and gate of a MOS transistor is set to a high level voltage of an input signal. 2. a first terminal receiving a power supply voltage; a second terminal receiving a common potential; input terminal means receiving at least one input signal; first means for outputting one first signal; one or more bipolar transistors; and output terminal means connected to the collector or emitter of the bipolar transistor; switching between the first terminal and the second terminal in response to a signal, and providing a first electrical connection between the first terminal and the output terminal or between the second terminal and the output terminal; In the complementary MOS/bipolar composite circuit, the complementary MOS/bipolar composite circuit includes: a switching means for forming a connection between the base of the bipolar transistor and the second terminal; and a base charge extraction means for connecting the base of the bipolar transistor and the second terminal; or provided in series with the base charge extraction means between the base of the first bipolar transistor whose collector is connected to the first terminal and the second terminal, and when the base charge extraction means operates, The first bipolar transistor has a potential raising means that operates to raise the potential higher than the second terminal by the base-emitter forward voltage V_B_E, and the power supply voltage V supplied to the first terminal. is higher than the high level voltage of the first input signal.
A semiconductor circuit device that is characterized by its high cost. 3. The semiconductor circuit device according to claim 1, wherein a diode having a forward voltage equal to the V_B_E is connected in series with the base charge extracting means as the potential raising means. 4. In a circuit combining a complementary MOS/bipolar logic circuit and a complementary MOS logic circuit constituted by a MOS transistor and a bipolar transistor, the source of the MOS transistor for driving the bipolar transistor connected to the base terminal of the bipolar transistor is connected to the base terminal of the bipolar transistor. MOS between the drains and forming the complementary MOS logic circuit
A semiconductor circuit device characterized in that the maximum voltage applied between the source and drain of a transistor is lower than the power supply voltage applied to the circuit and is the same for all transistors. 5. In the semiconductor device according to claim 1, the maximum voltage applied between the source and drain of the driving MOS transistor and between the source and drain of the MOS transistor constituting the complementary MOS logic circuit is A semiconductor circuit device characterized in that the base-emitter forward voltage of the bipolar transistor is lower than the power supply voltage applied to the bipolar transistor. 6. In the semiconductor device according to claim 5, a P-channel M connected to the base terminal of the load charging bipolar transistor of the complementary MOS/bipolar logic circuit.
Applying a voltage equal to the base-emitter voltage of the bipolar transistor to the drain terminal of the OS transistor, and applying a voltage equal to the base-emitter voltage of the bipolar transistor to the source terminal of the P-channel MOS transistor of the complementary MOS logic circuit, which is lower than the power supply voltage by the base-emitter forward voltage of the bipolar transistor. By applying a potential, the maximum voltage applied between the source and drain of the bipolar driving MOS transistor and between the source and drain of the MOS transistor constituting the complementary MOS logic circuit can be made lower than the power supply voltage applied to the circuit. A semiconductor circuit device characterized by lowering only the base-emitter voltage of a bipolar transistor. 7. In the semiconductor device according to claim 6, a forward voltage of a diode is used to apply a base-emitter forward voltage of a bipolar transistor to a drain terminal of a P-channel MOS transistor of the complementary MOS/bipolar logic circuit. , and a potential lower than the power supply voltage by the base-emitter forward voltage of the bipolar transistor is applied to the source terminal of the P-channel MOS transistor of the complementary MOS logic circuit.