JPH0220118A - Space dividing switch - Google Patents

Abstract

PURPOSE:To delete the number of elements to constitute a crossing switch and to reduce an energy consumption by providing a common constant current source for crossing switches connected to the same output data line out of the crossing switches. CONSTITUTION:When for example a logic 1 is given to an input terminal 12 of a crossing switch 10-44, a constant current source 11-4 flows only at a transistor Q3 of the crossing switch 10-44 and does not flow at remaining crossing switches 10-14, 10-24 and 10-34. Thus, for differential transistors Q1 and Q2 connected to the corrector of the transistor Q3, the crossing switch 10-44 only becomes active. The action when other crossing switch except the crossing switch 10-44 becomes an active condition is also the same. Consequently, the necessary element per crossing switch may be transistors Q1-Q3 only, an N number of constant current sources is sufficient concerning the energy consumption, and therefore, the low power of 1/N is executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides input data that is spatially expanded by opening and closing a cross-point switch disposed between an input data line and an output data line. This relates to a space division switch that converts and outputs the converted data as output data.

[Conventional technology]

FIG. 4 is a block diagram showing the structure of a conventional synchronous space division switch. In the figure, 1 is a cross-point matrix switch configured in a 4×4 matrix, and 2 is, for example, D
A manual data register composed of latches, 3 is an output data register, 4-14-2.4-3.4-4 are input data highways, 5-1.5-2.5-3.5-
4 are output data highways, 6 is an input terminal for the first synchronization clock CKI, 7 is an input terminal for the second synchronization clock CK2, 8-1. 8-28-3.8-
4 is the manual data line to the cross-point matrix switch 1, 9-
1.9-2.9-3.94 are output data lines.

Next, the operation of the conventional space division switch will be explained with reference to FIG. Input data highway 4-14-2.4-3
．． The data (spatially developed input data) transmitted on 4-4 is latched into the input data register 2. Next, the latched manual data is sent to a cross-point matrix switch 1 configured in a matrix, and based on the open/closed states of the cross-points, is transmitted to an output data register 3 and launched into the register 3. Furthermore, the data launched into the output data register 3 is sent out onto the output data highway 5-1.5-2.5-3.5-4. The launch clock for input data register 2 and output data register 3 is supplied from synchronous clock input terminals 6 and 7.

FIG. 5 is a circuit diagram showing a conventional configuration example of a fork switch. In the same figure, 8 is a manual data line, 9 is an output data line, 10 is an AND gate that receives input data and switch opening/closing data; 11 is a wired OR, and 12 is an input terminal for switch opening/closing data. To explain the operation of the switch, when the logic 1-1 is applied to the input terminal 12, the AND gate 10 is in an active state, and data having the same polarity as the human input data appears at the output, and the data is transmitted. On the other hand, when the logic rOJ is applied to the switch opening/closing data input terminal 12, the output of the AND gate IO is kept at logic "0" regardless of the input data.

Therefore, the wired OR 11 is off, and data from another active cross-point switch (not shown) is transmitted to the output data line 9.

FIG. 6 is a circuit diagram showing an example of a specific transistor circuit configuration of the cross-point switch shown in FIG. The AND gate is constructed using a known current switching (CML) type circuit. , the NPN transistor lid is an emitter follower, and by connecting the emitter to the output data line 9, a well-known wired-OR logic is realized. 13 is a voltage terminal that supplies voltage Vcc (usually ground level), 14 is voltage VEE (5,
2V), 15 is a reference voltage terminal that supplies reference voltage v1, and 16 is a reference voltage terminal that supplies reference voltage V2. Usually the reference voltage V.

is set to the middle voltage of the input data voltage amplitude, and the reference voltage 2 is set to the middle of the switch inch open/close data voltage amplitude.

Next, the operation of the circuit shown in FIG. 6 will be explained. When logic ril (corresponding to switch closing) is applied to input terminal 12,
Differential transistor pair Q3. Transistor Q behind Q4
3 is on and Q4 is off, making it a constant current source! The current of 1 flows through the transistor Q3 and activates the switch of the differential transistor pair Q1 and Q2 connected to the collector of the transistor Q3. This changes the input data to logic “1”.
”, transistor Q1 is on and 02 is off, and when the input data is logic “0”, transistor Ql is off and 02
turns on, and a logic voltage signal with the same polarity as the input data is generated at the resistor R1 with a voltage amplitude r+XI+ (r is the resistance value of the resistor R1, and ■ is the current value of the constant current source 11), and is passed through the emitter follower Q5. A signal having the same polarity as the input data is transmitted to the output data line 9.

When logic "0" (corresponding to open switch) is applied to the input terminal 12, transistor Q3 of the differential transistor pair Q3 and Q4 is off and Q4 is on, and the current of the constant current source 11 flows through the transistor Q4. always resistor R
1, so the base potential of transistor Q5 is Vc
It becomes a low potential of cr+XI+, the emitter follower transistor Q5 is turned off, and no signal is transmitted to the output data line 9.

[Problem to be solved by the invention]

In this way, the conventional cross-point matrix switch is composed of one constant current a, five transistors, and one resistor for one cross-point, and the total cross-point matrix switch of the entire four-man power, four-output space division switch is In this case, 4" = 16 times the number of elements and constant current sources are required. Generally speaking, a space division switch with N inputs and N outputs requires N2 times the number of elements, which requires an extremely large number of elements and increases power consumption. There was a drawback that

The present invention has been made in view of these points, and its purpose is to provide a space division switch with a small number of elements and low power consumption.

[Failure to solve the problem]

To achieve this purpose, the present invention converts and outputs spatially expanded human data by opening and closing a cross-point switch disposed between an input data line and an output data line. In a space division switch that outputs data, a common constant current source is provided for the cross-point switches connected to the same output data line behind the cross-point switches.

[Operation] In the space division switch according to the present invention, cross-point switches connected to the same output data line are driven by a common constant current source.

〔Example〕

In the space division switch according to the present invention, the constant current sources of the cross-point switches connected to the same output data line are common 1, the emitters of the transistors that control switch opening and closing are commonly connected to the constant current source 1, and the collectors of the transistors F are connected in common. Differential transistors for manual data transmission: /... It is best to connect the common emitters of the lid pair, connect the base of the differential transistor pair to the input data line, and the collector to the output data line to form a cross-point switch. 1 essential feature. What is conventional technology?
The point is that there is only one constant current source in multiple cross points connected to the same output data wire, and the data transmission to the output pig wire is not from the emitter follower but from the collector of the differential transistor bare. The difference is that

FIG. 1 is a circuit diagram showing a first embodiment of a cross-point matrix switch constituting a space division switch according to the present invention. In the figure, 8-1.8-28-3.8-4 is an input data line, 9-1.92.1-3.9-4 is an output data line, 1O-ijN=t, 2.3. 4, j=1.2.3
．． 4) is a cross-point switch, 12 is an input terminal for switch opening/closing data, I3 is a power supply terminal that supplies voltage VCC, 14 is a power supply terminal that supplies voltage VEE, 15 is a reference voltage terminal that supplies reference voltage 1, QI Q2 and Q3 are the first.
Second and third transistors, I11□, l l-3
, l 1-1 are constant current sources, and these constitute a 4×4 cross-point matrix switch.

To simplify the explanation, output data line 9-4 (connected cross-point switch 10-14, 10-2110-34)
．． 10-44 will be described below.

Each cross-point switch has a switch opening/closing control transistor Q3 whose base is connected to the input terminal 12, whose emitter is connected to the common constant current source 1.4, and whose common emitter is connected to the co1/coctor of the transistor Q3. It consists of differential VJ transistors Ql and Q2 for input data transmission. The collector of transistor ω1 is connected to the power supply terminal 13,
Its base is input data vA8-1.8-2.8-3.
8-4. The base of the transistor Q2 is connected to the reference voltage terminal 15, and its collector is connected to the other cross-point switches 10-14, 1 (1-24, 1L-31, L
- Commonly connected to the output data line 9-4.

Next, the operation will be explained. For example, the fork switch l O
Logic 1-11 is input to the input terminal 12 of -44,
Remaining cross-point switches to-14, 10-24, 10-3
If logic "0" is given to the input terminal 12 of the constant current source 11, the constant current source 11
-1 flows only to the transistor Q3 of the cross-point switch l〇-44, and the remaining cross-point switches 10-14, 10-24.
It does not flow to 10-34. Therefore, in the differential transistor pair Ql, Q2 connected to the collector of the transistor Q3, only the cross-point switch 10-44 is activated. Here, if the logic on the input data line 8-4 is "L", the transistor Q1 is on and Q2 is off, and the current of the constant current source 11-4 flows from the power supply terminal 13 via the transistor Q1. , no current flows through the output data line 94. If the logic on input data line 8-4 is "0", transistor Q
2 is on and Ql is off, the current of the constant current source 11-4 flows to the output data line 94 via the transistor Q2. Therefore, detecting the current of output data vA9-4,
It is clear that by associating no current with logic "1" and presence of current with logic "0", the data on input data line 8-4 is correctly transmitted to output data line 9-4.

As described above, among a plurality of cross-point switches connected to the same output data line, the logic rlJ is applied to the input terminal 12, the transistor Q3 is turned on, the current of the constant current source flows, and the cross-point switch becomes active. Since there is only one point switch, it is clear that the operation will be the same when other fork switches other than the fork switch 10-44 are activated.

Furthermore, in the above embodiment, the case where the collector of the transistor Q2 is connected to the output data line has been explained.
It is clear that the collector of transistor Q1 may be connected to the output data line and the operation in this case would be similar except that the output data is obtained as the inverse of the input data.

As is clear from such a configuration, the necessary elements for each cross-point switch are transistors Q1. Only Q2Q3 is required, and a significant reduction in the number of elements is achieved compared to the conventional configuration. Regarding power consumption, the conventional cross-point matrix switch with NXN configuration required N2 constant current sources;
Since only N constant current sources are required, a power reduction of 1/N is achieved.

FIG. 2 is a circuit diagram showing a second embodiment of a fork matrix switch constituting a space division switch according to the present invention, and the same or equivalent parts as in FIG. 1 are given the same reference numerals. , the explanation of that part will be omitted, but the first
The difference from the diagram is that the input data lines are 8-1, 8-1', 8-
2 and 8-218-3 and 8-3', 8-4 and 8-4' are differential pair lines, and 8 to 11.82
°, 8-3°, 8-4' input data lines each have 8-1
．． 8-2.8-3.13-4 negative input data is given. The negative input data line 8-18-2", 8-3°,
8-4° is connected to the base of a transistor Q2, which constitutes a differential transistor pair of the cross-point switch and which was connected to the reference voltage terminal 15 in FIG. Since it is configured in this way, the operating principle as a cross-point matrix switch is the same as that of the embodiment shown in FIG. 1, and its explanation will be omitted. Since it is possible to operate with the same operating margin even if the speed is reduced to 1/2, higher speed and lower power consumption are possible.

FIG. 3 is a circuit diagram showing a third embodiment of the cross-point matrix switch constituting the space division switch according to the present invention, and the same or equivalent parts as in FIG. 2 are given the same reference numerals. I will omit the explanation of that part, but the second
The difference from the diagram is that the output data lines are 9-1, 9-1°, 9-
2 and 9-2'9-3 and 9-3' 9-4 and 9-4'
The output data lines 91', 9-2', 9-3', and 9-4' form a differential transistor pair of a cross-point switch. , in FIG. 2, the transistor Q connected to the power supply terminal 13
1 collector is connected. Since it is constructed in this way, the principle of operation as a fork matrix switch is the same as that of the embodiment shown in FIG. 1, and its explanation will be omitted. ', 9-4' have output data lines 9-1, 9-2. ! 11-3.9-
Since the negative signal of the signal above 4 is generated, even if the detection current of the output data line is reduced to 1/2 compared to the embodiment of FIG. 1, the operation can be performed with the same operating margin and operating speed, resulting in lower power consumption. This makes it possible to

Although the above specific embodiments have been explained using a 4×4 cross-point matrix switch as an example, it is clear that the present invention has similar advantages regardless of the matrix size.

〔Effect of the invention〕

As explained above, the space division switch according to the present invention is
By providing a common constant current source for the cross-point switches connected to the same output data line, it is possible to reduce the number of elements that make up the cross-point switch and reduce power consumption. Therefore, there is an advantage that a high-density, low-power space division switch can be realized while maintaining high speed.

[Brief explanation of the drawing]

1 to 3 are circuit diagrams showing first to third embodiments of the present invention, and FIG. 4 is a configuration diagram showing a conventional space division switch.
FIGS. 5 and 6 are circuit diagrams showing conventional cross-point switches. 8-1.8-2.8-3.8-4...Input data line,
9-1.9-2.9-3.9-4...output data line,
1O-ij (i=1,2,3,4,j=12.3.
4)... cross-point switch, 12... input terminal, 13.
14... Power supply terminal, 15... Reference voltage terminal, Ql,
Q2. Q3...Transistor, I +1. + 1-
2.13+'l-4...constant current source.

Claims (4)

[Claims] (1) A space division switch that converts spatially expanded input data and outputs it as output data by opening and closing a cross-point switch disposed between an input data line and an output data line. A space division switch characterized in that a common constant current source is provided for the cross-point switches connected to the same output data line among the cross-point switches. (2) The cross-point switch includes a differential transistor pair in which the emitters of the first and second transistors are common, the collector is connected to the common emitter, the base is connected to the switch open/close data input terminal, and the emitter and a third transistor connected to a common current source, an input data line is connected to the base of the first transistor, and an output data line is connected to the collector of the first or second transistor. 2. A space division switch according to claim 1. (3) The cross-point switch has a differential transistor pair in which the emitters of the first and second transistors are common, the input data line is a differential signal line pair, and one of the differential signal line pairs is connected to the 2. The space division switch according to claim 1, wherein the space division switch is connected to the base of one transistor and the other is connected to the base of the second transistor. (4) The cross-point switch has a differential transistor pair in which the emitters of the first and second transistors are common, and the output data line is a differential signal line pair, and one of the differential signal line pairs is connected to the Connect the collector of the second transistor to the collector of the second transistor, and connect the other to the collector of the first transistor.
2. The space division switch according to claim 1, wherein the space division switch is connected to the collector of the transistor.