JPH02199926A - Nrz/rz conversion circuit - Google Patents

Abstract

PURPOSE:To make the occupancy rate of an input clock signal constant after the occupancy rate of an RZ signal after conversion is set once by detecting the occupancy rate while part of the input clock signal is branched to detect the occupancy rate and controlling the DC voltage fed to a clock input terminal of a logic gate in response to the degree of a change. CONSTITUTION:When an occupancy rate of a clock signal inputted from a clock signal input terminal 3 has a change, an occupancy rate detection circuit 5 detects the reduction in the occupancy rate of an input clock signal and controls an output voltage fed to the variable resistor 6 so that a DC voltage divided by the variable resistor 6 and fed to a clock signal input terminal of an AND gate 2 via a resistor 7 is Vo'. Thus, the occupancy rate of an RZ signal outputted at an RZ signal output terminal 8 is unchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an N)LZ/RZ conversion circuit that converts an NRZ signal of a digital signal into an RZ signal.

(Prior Art) An example of a conventional NRZ/RZ conversion circuit will be described with reference to FIG.

In FIG. 3, a data signal (AND gate) 12 inputted to a data signal input terminal 11 is inputted to one input terminal. - The clock signal input to the clock signal input connector 13 has its DC component removed by the coupling capacitor 14, and is input to the other input terminal of the AND gate 12.

The output voltage of the DC voltage source 19 is divided by the variable resistor 6 and the resistor 17t? The clock input terminal of the AND gate 12 is applied to the clock input terminal of the AND gate 12 via the clock input terminal. Since the AND gate 12 takes the logical product of the NRZ data signal and the clock signal, the RZ multiplied signal is outputted from the output terminal 18.

FIG. 4 is a diagram illustrating a method for adjusting the RZ multiplied signal occupation rate in the NRZ/RZ conversion circuit.

Referring to FIG. 4, 41 is an NRZ signal input to the data signal input terminal 11 in FIG. 3, 42 is an NRZ signal input to the clock signal input terminal 13 in FIG.
For example, the occupancy rate 5 is input to the AND gate 12 after passing through 4.
This is a 0% clock signal. ■0 in FIG. 3 is the nib DC voltage applied to the clock input terminal of the AND gate 12 via the resistor 17 after dividing the output voltage of the DC voltage source 19 by the variable resistor 17, and vth is the AND gate 1
20 input threshold voltages. 43 is the output waveform of the AND gate 12. In the example of FIG. 4, ■o is set lower than Vth, so the threshold voltage Vt of the AND gate 12
The occupation rate of the clock signal for h is less than 50%. By taking the logical product of the NRZ signal 41 and the clock signal 42, an RZ multiplied signal output holder 18 having an occupation rate of less than 50% is obtained.

(Problem to be solved by the invention) In the conventional NR, Z/几2 conversion circuit, the variable resistor is manually adjusted in this way, and the total change in the DC voltage applied to the clock signal input terminal of the ANL/gate is controlled. Since the configuration is such that the output RZ signal occupancy rate is adjusted by t-, even if the occupancy rate of the RZ signal is adjusted to the desired value, if the occupancy rate of the input clock signal changes thereafter, The RZ multiplication signal occupancy rate depends on the occupancy rate of the input clock signal.

Accordingly, the output RZ multiplied signal occupation rate also changes.

Therefore, when the conventional N-Z/RZ conversion circuit is used in a transmitting circuit such as a repeater, the occupancy rate of the RZ signal sent to the transmission line also changes, which causes the identification and reproduction point at the receiving side of the transmission line to change. The disadvantage of this method is that jitter and code amount interference occur in the received equalized waveform, resulting in a high code error rate.

The object of the present invention is to overcome the above-mentioned drawbacks.

An object of the present invention is to provide a Z/FLZ conversion circuit which does not increase the code error rate in identification reproduction on the receiving side of a transmission line by keeping the RZ double signal occupation rate constant.

(Means for Solving the Problems) In order to achieve the above object, the NRZ/RZ conversion circuit according to the present invention adjusts the DC voltage through the conversion means, adds the adjusted DC voltage and a clock signal, and converts the added signal to the DC voltage. NRZ/R converts the NRZ signal into an RZ signal having a predetermined occupancy rate by taking the logical product of the NRZ signal and the NRZ signal.
The Z conversion circuit includes an occupancy detection circuit that detects the occupancy of a clock signal obtained by partially branching the clock signal and outputs a voltage proportional to the detection result of the occupancy of the clock signal, and outputs the occupancy detection circuit. is configured to be applied to the voltage changing means as the DC voltage.

(Example) The present invention will be explained in more detail below with reference to one drawing.

FIG. 1 is a circuit diagram showing an embodiment of the RZ/RZ conversion circuit according to the present invention. A data signal input from the data signal input terminal l is input to an AND gate 2. 9, the DC component of the clock signal input to the clock signal input terminal 3 is removed by the coupling capacitor 4. A part of the clock signal manually input from the clock signal input terminal 3 is branched and inputted to the clock signal occupancy rate detection circuit 5.

A DC voltage corresponding to the detected occupancy rate is output from the occupancy rate detection circuit 5 and applied to the variable resistor 6. Variable resistor 6
divides the output DC voltage of the occupancy rate detection circuit 5, and one divided voltage value is applied to one clock input of the AND gate 2 via the resistor 7t.

The AND gate 2 performs a logical product of the NRZ data signal and the clock signal, and outputs the RZ multiplied signal 8 from the output terminal.

FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG. 1.

In FIG. 2, 21 is the NRZ signal input to the data signal input terminal 1 in FIG. 1, and the center line waveform 22 is input to the clock signal input terminal 3 in FIG. An example of an input signal is a clock signal with an occupancy rate of 50%. (2) In FIG. 1, o is a DC voltage that is applied after dividing the output voltage of the occupancy rate detection circuit 5 by a variable resistor 6 and then applying a voltage to a resistor 7.

VthHAND is the threshold voltage of gate 2. V.

can be controlled by adjusting the variable resistor 6.

In the example shown in FIG. 2, the threshold voltage Vth of AND gate 2
Since it is set lower, the occupation rate of the clock signal with respect to the threshold voltage Vth of the gate 2 (ANL) becomes smaller than 50%. Therefore, the NRZ signal 21 and the clock signal 22
RZ signal 2 with a small occupancy rate by taking the AND with
3 is obtained.

Here, if the occupancy rate of the clock signal input from the clock signal input terminal 3 changes and the occupancy rate becomes small, for example, as shown in the dashed line waveform shown in 22 of the second prisoner, the conventional example NRZ/)( , in the Z conversion circuit, the occupation rate of the clock signal with respect to the threshold voltage Vth of the AND gate 12 becomes even smaller.
(Although the occupancy rate of the Z signal has become smaller, the N
In the Z/RZ conversion circuit, the occupancy rate detection circuit 5 detects a decrease in the occupancy rate of the human clock signal, and depending on the degree of change in the occupancy rate, the voltage is divided by the variable resistor 6 and the voltage is applied to the resistor 7.
The output voltage applied to the oT variable resistor 6 is controlled so that the DC voltage applied to the clock signal input terminal of the gate 2 (through ANL) becomes ◯o' shown at 24 in FIG.

Therefore, the RZ multiplied signal occupancy rate output to the RZ signal output terminal 8 does not change.

(Effects of the Invention) As explained above, the NZ/RZ conversion circuit according to the present invention branches part of the input clock signal to detect the occupancy rate, and outputs the signal to the clock input terminal of the logic gate according to the degree of change. Since the configuration is such that the direct current voltage applied to the stamp is controlled, there is an effect that once the RZ multiplication signal occupancy rate after conversion is set, the occupancy rate of the input clock signal remains constant regardless.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the NB, Z/RZ conversion circuit according to the present invention, Fig. 2 is a timing chart for explaining the operation of Fig. 1, and Fig. 3 is an example of a conventional NRZyRZf conversion circuit. The entire circuit diagram and FIG. 4 are timing charts for explaining the operation of the conventional example. l, 11... NRZ signal input terminal 2.12... AND gate 3.13... Clock signal input terminal 4.14... Coupling capacitor 5... Occupancy rate detection circuit 6.16... Variable resistor 7.17...Resistor 8.18...RZ signal output terminal 9.19...DC voltage source 21, 41-7 N RZ signal 22.42...Clock signal 23.43 ...Output RZ double signal 4...Clock signal Figure 3 Figure 4 Patent applicant NEC Corporation

Claims (1)

[Claims] The DC voltage is adjusted through a variable means, the adjusted DC voltage and a clock signal are added, and the added signal is ANDed with the NRZ signal to convert the NRZ signal into an RZ signal having a predetermined occupation rate. In the NRZ/RZ conversion circuit, an occupancy rate detection circuit is provided that detects the occupancy rate of a clock signal obtained by partially branching the clock signal, and outputs a voltage proportional to the detection result of the occupancy rate of the clock signal, and the occupancy rate detection circuit NRZ/R characterized in that the output is configured to be applied to the variable means as the DC voltage.
Z conversion circuit.