JPH02199863A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02199863A
JPH02199863A JP1020041A JP2004189A JPH02199863A JP H02199863 A JPH02199863 A JP H02199863A JP 1020041 A JP1020041 A JP 1020041A JP 2004189 A JP2004189 A JP 2004189A JP H02199863 A JPH02199863 A JP H02199863A
Authority
JP
Japan
Prior art keywords
substrate
potential
fet
substrate potential
bbg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1020041A
Other languages
Japanese (ja)
Inventor
Sumio Ogawa
澄男 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1020041A priority Critical patent/JPH02199863A/en
Publication of JPH02199863A publication Critical patent/JPH02199863A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To always detect a substrate potential correctly and to control a feedback without delay by a method wherein a detecting part of a substrate potential detector is installed near a maximum leakage-current source of a potential change in a semiconductor substrate. CONSTITUTION:An FET Q1 used as a maximum leakage-current source is formed in an FET substrate 1. A detecting part (detecting terminal) of an SD 2 is installed near the FET Q1. The SD 2 detects a substrate potential VSD near the FET Q1, outputs a feedback signal FB to a substrate-potential generation circuit (BBG) 3 and adjusts a potential-output capacity of the BBG 3. The BBG 3 supplies a substrate potential VBB to the FET substrate 1 on the basis of the feedback signal PB. The FET Q1 generates a substrate leakage current by means of a switching operation and changes the substrate potential near the FET Q1; however, since the SD 2 has detected the potential near the FET Q1 in advance, it can quickly change a capacity of the BBG 3, and the substrate potential is stabilized.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は電界効果型トランジスタ(以下、FETと略す
)が形成された半導体装置に関し、特にその基板電位の
安定化手段を備えた半導体装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device in which a field effect transistor (hereinafter abbreviated as FET) is formed, and particularly relates to a semiconductor device equipped with means for stabilizing the substrate potential thereof. .

[従来の技術] 従来、FETを使用した半導体装置では、基板電位を回
路の電源とは別の電源から供給するようにしていた。し
かし、最近では、単一電源化の要求に応えるため、基板
電位発生回路(以下、BBGと略す)を使用して回路電
源から基板電源を作り出すことが行われている。
[Prior Art] Conventionally, in a semiconductor device using an FET, a substrate potential is supplied from a power source different from a circuit power source. However, recently, in order to meet the demand for a single power supply, a substrate potential generation circuit (hereinafter abbreviated as BBG) has been used to generate a substrate power source from a circuit power source.

第4図は、単一電源化を図ったこの種の従来の半導体装
置の概略構成を示す図である。
FIG. 4 is a diagram showing a schematic configuration of a conventional semiconductor device of this type that uses a single power source.

FET基板1の電位VSDは、基板電位検知器(以下、
SDと略す)2によって検知され、その検知出力をBB
G3にフィードバックすることにより、BBG3からF
ET基板1に供給される基板電位VBBが制御されるよ
うになっている。
The potential VSD of the FET substrate 1 is detected by a substrate potential detector (hereinafter referred to as
(abbreviated as SD) 2, and its detection output is BB
By feeding back to G3, BBG3 to F
The substrate potential VBB supplied to the ET substrate 1 is controlled.

この回路によれば、例えばFETのリーク電流等の影響
で基板電位が変動した場合に、フィードバック制御によ
って電位変動が制御され、常に適切な基板電位に保持す
ることができる。
According to this circuit, when the substrate potential fluctuates due to the influence of leakage current of the FET, for example, the potential fluctuation is controlled by feedback control, and the substrate potential can always be maintained at an appropriate substrate potential.

[発明が解決しようとする課題] しかしながら、基板電位は基板全域に亘って、−様であ
るとは限らない、即ち、基板には第4図V1、V2、V
、及び■4の等電位線で示すような電位分布が生じる。
[Problems to be Solved by the Invention] However, the substrate potential is not necessarily -like over the entire area of the substrate.
, and potential distributions as shown by the equipotential lines in (4) are generated.

以下に基板電位分布が生じるメカニズムについて説明す
る。
The mechanism by which substrate potential distribution occurs will be explained below.

第4図において、FETQlはNチャネルMO9FET
であり、FET基板1はP型半導体であるとすると、F
 E T Q 7がスイッチングしたとき、チャネルか
ら基板リーク電流ILが基板中に流入し、近傍の基板電
位を変動させる。しかし、この電位は通常は直ちに周辺
の基板電位に平均化されてしまう。
In Fig. 4, FETQl is an N-channel MO9FET.
, and assuming that the FET substrate 1 is a P-type semiconductor, F
When E T Q 7 switches, a substrate leakage current IL flows from the channel into the substrate, changing the nearby substrate potential. However, this potential is usually immediately averaged to the surrounding substrate potential.

S i LS Iにおける出力FET等のように、例え
ばゲート長3μm、幅120.umと、FETサイズが
大きくなってくると、リーク電位工、もそれに伴って大
きくなり、基板の層抵抗のために基板電位の速やかな平
均化が行われず、図中Vl>V2 >V3 >V4 >
Vso≧VBBで示すような電位分布が生じてしまう。
Like the output FET in S i LS I, for example, the gate length is 3 μm and the width is 120. As um and the FET size increase, the leakage potential also increases, and due to the layer resistance of the substrate, the substrate potential is not quickly averaged, and in the figure, Vl > V2 > V3 > V4 >
A potential distribution as shown by Vso≧VBB occurs.

ところが、SD2はその検出部がBBG3の基板電位供
給部の近傍に設けられ、電位VBBに近い値(V5D)
を検出しているため、上述した異常電位の検知が遅れた
り、誤った電位を検知してフィードバックが不適切にな
るという問題点があった。
However, in SD2, the detection section is provided near the substrate potential supply section of BBG3, and the potential is close to VBB (V5D).
Therefore, there are problems in that the detection of the above-mentioned abnormal potential is delayed, or an erroneous potential is detected, resulting in inappropriate feedback.

このため、FETQ、の近傍では基板電位があるべき値
からはずれてしまい、FETQ7又はその近くのFET
までが誤動作してしまうという問題点があった。
For this reason, the substrate potential near FETQ deviates from the desired value, and FETQ7 or the FET near it deviates from its expected value.
There was a problem that the system would malfunction.

本発明はかかる問題点に鑑みてなされたものであって、
基板電位を常に正しく検知して遅れのない適切なフィー
ドバック制御をかけることが可能な半導体装置を提供す
ることを目的とする。
The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a semiconductor device that can always correctly detect a substrate potential and perform appropriate feedback control without delay.

[課題を解決するための手段] 本発明に係る半導体装置は、半導体基板の電位を検知す
る基板電位検知器と、この基板電位検知器からの検知出
力に基づいて前記半導体基板の電位を制御する基板電位
発生回路とを備えた半導体装置において、前記基板電位
検知器は、検知部が少なくとも前記半導体基板内のリー
ク電流源のうち最も大きなリーク電流源の近傍に設置さ
れていることを特徴とする。
[Means for Solving the Problems] A semiconductor device according to the present invention includes a substrate potential detector that detects the potential of a semiconductor substrate, and controls the potential of the semiconductor substrate based on a detection output from the substrate potential detector. In the semiconductor device including a substrate potential generation circuit, the substrate potential detector is characterized in that a detection section is installed at least near the largest leakage current source among the leakage current sources in the semiconductor substrate. .

[作用] 本発明においては、基板電位検知器の検知部が、半導体
基板中の少なくとも基板電位変動の著しい最大リーク電
流源近傍に設置されているため、基板電位の変動を確実
に検知することができる。このため、電位検知が遅れる
ことがなく、速やかなフィードバック信号を伝達するこ
とができる。
[Function] In the present invention, since the detection part of the substrate potential detector is installed in the semiconductor substrate at least near the maximum leakage current source where the substrate potential changes significantly, it is possible to reliably detect changes in the substrate potential. can. Therefore, potential detection is not delayed, and a feedback signal can be transmitted quickly.

[実施例] 以下、添付の図面を参照しながら本発明の実施例につい
て説明する。
[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

第1図は本発明の第1の実施例に係る半導体装置の概略
構成を示す図である。
FIG. 1 is a diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention.

FET基板1には、最大リーク電流源となるFETQl
が形成されている。このFETQlの近傍にはSD2の
検知部(検知端子)が設置されている。SD2はFET
QI近傍の基板電位■sDを検知して、BBG3にフィ
ードバック信号FBを出力し、B B G 3’の電位
出力能力を調整する。BBG3は、フィードバック信号
FBに基づいてFET基板1に基板電位VBBを供給す
る。
The FET board 1 has a FETQl which is the maximum leakage current source.
is formed. A detection section (detection terminal) of SD2 is installed near this FETQl. SD2 is FET
It detects the substrate potential ■sD near QI, outputs a feedback signal FB to BBG3, and adjusts the potential output capability of BBG3'. BBG3 supplies substrate potential VBB to FET substrate 1 based on feedback signal FB.

F E T Q 1はスイッチングによって、基板リー
ク電流を生じさせ、FETQ、近傍の基板電位を変化さ
せるが、SD2は前もってFETQ、の近傍位置の電位
を検出しているため、BBG3の能力を速やかに変化さ
せることができ、基板電位の安定化が行われる。
FETQ1 generates a substrate leakage current through switching and changes the substrate potential near FETQ, but SD2 detects the potential near FETQ in advance, so it quickly changes the ability of BBG3. The substrate potential can be stabilized.

なお、SD2が基板電位を検知する位置は一般的なSt
−メモリデバイスの場合、リーク源から約700μm以
内が好適で゛ある。これは、過去の一般的なメモリにお
いて、基板リーク源から7゜0μm以内のFETに誤動
作が起こり、約8o。
Note that the position where SD2 detects the substrate potential is the general St.
- For memory devices, preferably within about 700 μm from the leak source. This is because in past general memories, malfunctions occurred in FETs within 7°0 μm from the substrate leak source, and the error was approximately 8°.

μmにおけるFETの動作に影響が無かったという経験
則に基づく。
Based on the empirical rule that there was no effect on FET operation in μm.

第2図は本発明の第2の実施例を示す図である。FIG. 2 is a diagram showing a second embodiment of the present invention.

基板リーク電流源となるようなF、ETは第1の実施例
のように1つであるとは限らない、この第2の実施例で
は、そのようなFETが2つある場合、各F E T 
Q 2 、 Q sの近くに夫々SD、2a。
The number of FETs that serve as substrate leakage current sources is not necessarily one as in the first embodiment.In this second embodiment, when there are two such FETs, each FET is T
SD and 2a near Q 2 and Q s, respectively.

5D22bの検知部を設置している。A 5D22b detection unit is installed.

このように、リーク源となるような複数個のFETがあ
った場合、これと同数のSDの検知部を各FETの近傍
に配置することにより、本発明の効果を高めることが可
能である。
In this way, when there are a plurality of FETs that can be a leak source, it is possible to enhance the effects of the present invention by arranging the same number of SD detection sections near each FET.

但し、この場合SDの設置によりチップ面積があまり増
加しないようにSDの設置を特にリーク電流の大きなF
ETに限定し、その数は10個程度であることが好まし
い。
However, in this case, in order to prevent the chip area from increasing too much due to the installation of the SD, the installation of the SD should be done especially on F with a large leakage current.
It is preferable that the number is limited to ET and that the number is about 10.

第3図は本発明の第3の実施例を示す図である。FIG. 3 is a diagram showing a third embodiment of the present invention.

基板リーク電流源はトランジスタに限定されない。即ち
、第3図に示すようにFET基板1内にMOSFETに
よって構成された大容量キャパシタンスCの充放電にも
基板リーク電流が伴う。従って、リーク源のFETQ6
の他に、このような素子を構成するFETQ4 、Q5
の近傍にも5DC2Cの検知部を設置することが有効で
ある。
Substrate leakage current sources are not limited to transistors. That is, as shown in FIG. 3, a substrate leakage current also accompanies the charging and discharging of a large capacitance C formed by a MOSFET in the FET substrate 1. Therefore, the leak source FETQ6
In addition, FETQ4 and Q5 that constitute such an element
It is effective to install a 5DC2C detection section also near the.

なお、上記実施例では、リーク源としてキャパシタンス
を挙げたが、−船釣に拡散層(基板)を構成要素とする
素子はリーク源と考えられることは明白である。よって
、このような素子の近傍に基板電位検知器を設置すれば
、本発明の効果が得られることは明らかである。
In the above embodiment, capacitance was cited as a leak source, but it is clear that an element having a diffusion layer (substrate) as a component can be considered as a leak source. Therefore, it is clear that the effects of the present invention can be obtained by installing a substrate potential detector near such an element.

[発明の効果] 以上説明したように本発明は、基板電位検知器の検知部
を基板リーク電流源の近くに設置することにより、基板
電位変動を速やかに基板電位発生回路にフィードバック
することができ、基板電位の安定化を図ることができ、
安定した回路動作を得ることができる。
[Effects of the Invention] As explained above, in the present invention, substrate potential fluctuations can be quickly fed back to the substrate potential generation circuit by installing the detection part of the substrate potential detector near the substrate leakage current source. , it is possible to stabilize the substrate potential,
Stable circuit operation can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例に係る半導体装置の概略
ブロック図、第2図は本発明の第2の実施例に係る半導
体装置の概略ブロック図、第3図は本発明の第3の実施
例に係る半導体装置の概略ブロック図、第4図は従来の
半導体装置の概略ブロック図である。 1、FET基板、2a、2b、2c;基板電位検知器、
3;基板電位発生回路、Q1〜Q7;FF、T、 C、
キャパシタンス
1 is a schematic block diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a schematic block diagram of a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a schematic block diagram of a semiconductor device according to a second embodiment of the present invention. FIG. 4 is a schematic block diagram of a conventional semiconductor device. 1, FET substrate, 2a, 2b, 2c; substrate potential detector,
3; Substrate potential generation circuit, Q1 to Q7; FF, T, C,
capacitance

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板の電位を検知する基板電位検知器と、
この基板電位検知器からの検知出力に基づいて前記半導
体基板の電位を制御する基板電位発生回路とを備えた半
導体装置において、前記基板電位検知器は、検知部が少
なくとも前記半導体基板内のリーク電流源のうち最も大
きなリーク電流源の近傍に設置されていることを特徴と
する半導体装置。
(1) A substrate potential detector that detects the potential of a semiconductor substrate;
In the semiconductor device including a substrate potential generation circuit that controls the potential of the semiconductor substrate based on a detection output from the substrate potential detector, the substrate potential detector has a detection section that detects at least a leakage current in the semiconductor substrate. A semiconductor device characterized in that the semiconductor device is installed near the largest leakage current source among the sources.
JP1020041A 1989-01-30 1989-01-30 Semiconductor device Pending JPH02199863A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1020041A JPH02199863A (en) 1989-01-30 1989-01-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1020041A JPH02199863A (en) 1989-01-30 1989-01-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02199863A true JPH02199863A (en) 1990-08-08

Family

ID=12015976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1020041A Pending JPH02199863A (en) 1989-01-30 1989-01-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02199863A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003094235A1 (en) * 2002-04-30 2003-11-13 Renesas Technology Corp. Semiconductor integrated circuit device
US7605616B2 (en) 2006-10-18 2009-10-20 Spansion Llc Voltage detector circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003094235A1 (en) * 2002-04-30 2003-11-13 Renesas Technology Corp. Semiconductor integrated circuit device
US7605616B2 (en) 2006-10-18 2009-10-20 Spansion Llc Voltage detector circuit

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