JPH02199542A - Information processor - Google Patents

Abstract

PURPOSE:To generate an optional vector address, to read out a required start address and to increase the number of routines by changing the level of upper bits in the vector address. CONSTITUTION:An upper address setting part X' selectively connects each bit line out of upper 12 bits in the vector address to a test signal line Q or a ground line G so that a required address can be previously obtained. Since the upper 12 bit are always held at the 'L' level when the line Q is in the 'L' level, a normal mode to be usually used by a user is set up. When the line Q is turned to an 'H' level, a test mode is set up and the upper 12 bits can be constituted of required bits by connecting respective bit lines to the line Q or G by the setting part X'. Thereby, a required starte address can be read out from a ROM 1 and the number of routines can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to (1) an information processing device such as a chip microcomputer, and particularly relates to an information processing device in which a start address can be changed at the time of an interrupt or the like.

[Prior Art] An information processing device such as a processor IC has a built-in mechanism for generating a start address for a processing routine executed when a reset or an interrupt occurs.

However, in ICs with built-in programs such as I-chip microcomputers and DSPs in which the address bus does not go outside the chip, the start address is stored in the mask ROM.
It is common that the code is fixed and written in
FIG. 3 shows an example of the configuration of this type of address control circuit.

4 bytes of ROM1 is allocated to the address space of 0000B-OFFFFH, and 000FH to 0OO
The 16 addresses of FH have a total of 16 vector addresses, 2 types of reset and 14 types of interrupt processing.
starting addresses are written.

To distinguish between these 16 types of vector addresses, 4
Since bits are sufficient, the vector address generator 2 outputs the lower 4 bits (A3-A11) of the 16-bit address as vector address information. The remaining upper 12 bits of the address (A
Each bit line (BI6 to B4) of the vector address generator 2 is grounded in the upper address setting section
AO) is sent to the address bus via the gate 3 as a vector address together with the upper 12 bits (A15 to A4) fixed at L level from the upper address setting unit X.

A multiplexer 4 that selects the address value or PC value from these buses is connected to the address bus and the PC bus, and as shown in FIG. However, in the second half when the reference clock becomes L level, the PC value is selected in a time-division manner, and the RO
Given to MI. This value ≠ break +4 is further controlled by the chip ice-pull circuit 5ζ pin, and in this embodiment, the address space of ROMI is in the lower 4 bytes, so the address value and PC value is ROM
If the address value is within the address space, the multiplexer 4 is enabled, and if the address value and PC value are outside the address space, the output of the multiplexer 4 is prohibited.

It is characterized in that it can be read by accessing the ROMI in this way.

[Action] For example, [LLLLI, I, L, LLLLL HL;H
L], the upper 12 bits are fixed at L level,
At a vector address where the lower 4 bits are set to an arbitrary H or L level, the upper 12
By making each bit in the bits easily set to H or L, an arbitrary vector address can be obtained, and a desired start address can be read by accessing this vector address.

[Embodiment] FIG. 1 is a control block diagram showing an embodiment of the apparatus of the present invention, and the same parts as in FIG. 3 are given the same reference numerals.

In the upper address setting section X', each line of the upper 12 bits (A15 to A4) in the vector address can be selectively connected to the ground line G or the test signal line Q, so that the desired address can be obtained in advance. so that you can
Each bit line is tested.The borrowed start address is latched by the latch circuit 6 and transferred to the PC register 7 in the next cycle.

[Problems to be Solved by the Invention] In the conventional circuit described above, the start address is read out from the ROMI addresses 0000H to 000FH based on 16 types of fixed vector addresses generated by the vector address generator 2. Therefore, it was difficult to change to a different start address.

The present invention has been made to eliminate the above-mentioned problems, and it is an object of the present invention to provide an information processing device that can read a desired start address by switching the operation mode.

[Means for Solving the Problems] An information processing device of the present invention has a vector address in which a predetermined number of high-order bits are set to L level, and each of the high-order bits is set to H or L level. A means for enabling this is connected to the signal line Q or the ground line G.

In FIG. 1, bit line Bu5 is connected to test signal line Q, and bit line B14 is connected to ground line G. The test signal line L is at the L level in the normal operation mode, and at the H level in the test mode.

In the above configuration, when the test signal line Q is at the L level, the upper 12 pins (A15 to A4) are always at the L level regardless of the connection state in the upper address setting section X°. As with the conventional example, it is the normal mode used by normal users, and the ROMI 000
Any address from 0H to 0OOF')I is accessed and the start address is read.

On the other hand, when the test signal line Q becomes H level, the test mode is entered, and the upper address setting section X.

, the bit line connected to the ground line G is L
However, since the bit line connected to the test signal line Q is at the I4 level, the upper address setting section
By connecting each bit line to the test signal line Q or ground line G at will, the upper 12 bits (
A15 to A4) can be made into a desired bit configuration,
Therefore, a desired start address can be read by accessing a desired address in the ROM1.

FIG. 2 shows an example in which the bit line can be selectively connected to the ground line G or the test signal line Q in the upper address setting section X'.

A test signal line Q and a ground line G are formed in parallel,
Through these lines 1 and a contact mask (not shown), address bit lines (B15.BI-...B,) in the address setting section X° are formed in a direction orthogonal to the lines Q and G. As shown in FIG. 2, the contact mask includes bit lines B1. Openings W1 and W2 are provided to correspond to the overlapping part between the bit line BI4 and the test signal line Q, and the overlapping part between the bit line BI4 and the ground line G, respectively. Bit line B15 can be used as test signal line Q. Alternatively, only the normal vector address may be disclosed to the user, and the vector address at the time of mode switching may be used by the manufacturer for evaluation of the program.

[Brief explanation of the drawing]

FIG. 1 is a control block diagram showing one embodiment of the information processing device of the present invention, FIG. 2 is a pattern formation diagram showing an example of the configuration of the upper address setting section in the device of FIG. 1, and FIG. FIG. 4, which is a control block diagram of the information processing apparatus, is a time chart showing the operation of the apparatus shown in FIG. l...ROM, 2...vector address generator, 3...
...Gate, 4...Multiplexer, 5...Chip enable circuit, 6...Latch circuit, 7...IC register, Xo...Upper address setting section.

Claims (1)

[Claims] (1) An information processing apparatus having a vector address in which a predetermined number of upper bits are set to L level, comprising means for enabling each of the upper bits to be set to H or L level. Device.