JPH02198429A - Thin film field effect type transistor element array - Google Patents

Abstract

PURPOSE:To obtain a larger display which does not bring on deterioration of a display quality caused by a write shortage of a signal voltage by forming the whole gate bus line from a metal without increasing a mask pattern exceeding three pieces. CONSTITUTION:A picture element electrode 6b is formed by a transparent conductive film, and by a laminated film of the transparent conductive film and a first metal, island-like gate electrodes 2a, 2b and drain bus lines 5a, 5b are formed. Also, in each intersection part of a thin film field effect type transistor 10 forming part and a gate bus line 3a, and the drain bus lines 5a, 5b, an island-like insulating layer and a semiconductor layer are formed, and moreover, by a second metal, drain and source electrodes 14 of the thin film field effect type transistor 10 and the gate bus line 3a are formed. In such a way, by three pieces of masks to be used, the gate bus line can be converted to a low resistance, and a larger display which does not bring on deterioration of a display shortage generated by a write shortage of a signal voltage caused by a propagation delay of a signal pulse can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film field effect transistor element array used particularly in an active matrix liquid crystal display.

[Conventional technology]

Liquid crystal displays are attracting attention as flat panel displays for portable computers and wall-mounted televisions. Among these, the active matrix method, in which an array of thin-film field-effect transistors is formed on a glass substrate and used as a switch for each pixel, is capable of full-color display, so it is expected to be applied to televisions, etc., and is being actively used in various institutions. is being carried out. In order to put this active matrix type liquid crystal display into practical use, cost reduction is an important issue, and the solution to this problem is to simplify the structure and manufacturing process. In the inverted staggered structure in which the gate electrode of a thin film field effect transistor is formed closer to the glass substrate than the source/drain electrode, the conventional technology is to
There is a manufacturing method using three masks (for example, Japanese Patent Laid-Open No. 62286271).

FIGS. 3(a) to 3(g) are diagrams showing one step in forming a thin film field effect transistor element array based on a conventional method, (a) and (c).

(e) is a plan view seen from above, and (b).

(d), (f), and (g) are (a) and (c), respectively.

AA', B-B', C-C'D- in (e)
It is a sectional view of the part D'. In FIG. 3, 1 is a glass substrate which is a light-transmitting insulating substrate, and 2a and 6a are a chromium (Cr) gate electrode and a chromium pixel electrode, respectively. Further, 2b and 6b are transparent gate electrodes and transparent pixel electrodes made of transparent conductive films. Further, 7 is silicon nitride (SiNx), 8 is hydrogenated amorphous silicon (a-Si:H), and 9 is phosphorus-doped n-type hydrogenated amorphous silicon (n''-a-St:H).Furthermore, 4 5a is a drain electrode, and 5a is a chromium drain bus line, which are formed in the same process and are integrated.A source electrode is placed on the opposite side of the drain electrode 4 across the channel part of the thin film field effect transistor 10. 1
4 is connected to a transparent pixel electrode 6b via a chrome pixel electrode 6a.

Chromium was used as the gate electrode and drain electrode, SiNx was used as the gate insulating film, a-8i:H was used as the semiconductor film, n"-aSi:H5 doped with phosphorus was used as the n-type semiconductor film, and indium and tin oxide were used as the transparent conductive film.
Using Tin Oxide: ITO),
The process of manufacturing a conventional thin film field effect transistor array will be explained with reference to FIG. First, ITO and chromium as a first metal are laminated on a glass substrate 1, and a chromium gate electrode 2a, a chromium pixel electrode 6a, a transparent gate electrode 2b, and a transparent pixel electrode 6b are formed by photolithography using a first mask pattern. (Fig. 3(a))
.

(b)), then 5iNx7,a-Si:H8,n”
-a-St:H9 was sequentially laminated, and by photolithography using a second mask, the laminated film near the thin film field effect transistor 10 and the chromium drain bus line 5a was left, and the other parts were 5iNx7, a-S
i:)18, n+-a-Si:89 is removed (Fig. 3 (C), (d)). Then, after further forming a film of chromium as a second metal, the second chromium is etched by photolithography using a third mask,
A chromium drain bus line 5a, a drain electrode 4, and a source electrode 14 are formed, and further etching is performed to form a chromium pixel electrode 6 made of the first chromium on a transparent pixel electrode 6b.
Remove a. At the same time, the thin film transistor 10
and other than the intersection with the chrome drain bus line 5a,
The first chrome gate electrode made of chromium on the transparent gate electrode 6b is also removed. Then, by etching n+a-Si:H9 using the same resist pattern, the n-type amorphous silicon between the train electrode 4 and the source electrode 14 is removed, and a channel portion of the thin film field effect transistor 10 is formed. (Figure 3(e).

(f)). In this case, the gate bus line 3 has a laminated structure of the first chromium and ITO at the intersection with the thin film transistor 10 and the drain bus line 5, but is composed only of ITO in other parts (Fig. 3). (g))
.

Normally, five to seven mask patterns are required to fabricate an inverted staggered thin film transistor array, but according to the method described above, a thin film field effect transistor array can be formed using three masks.

[Problem to be solved by the invention]

Now, as the display size of a display becomes larger, the wiring length increases, and as the definition becomes higher, the wiring width decreases.

Therefore, since the wiring resistance increases, the voltage applied to the gate bus line and the drain bus line causes a propagation delay due to the interaction with the wiring capacitance. This propagation delay causes insufficient voltage to be applied to each thin film transistor, resulting in insufficient writing of the signal voltage to each pixel, resulting in deterioration of display quality. In particular, in the case of gate bus lines, since they are arranged horizontally in the display, the wiring length is long and the wiring resistance is high. Furthermore, since the wiring capacitance is large, such as the capacitance at the intersection with the drain bus line and the channel capacitance of the thin film transistor, the influence of propagation delay is greater than that of the drain bus line. As can be seen from the plan view in Figure 3(e), in conventional thin film field effect transistor arrays, part of the gate bus line is made of transparent material, which has a resistivity several tens to hundreds of times higher than that of metal. Since it is formed from a conductive film, the wiring resistance is high and the influence is even greater. Furthermore, as shown in FIG. 3(e), since an a-Si:H8 layer exists near the thin film field effect transistor 10, it is difficult to define the channel length and channel width of the thin film field effect transistor 10. there were.

An object of the present invention is to provide a thin film field effect transistor element array in which the entire gate bus line can be formed from metal without increasing the number of mask patterns beyond three.

[Means to solve the problem]

In the present invention, a gate bus line and a drain bus line are formed on a transparent insulating substrate so as to intersect with each other, and the crossing portions are formed in a matrix shape and surrounded by the gate bus line and the drain bus line. A pixel electrode is formed in the area where the pixel electrode is formed, a thin film field effect transistor is formed near each intersection, a source electrode of each of the thin film field effect transistors is connected to the pixel electrode, and a gate electrode is connected to the gate bus line. In the thin film field effect transistor element array in which the drain electrode is connected to the drain bus line, the pixel electrode is formed of a transparent conductive film, and the island-shaped gate electrode is formed by a laminated film of the transparent conductive film and the first metal. , the drain bus line is formed, an island-shaped insulating layer and a semiconductor layer are formed in the thin film field effect transistor forming portion and at each intersection of the gate bus line and the drain bus line, and a second metal Accordingly, the drain and source electrodes of the thin film field effect transistor and the gate bus line are formed.

[Effect]

According to the thin film field effect transistor element array of the present invention, the entire portion of the gate bus line, which is largely affected by wiring resistance, can be made of metal. Furthermore, the channel length and channel width of the transistor can be reliably defined.

〔Example〕

FIGS. 1(a) to 1(g) are process diagrams showing an embodiment of a method for manufacturing a thin film field effect transistor element array having a structure according to the present invention, and FIGS. are plan views seen from above; (b), (d), (f),
(g) is A− in (a>, (c), and (e), respectively)
It is sectional drawing of the part of A'BB', CC', and DD'. In FIG. 1, 1 is a glass substrate which is a light-transmitting insulating substrate, and 2a and 3a are chrome gate electrodes and chrome gate bus lines using chromium as metal. Further, 5a is a chrome drain bus line 5 which is also made of chrome. Also, 7 is silicon nitride (SiNx), 8 is hydrogenated amorphous silicon (a
-8i:H), 9 is n-type hydrogenated amorphous silicon doped with phosphorus (n+a -Si:H). Further, 5b and 6b are a transparent drain bus line and a transparent pixel electrode, respectively, made of ITO. Furthermore, 4 and 14 are a drain electrode and a source electrode, respectively.

Further, 10 is a thin film field effect transistor.

A method of manufacturing a thin film field effect transistor element array having the structure of the present invention will be explained with reference to FIG. First, 500 layers of ITO were formed on a glass substrate 1 by sputtering, then 1000 layers of chromium was formed as the first metal, and a chrome gate was formed by photolithography using a first mask pattern. Electrode 2a, transparent gate electrode 2b
, a chrome drain bus line 5a, a transparent drain bus line 5b, a chromium pixel electrode 6a, and a transparent pixel electrode 6b are formed (see FIGS. The photoresist is formed using a wet etching method to remove the chromium in the areas not covered with the photoresist.
! A dry etching method using 4 may also be used. Subsequently, wet etching of ITO is performed using the same resist pattern to remove portions of ITO not covered by the photoresist. After etching, the photoresist is peeled off, thereby completing the photolithography using the first mask pattern. The characteristics of the mask pattern include the chrome gate electrode 2a and the transparent gate electrode i.
2b is island-shaped. Next, plasma C
VD (Chemical Vapor Deposit)
ion) method, 5iNx7,a-Si:H8,n
” -a-9t:l (9 is sequentially formed and laminated. In addition, 5iNx7, a -Si:H film 8, n+-a -Si
:The film thickness of H9 is 3000, 2000, and 5, respectively.
There are 00 people. Thereafter, by photolithography using a second mask pattern, 5iNx7, a-8t:H8,
n+-a-8t: Forms an island of H9 (Fig. 1(c),
(d)). Specifically, the shape of the second mask pattern is formed using photoresist. Then, by dry etching using CF4 gas, the parts not covered with the photoresist were etched with 5iNx7,a -Si:H8,n+-a
The Si:H9 is removed and the photoresist is stripped. Next, after forming 1000 layers of chromium as a second metal by sputtering, a chromium gate bus line 3a, a drain electrode 4, and a source electrode 14 are formed by photolithography using a third mask pattern.
The chrome gate electrode 2a and the drain electrode 4 are connected to the chrome gate bus line 3a and the chrome drain bus line 5a, respectively. Specifically, photoresist is used to
A mask pattern shape is formed, and chromium, which is the second metal, is removed from the areas where there is no photoresist by wet etching. Next, proceed with further etching,
When the chromium pixel electrode 6a and the like made of the first metal are removed, the transparent pixel electrode 6b and the like are exposed. Then, by etching n+-a-3i:H9 using the same resist pattern, the train electrode 4 and the source electrode 14 are etched.
The n+-a-Si:H in between is removed to form the channel portion of the thin film field effect transistor 10 (FIG. 1(e)).
, (f), (g)).

Finally, by removing the photoresist, the thin film field effect transistor element array is completed.

As described in the above manufacturing method, the thin film field effect transistor array according to this example has gate bus lines 3, as shown in the plan view of FIG. 1(f) and the cross-sectional view of FIG.
The entire part of a can be made of chromium. The electrical resistance of chromium is about 1i20 that of ITO, so some conventional ITO
We were able to realize a gate bus line with wiring resistance that is about one impulse lower than that of the gate bus line that was constructed using the following. Note that in this embodiment, some of the drain bus lines are
However, since the drain bus line is arranged in the vertical direction of the display, its length is shorter than the gate bus line, and the capacitance of thin film field effect transistors only needs to be considered on the drain electrode side. , the signal propagation delay due to wiring resistance and wiring capacitance is short (
(Reference, 1985 IEICE Autumn Conference, Semiconductor and Materials Division, page 185). Therefore, a larger display can be realized without deterioration in display quality due to insufficient writing of signal voltages.

In this example, ITO was used as the transparent conductive film, but In20g or 5n03 can also be used. Furthermore, 5i02 may be used instead of SiNx as the gate insulating film. Furthermore, other metals such as Ta, AI, Mo, etc. can be used instead of chromium for the gate bus line and drain bus line.

A plan view of another thin film field effect transistor element array according to the present invention is shown in FIG. In this case, a chromium gate electrode 2a and a transparent gate electrode 2b made of the first metal are used.
By arranging also below the chrome gate bus line 3a made of the second metal, multiple wiring of the gate bus line is performed, preventing disconnection and lowering the wiring resistance. Also, in the drain bus line, the second
By extending the drain electrode 4 made of chromium, which is a metal of Multiple wiring is used to prevent wire breakage. The rest is the same as the embodiment shown in FIG.

〔Effect of the invention〕

As described above, according to the thin film field effect transistor array of the present invention, it is possible to reduce the resistance of the gate bus line by using only three masks, and it is possible to reduce the writing of signal voltage caused by the propagation delay of signal pulses. A larger display can be realized without deteriorating display quality due to shortage.

[Brief explanation of the drawing]

1(a) to g> are a plan view and a cross-sectional view illustrating the manufacturing process of one embodiment of a thin film field effect transistor element array according to the present invention, FIG. 2 is a plan view of another embodiment, FIGS. 3(a) to 3(g) are a plan view and a cross-sectional view illustrating the manufacturing process of a conventional thin film field effect transistor element array. 1...Glass substrate, 2a...Chromium gate electrode, 2
b...Transparent gate electrode, 3a...Chromium gate bus line, 4...Drain electrode, 5a...Chromium drain bus line, 5b...Transparent drain bus line,
6a...Chromium pixel electrode, 6b...Transparent pixel electrode,
7--SiNx, 8-a-Si:H19-n"
-a-5t: Hllo... thin film field effect transistor, 14... source electrode.

Claims (1)

[Claims] A plurality of gate bus lines arranged in parallel and a plurality of drain bus lines arranged in parallel are formed on a transparent insulating substrate so as to cross each other, and are surrounded by the gate bus line and the drain bus line. a pixel electrode is formed in the region, a thin film field effect transistor is formed near each intersection of a gate bus line and a drain bus line, a source electrode of each of the thin film field effect transistors is connected to the pixel electrode, In a thin film field effect transistor element array in which a gate electrode is connected to the gate bus line and a drain electrode is connected to the drain bus line, the pixel electrode is formed of a transparent conductive film, and the transparent conductive film and the first metal are connected to each other. An island-shaped gate electrode and the drain bus line are formed by the laminated film, and an island-shaped insulating layer and A thin film field effect transistor element array, characterized in that a semiconductor layer is formed, and a drain and a source electrode of the thin film field effect transistor, and the gate bus line are formed of a second metal.