JPH02197940A - Hierarchical memory system including another cash memory for storing data and instructions - Google Patents

Abstract

PURPOSE: To shorten the waiting time of a CPU by writing back the instruction, which is read into a cache for data and is changed, to a main storage device and invalidating a line corresponding to the changed instruction in a cache for instruction. CONSTITUTION: Assuming that a line is effective and indicates the change in the case of the occurrence of data cache mistake, the data line in the data cache must be written back to the storage device before a new data line can be loaded to this specific line in the data cache. Therefore, a write-back latch/ multiplexer 52 is energized. A byte selection mechanism 46 and byte write gates 50 control the storage of data to the data cache. The byte selection mechanism 49 gates main storage data so that only double words of main storage data pass a byte input multiplexer 48 at the time of CPU load OP accompanied with directory mistake, and all byte write gates 50 are activated. Thus, the waiting time of the CPU is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION A. TECHNICAL FIELD The present invention relates to a hierarchical storage organization using a unique cache architecture, each having separate caches for instruction storage and data storage. This hierarchical storage arrangement is particularly suitable for high speed electronic computing systems where it is particularly desirable to minimize CPU latency due to memory accesses.

B. Background Art Modern high-speed electronic data processing systems often consist of a processing unit or CPU and a hierarchical storage system. The latter means that the cycle time is
A relatively large, slow memory whose cycle time is much longer than that of a processing unit; and a relatively much smaller, faster memory whose cycle time, usually called a cache, is comparable to the cycle time of a processing unit. Contains. Such cache memory systems for reducing effective memory access time at reasonable cost are well known in the art. When the CPU requires information, the information is read from main memory, provided to the processing unit, and written to cache storage. If the same information is subsequently needed by the processing unit, it can be read directly from the cache, avoiding the time delay that would normally occur when reading from main memory.

However, if the cache storage is 7 full, the required information must be obtained from main storage, and a location in the cache must be identified to store this new information. However, before an old storage location can be used to store new data, a determination must be made whether the data currently in the cache has been modified by the program; The data must be written back to main memory (if necessary) so that main memory properly reflects the current state of the data. Most current cache architectures require such writeback, but only if the data in its modified form is never needed by the program again, or if the data is never modified. , it would be clearly advantageous to remove this write-back function.

Another common feature of many existing cache architectures is that they are essentially transparent to system software. In other words, the system including compiler, operating system, etc.
The software performs memory fetch and store operations as if the cache were not present. In such systems, the cache hardware is essentially
and the main memory. In such a system,
Although the presence of a cache significantly speeds up the effective memory access time, much of the benefit that could be gained from such faster storage is lost due to the architecture and conventions used.

ACM 5IGPLAN Notice, Vol.
17, No. 4, April 1982, pp, 39
~The8 by George Radin in 47
The paper entitled 01 Minicomputer is an overview of an experimental minicomputer that utilizes the concepts of the present invention and incorporates a hierarchical storage configuration including separate cache storage for instructions and data.

U.S. Patent No. 4,142,234, and IBM Tachn
iLcal Diaeloiure Bullie
tinVo 1.18 No, 12, May 197
No. 6, and U.S. Pat. No. 4,056,844, disclose hierarchical storage configurations that generally include cache storage, but the caches are not divided into separate data and instruction portions or otherwise affect the operation of the memory system. It does not contain any special control fields accessible to the program for control.

U.S. Pat.
The system is described.

No. 4,070,706 discloses a cache storage system in which the cache is divided into a data section and an address section (not a directory), but the cache is not divided into a data section and an instruction section.

U.S. Pat. No. 4,245,304 describes a split-cache system in which operations are divided into two half-cycles so that instructions can be accessed from or written to the cache during the same half-cycle. . This patent does not disclose or suggest special control bits in the cache directory to control cache/main memory operations.

U.S. Pat. No. 4,075,686 describes a cache storage system that selectively bypasses the cache during memory access operations according to the coding of specific instruction bits, thereby reducing execution time for certain types of operations. There is.

U.S. Pat. No. 4,142,234 discloses a cache system that eliminates cache-directory specific queries to reduce the size of specs.

U.S. Patent No. 3,618,041 and IBM Techni
cal Disclosure Bulletin
nVol, 22 No. 11, April 1980
, p. 5183 outlines the basic concept of dividing the cache subsystem into separate instruction and data parts and providing complex operating system support for overlapping operation of the two separate caches. has been disclosed.

US Pat. No. 4,197,580 generally discloses a single cache subsystem using special valid bits and "tags" for controlling certain read-write operations. This bit is used to avoid unnecessary cache cycles rather than unnecessary main memory cycles, and the present invention is intended to avoid unnecessary main memory cycles.

C8 OBJECTS AND SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved hierarchical storage having a large capacity main memory and a small capacity cache storage divided into two separate parts, each dedicated to the storage of data and instructions. It is to provide configuration.

According to the invention, such a cache storage arrangement has at least one special control bit in the cache directory for each line that affects the operation of the cache.

According to the invention, such a cache storage device has at least one special control bit used in the cache line replacement process.

In accordance with the present invention, such a cache storage system has control bits that indicate whether a line in the data φ cache has been modified since it was originally stored therein.

In accordance with the present invention, a control bit is provided to indicate whether a given cache line is valid or not.

In accordance with the present invention, temporary data storage space is provided for scratch pad storage, etc., without requiring queries to main memory.

A cache subsystem is provided.

In accordance with the present invention, all mass controls are controlled by the system software and no controller is required to notify the instruction cache when changes are made to data stored in the data cache. A cache subsystem is provided.

The objects of the present invention are achieved by a hierarchical storage system for use with high speed data processing devices, which typically includes a large capacity, relatively slow main memory and a much smaller capacity, high speed cache storage.

Cache storage consists of two separate parts, each dedicated to the storage of data and instructions. Each portion includes a cache directory having a storage location for each line stored in the cache. The above locations in each of both directories provide a means for storing the high order bits of the main memory address of the data stored in each cache line, and each time memory access to a particular line is requested. Means is provided for storing special control bits settable by the system for controlling operation of the cache storage device. Both cache directories described above include control bits in each directory entry to indicate which of a plurality of cache subset lines should be replaced when a cache miss occurs.

Both directories also include a plurality of control bits at each location to indicate that a given cache line specified by a particular cache directory location is invalid. Additionally, each memory location in the cache directory for a data cache indicates that a given cache line specified by a particular address stored in the memory location has been modified by a previous CPU operation, and that the cache It also includes bits to indicate that the corresponding line in main memory must be updated by a "write back" operation before a particular line in main memory can be replaced.

It also provides means for setting various control bits in the cache directory and memory access by the CPU.
Means are provided in the cache control system for loading and storing particular cache lines from main memory and vice versa independent of access operations.

D19 Best Mode for Carrying Out the Invention (-) General Explanation of Storage Hierarchy The performance of a system (CPU) that operates at extremely high speed is
Highly dependent on storage subsystem performance. Current technology provides caches with access times of 60 nanoseconds and access contention times as fast as about 115, or about 30 nanoseconds.
It is possible to produce 0 nanosecond backing storage. Improving the performance of the storage subsystem gives very good results in terms of overall system performance.

The present invention aims to improve the performance of the cache subsystem in two areas of operation. The first
The objective is to improve the cache hit ratio, ie, to increase the percentage of storage references that are found in the cache and therefore do not require access to main storage and the associated delay. The second is to improve the time to access a line from backing storage when a cache reference fails.

Considering the first objective, it can be seen that frequent access to backing storage is not necessary for correct execution of a program.

Frequent accesses to the backing storage occur because the hardware cannot infer the meaning of the software. Generally, these unnecessary references fall into two categories.

The first is that the program wants a new block of memory. This means that when a procedure is called and requires temporary (i.e. AUTOMATIC) storage,
This can occur when a second level interrupt handler requires a register save area, when an access method requires a buffer, or when a program issues a GETMAIN request.

What is similar in all of these cases is that the program
Don't be concerned about the old contents of your storage device.

The program just wants some storage. However, most current storage subsystems flush old lines from backing storage to cache when the first reference to such storage occurs. The reason for doing so is that the first reference is to at most one word in the line (since the unit of access between the CPU and the cache is a word), and subsequent requests refer to other words in the line. This is because the subsystem cannot know that it does not need the words until it updates them.

The second case is when the program no longer needs the block of storage, even if its contents have changed. This occurs when temporary storage is freed on return from a procedure, when buffers are freed,
Generally, this can occur when a program issues F'REE MAIN.

No currently available storage subsystem is known in the art that has a mechanism for determining that such writeback of modified lines is unnecessary.

Therefore, the CPU has the basic hardware mechanism (in the form of instructions) that software can use to provide such information to the hardware, i.e., the cache control mechanism.
It is advantageous to provide Specifically, two instructions are defined that are generally executed by cache control hardware to enable such software control of cache operations. They are defined as follows.

(1) Data cache line set (2)
Data Cache Line Invalidation These instructions are issued by the control program and generated by the compiler for the application program. These instructions ensure that such unnecessary backing storage accesses do not occur.

In fact, the temporary storage required by procedures is managed in the stack, and even supervisor calls are called on demand, so that dispatched process data is persistent (i.e. S RAT I e
The backing storage is not accessed for dispatched process data until the stack depth is large compared to the cache size. Backing storage therefore begins to play a role similar to that played by secondary storage (ie, file space and paging area). Using such a strategy, the cpu's activity during interrupts is controlled by the "priority level interrupt" system.
No more than an activity performed at the end. This "priority level interrupt" system also must store its internal registers in high speed memory (ie, register space).

The difference in the aforementioned CPU configuration is that it does not dedicate high speed memory to this purpose, thus saving costs. Although CPUs with such architectures can detect cache misses during 'redisbatch',
It is not in the response critical part of the route.

As with most systems, CPtJ retrieves instructions from the cache in anticipation of execution. The CPU is
It has a prefetch buffer (a 6-word buffer is assumed in the system disclosed here), and
tries to keep it full. Filling this buffer may result in a cache miss and initiate an instruction fetch from backing storage.

However, there may be a branch instruction that is already in the buffer but not yet executed before the instruction that is fetched. In the present architecture, it is envisioned that the CPTJ's prefetch mechanism scans the OP code and inhibits such unnecessary backing storage fetches. In fact, while scanning the OP code for this purpose, the N0OP (/- operation) can also be recognized and deleted, so that its execution time becomes zero.

A second method of improving storage subsystem performance based on the teachings of the present invention involves making backing storage accesses faster.

When a word, whether data or instruction, that results in a cache miss is requested from the storage subsystem, the backing storage is accessed for the necessary line starting with the requested word. This word is then sent directly to the CPU, bypassing the cache, and the line is stored in the cache while the CPU continues executing instructions. Thus, for example, a load instruction that causes a cache miss takes only 340 nanoseconds (minus the amount by which the instruction can overlap with the load) to complete.

Since the instruction prefetching mechanism is inherently asynchronous to the data fetching mechanism, it has been found advantageous to separate the cache into two separate parts, one for instructions and one for data.

As a result, each cache allows the backing storage to be accessed independently and in an overlapping manner.

This feature can effectively double the access speed if the particular instruction stream being executed allows. Other benefits are possible with such an overall cache subsystem architecture.

The cache subsystem is constructed and defined such that no modification of instructions in the instruction cache is permitted. Therefore, instruction line fetches never require write-backs and are not delayed during instruction cache misses.

Each cache part (instruction part and data part) is designed in a two-way set associative manner. Therefore 4
Some of the benefits of the way set associative approach are obtained without the expense. From now on, LRU (lea
Special control bits or fields, called bits (used) bits, control the normal replacement procedure that determines which of two lines should be replaced in the addressed region of the cache after a miss. Allows the associative fist cache to be held.

Each cache characteristic, such as overall size, depth, line size, and other physical parameters, can be selected to suit the particular purpose, instructions or data, for which the cache is intended. Similarly, separate replacement algorithms can be used to take advantage of differences in access characteristics or patterns between instructions and data. In the prototype of our system, a similar replacement algorithm was used for both caches with satisfactory results, but adapting the algorithm to a particular cache should yield some improvement.

As mentioned in the Background section, split caching has been known in the art for several years, but its implementation using traditional architectures has created serious problems. Since instructions can be legally modified in the data cache and then branched to, all modifications must be notified to the instruction cache, and
It must be ensured that modified lines are invalidated. But in reality, in today's more sophisticated systems, instructions rarely change. Therefore, it is much more efficient to perform this function, i.e., changing instructions, in software (when needed) rather than providing a mechanism in the hardware to repeatedly perform this function each time a data change occurs. It was determined that it was.

As mentioned above, this system assumes that when a change is required, an instruction is placed in the data Φ cache and that software is provided to treat it as data. Obviously this can be done easily. However, the data cache does not inform the instruction cache of modified lines.

Therefore, those changes are not reflected during the next branch to the modified instruction. To achieve such control, the split cache subsystem architecture disclosed herein provides an instruction called "Instruction Cache Line Invalidation."

Software must issue this command to purge old commands. The architecture also provides an instruction called "data cache line store." This instruction ensures that modified instructions are reflected in backing storage. In the most common case, when loading from disk causes a change in the siprogram, only the first instruction must be issued.

An additional advantage of this cache subsystem architecture is that it can naturally support separate virtual storage for caches, instructions, and data that operate separately and independently.

Thus, for example, software strategies are possible in which a single reentrant copy of the APL interpreter can be executed for many different user areas with minimal bus time by repeated memory operations.

This architecture does not allow sharing of pages between virtual storage devices. This restriction provides great simplifications from both a hardware and software perspective.

First, it allows the cache to operate in virtual mode. In other words, the cache can be accessed using virtual addresses rather than real addresses. Apparently the line is in cache (more than 90% of the time)
When found, there is no time loss or quality loss from running the relocation algorithm.

Traditional relocation systems store fleeting amounts of high-speed storage in look-aside tables (DLs) on page tables.
AT) is reserved for exclusive use. Storage is generally the same technology as cache and is therefore very expensive. In this architecture, page tables are usually accessible through the cache, and their expected high frequency of use generally results in a very high probability of a cache hit. D.L.A.
It is possible to approximate T. Therefore, abnormal +7) DLAT can be detected without significantly affecting system performance.
The investment in can be appropriately directed to increasing the cache size or can be eliminated altogether.

Before proceeding with a detailed description of the hardware implementation, the special hardware instructions provided, and the various operations that can be performed within this cache subsystem, a brief description of the following figures and their relationship to each other is provided. state

FIG. 1 is an overall block diagram of a hierarchical storage configuration clearly showing the relationship between the CPU, instruction cache, data cache, and main memory. Direct storage adapter (DMA)
) are also shown as being directly connected to main memory. As previously mentioned, in most cache based systems, I/O passes through the cache subsystem and is stored in main memory, with the attendant reduction in system throughput. In this system, input/output is prohibited from passing through the cache, and in fact most of it passes directly through the DMA. In fact, steps are taken to prevent I/O operations from interrupting cache-initiated stores and reads, as described below. Cache-initiated stores and reads occur when cache misses occur that involve "store-through" operations.

Also, as will be pointed out later when referring to the figures, there is a data flow line from the data cache to main memory, but there is no flow line from the instruction cache to main memory. “Store-through” the instruction part of the cache
This should be kept in mind since changing the instruction in the instruction cache is not allowed.

FIG. 2 (FIGS. 2.1 and 2.2) is an extension of FIG. 1 showing the data path between main memory, cache, and CPU0 in more detail. The multiplexer in the figure (
MUX) is a conventional logic circuit that performs the gate functions for the various data transfers provided in this hardware embodiment.

One parity bit per byte of data is carried through input/output, main memory, and both caches; parity bits are transferred to the CPU and
Note that U-kamo-uke will not be taken.

FIG. 2 illustrates a word bypass mechanism that provides a direct data path for a 4-byte target data word from main memory to the CPU. The basic size for data transfer between cache and main memory is a 32-byte line. This data is received from main memory as a series of four double words of eight bytes each, and this storage architecture ensures that the first double word received always contains the target word. be done.

The destination word is stored in the cache at the same time as the CP
Bypassed to U. The data write-back path from the cache to main memory writes the data as a series of eight words of four bytes each through a write-back multiplexer.
Note that this is only provided for caching.

If you refer to the instruction cache and data number cache in FIG. 2, you will notice that the existence of two subcells A and B is shown. As mentioned above, the existence of these two subsets is a requirement of the two-way set-associative addressing architecture.

Next, the data flow diagram shown in FIG. 2 will be briefly explained. When referring to the diagram, the direction of data flow is generally from the top of the diagram to the bottom. Both instruction cache 10 and data cache 12 can also receive data from main memory 14.

However, only the data cache can receive data from the CPU. This was mentioned earlier.

This is because in this architecture it is not possible to change instructions in the instruction cache (therefore, the output of the instruction cache is
This is because it only goes to the PU. Similarly, since the instructions in its cache cannot be modified directly by the CPU, the instruction cache is routed to main memory 14 for loading via fetch launch 20 and input multiplexer 22.
All you have to do is connect to it. Therefore, instruction cache 10
To store instructions in the instruction cache, a line of instruction data is passed through the fetch latte 20 and ultimately transferred to a selected section (line) of the instruction cache. Similarly, to transfer instructions from the instruction cache to the CPU, data words are read from selected sections of the instruction cache and sent to output multiplexer 16 and multiplexer 1B.

instruction cache 10 and data cache 12, respectively.
associated directories 11 and 13 (Figure 3)
1 and 32)) are shown as (functionally) connected to the cache. It should be understood that these directories are not included in the cache data flow path, but are physically tied to the operation of the cache. As will be explained in more detail below, for a given cache access, the same line and associated directory entry in both cache subsets are accessed in parallel by the same line determined for the D field of the address. Ru. Additionally, this access makes the data in both cache subsets A and B available to the system.

These directories are typically created as separate, very fast storage devices in a suitable high speed circuit family, such as emitter-coupled logic circuits. In the embodiment disclosed herein, the cache access time was 30 nanoseconds, while the directory access time was approximately 12 nanoseconds. This is to allow logical decisions to be made based on directory entries when two data subsets are available from the cache.

As mentioned earlier, the data cache is located in main memory 1.
It can be loaded from 4- or from c, pu:so.

If the data line is to be stored from main memory 14,
Data flow passes through the fetch latch 20 shared by both caches and then through the data cache byte input multiplexer 48 into the data cache 12 itself. If a data line is to be transferred from CPU 30, the data path is routed to byte input multiplexer 4 as shown.
8ft and then enters data number cache 12. To transfer data from data cache 12 to the CPU, the data passes through output multiplexer 62, bypass multiplexer 34, and enters the CPU's data register.

When a data cache miss occurs, assuming that the line is valid and indicates a change, the data cache miss occurs before a new data line can be loaded into that particular line in the data cache. This line of data must be written back to storage 14. For this purpose, writeback latch/multiplexer 52 is activated.

Byte selection mechanism 49 and byte write gate 50 are
Controls the storage of data in the data cache.

During a CPU load OP with a directory miss, byte selector 49 gates so that only double words of main memory data pass through byte input multiplexer 48, and all byte write gates 50 are activated.

When CPU store OP with directory-hit, byte selector 49 gates only CPU data words through byte input multiplexer 48 and write gate 50 selects the number of bytes stored in the subset of data cache. used to control. This C
The PU architecture can store 1.2 or 3 bytes of data.

During a CPU store OP with a directory miss, byte selector 49 combines 1.2 or 3 bytes of CPU data into the first missed double word from main memory and passes it through byte input multiplexer 4B. All 4-byte write gates 50 are activated. For the remaining three double words of the missed line, byte selector 49 allows only main memory double words to pass through byte input multiplexer 4.

Both caches have a bypass mechanism so that a fetch request that results in a cache miss for either cache will bypass the instruction and data caches, respectively, if the data is available from main storage. About Cache Word Selection Multiplexer 3
8 or 40, the data can be sent to the cache and the CPU simultaneously. Thus, the CPU does not have to stop while waiting for the data (or instructions) to first be completely stored in the cache.

As discussed in more detail below, only the destination words of the instruction or data lines are bypassed directly to the CPU.

Therefore, it can be seen that the overall architecture of the present split cache subsystem is basically of a conventional character. That is, a data path is provided for loading the instruction and data caches from main memory. An additional means is to transfer data from the CPU.
Load cache. Similarly, both caches must each be able to transfer instructions and data to the CPU, and the data cache must also be able to write data back to main memory. Finally, both caches are equipped with a bypass mechanism whereby the addressed words in a line are immediately sent to the CPU and the line is stored in the cache simultaneously to minimize CPU delay. Therefore, it can be seen that the actual 7-ware architecture of the present split cache subsystem is quite straightforward. The improved functionality of the cache subsystem disclosed herein is provided by:
The actual use of the cache and the unique organization of the cache directory and special control bits provided within it.

Returning briefly to FIG. 2, it will be noted that both caches are divided into two subsections A and B by separate line selection mechanisms as shown. This will become clearer in the explanation that follows. This cache subsystem is two-way set associative. When a given line in the cache directory is addressed, two different pages (A and B) are accessed in the cache from each of the two data lines.
) is actually addressed. The final line selected will be determined by the destination page and
2 included in address pt and cache conflict directory
is determined by comparison with the two page references PA and PB. The word addressed from the selected line is
Gated to the CPU by output multiplexer 16 or 32.

Also, with reference to FIG. 2, it will be noted that the various multi-bit cables connecting each unit of the cache subsystem are shown as containing 32 or 36 bits. 32-bit cable and 36-bit cable
The cable difference is that, within the scope of this embodiment, a 36 bit cable contains 32 data bits and 4 parity bits. Generally 4 parities
Bits are removed or deleted when transferring data (or instructions) from the cache subsystem to the CPU. It is also noted that the cable between main storage 14 and eject latch 20 includes 72 bits. As will be readily appreciated, main memory is organized to read and transfer double words, so this cable only contains two 36-bit words.

The split cache subsystem is now “
-The general description of the entire software ends. The general construction and operation of this hardware is believed to be straightforward and well known in the abutment art.

Referring to Figure 3 (Figure 3.1 and Figure 3.2), 1
A detailed functional block diagram of Byte's data cache directory and its associated logic and control circuitry is shown in FIG. In the embodiment disclosed herein, it is assumed that a 24-bit CPU address is placed in register 60.

Of this entire 24-pit address, the left 11 bits (Pt) contain the page address of the memory reference. The 8-pit D field contains the line address of a particular storage reference within the specified page. It is pointed out that this address is actually used to address one of the 256 lines in the cache directory (and therefore also within the cache itself).

Finally, the 5-bit W field on the right is the word or byte offset within the entire 32-byte line.

That address or segment is actually used to address the intended pi)f pointed to by the global address.

As can be clearly seen from the figure, the cache directory contains 256 entries, and each entry (0 to 255) has a total of 7 information fields PA%PR,VA1V
Contains B, MA, MB%LRU'i. As explained in more detail below, PA%VA and MA refer to each line in the cache that belongs to subset A, with element P
B, VB and MB are related to the subsidiary) H. L
The RU bit indicates which of the two subsets 2-in was most recently accessed, and thus controls the replacement of a particular line in the cache (in subsets A or B).

During operation, when performing cache access, CP
A particular line pointed to by the D field of the U address causes one of the 256 entries in the directory to be accessed. It must then be determined which of pages PA and PB matches the destination page address pt in the CPU address. This comparison is performed using two comparison circuits 62.
and 64 is executed. If either page address PA or PB matches pt, the "Hit=A" line or the "Hit=BJ" line is activated.

The validity pin) V or modification pin) M is then queried to find out whether access can continue.

The details of this operation will be discussed in detail later. 2
If neither page address PA or PB wants to match pt, NAND circuit 66 activates the "miss" line and directory update logic 68 informs the system that a "miss" has occurred and the new data line is cached. - Indicates what must be brought into the system.

Which of the two subset-lines is replaced is
Determined by the LRU bit. A 7-bit line, designated as a "write strobe," allows new data to be entered into the selected field or bit position of a particular entry in the cache directory, as will be explained in more detail below. Of course, which bits are changed and when a new page address is inserted into the PA or PB field is determined by the particular instruction being decoded by the CPU instruction decoder 70.

The operation and organization of the cache directory and its associated controls is believed to be straightforward and given the functional description and block diagram disclosed herein.
This can be easily accomplished by computer technology experts.

FIG. 4 includes a series of tables illustrating the addressing and structure of the cache subsystem. In addition, the figure shows the effect of cache subsystem size on various parameters such as the addressing field.

In short, six different types of cache ψ size are set to 4, 8
and 16, it will be noticed that the directory entry contains two page identifiers Pa and Pb and five special control bits Va, Vb, M'a, Mb%LRU. The specific manner in which these special control bits are utilized will be discussed in more detail below.

The addressing of directories in the cache is also shown at the top of the diagram. Here, 24 bit C
Contains three fields: PU destination address U, P (page), D (line), and W (byte). As can be seen, the cache itself is addressed using the D and W fields, but the directory is addressed using only the D field in such a two-way set-associative cache. As will be understood by those skilled in the art, the directory is accessed and then it is determined whether the P field of the destination address matches either directory entry Pa or pb. This figure will be explained in more detail later.

5 through 11 are tabular summaries of the operations that occur within the hardware of the cache subsystem as a result of each particular hardware operation. The expression "hardware procedures" means a list of things that occur in the system as a result of operations on the cache subsystem hardware.

Figures 12 through 18 are all flowcharts and are closely related to the various cache subsystem operations described in Figures 5 through 11, as indicated by the labels attached to each figure. In other words, there is a flowchart for each hardware plunger listed, e.g.
The illustrated data cache retrieval hardware procedure is shown in greater detail in FIG. These flowcharts thus clearly describe the detailed testing and branching operations and specific operations that occur in the enumerated blue blocks as we proceed along the various branches. These operations will be explained in more detail later, but are generally considered to be a partial explanation of the operation of the cache subsystem.

The events that occur in such cache subsystems, as well as the function and purpose of all hardware components specifically shown in FIGS. 2 and 3, are believed to be well known in the art. Those skilled in the art should have no difficulty in creating the cache subsystem of the present invention using the overall cache subsystem configuration described in Figures 2 and 6 and the detailed flowcharts. .

(b) Detailed description of the operation of the storage hierarchy The following description is
The hierarchical storage of the present invention is particularly useful in certain versions of minicomputers.

It contains up to 16 megabytes of real main memory. Achieves 24-bit addressing to the hierarchical storage system. The 24-bit main CPU architecture is not critical to the invention, other than that it must provide the proper storage instructions as detailed herein.

The embodiments of the storage hierarchy disclosed herein include a cache fist subsystem that operates at CPU speeds and
It consists of up to 16 megabytes of FET main memory operating at speeds of 5.

The CPU communicates directly with the cache subsystem;
The latter, on the other hand, communicates with the main memory (see FIG. 1). Input/output data can be sent to main memory via a direct storage adapter (DMA), but cache
Subsystems cannot be contacted directly.

The unit of data transfer between the CPU and the cache subsystem is a 4-byte word. The unit of transfer between main storage and the cache subsystem is a 32-byte line. Line transfers occur from main memory via four 8-byte double words and to main memory via eight 4-byte words (see Figure 1). I/O data transfers to and from main memory are
This is done via 4-byte words under the control of the A adapter.

Note that one parity pit per data byte is carried through the storage hierarchy. Parity pits are not transferred to or from the CPU.

(c) Earth! The hierarchical storage subsystem disclosed herein is based on a system architecture designed to minimize CPIJ idle time caused by references to the storage hierarchy. This storage architecture is designed for CPUs with new instructions available every cycle, so a separate instruction cache matched to CPU speed allows instruction fetches to proceed independently of data fetches in the memory hierarchy. Do it like this. This architecture also prohibits direct I/O communication with the cache subsystem;
Therefore, the possibility of the CPU being locked out due to input/output interference noise is eliminated. Similarly, to avoid performance degradation due to excessive references to main memory, all storage is directed to the data cache and is not automatically "stored through" to main memory.

Because of this architectural type, changes to the contents of main memory caused by I/O operations are not immediately known to the CPU, and changes to the contents of the data cache performed by the cpu are not immediately known to the I/O or instruction cache. It may never be known.

However, this high-level system architecture provides a limited set of cache management instructions that allow programs to control the relationship between main memory and the contents of the cache subsystem.

These management instructions only handle 32-byte cache lines, allowing the system to avoid unnecessary cache references to slower main memory. For example, when storage is no longer needed, the use of a data cache line invalidation instruction removes unnecessary data from main memory, even if the line in the cache has been modified by previous CPU storage. prevent unnecessary writebacks.

(d) Cache subsystem The cache subsystem consists of 16 instruction caches and 16 data caches. Each cache is organized as a two-way set associative. Therefore, each cache consists of 8 subsets A and 8 subsets B. One cache can contain up to 512 lines of 32 bytes each. There are 256 lines in subset A and 256 lines in subset B.

(,) Directory Each cache has an associated directory.

This directory has an ultra-fast bipolar random
Included in the access storage device.

Each entry in the directory describes the existence and status of two possible cache lines, one in each association subset. Therefore, this directory must be large enough to contain entries equal to the maximum number of lines that can physically exist in one cache subset. Each cache subset can contain up to 256 lines, so the directory must contain 256 entries. This structure is shown in FIG.

(e-1) Address Field For this embodiment, it is assumed that the host system uses 24-bit addresses. Conceptually, an address can be subdivided into three fields: the page address, the address of the line in the page, and the address of the byte in the line. These subfields will be referred to herein as P%D and W, respectively. This configuration is
This is detailed in Figure 3. The table in FIG. 3 also shows the range of cache sizes (from 4 to 16K) and the effect of size on various cache and directory parameters.

Each directory entry has two cache successors)
Pages of lines stored in (PA and PB)
It has two address fields containing the address and a control bit field that directs the hardware algorithm for the cache instruction being processed. The directory is the line address of the destination address.
Addressed by subfield. cache·
As the size decreases, the size of the line address subfield decreases, but the size of the page address subfield increases. (See FIG. 3) In fact, at this time, more pages of smaller size (fewer lines per page) are formed.

(@-2) Control Bit Field The instruction cache directory contains three control pits for each entry, and the data cache directory contains five control bits. Both cache directories have each entry one for each subset,
Contains a total of two valid hits (vA and VB) and one LRU bit. Moreover, the data cache
There are 2 directories, one for each subset.
(See Figure 3).

The valid bit is used to control the relationship between cache and main memory contents. They are set to ``1'' when a line in the cache is replaced by the version currently residing in main memory. Valid bits for a line can be turned off by cache management instructions from the processor. When a program references an invalidated (V double) line, the invalidated line is replaced by its current version that resides in main memory.

The LRU bit determines which subset receives the replacement line from main memory. The state of the LRU pit is controlled by cache hardware procedures and cannot be managed by the processor under program control. LRU Replacement Replacement When it becomes necessary to replace a line in the cache with a new line from main memory, a valid strategy to follow is to replace the line in the associative set that has not been used in the recent past. It is based on the premise that this is true. Since the cache is truly two-way set associative, a single control bit can be opened to make this decision, and the least recently used becomes the most recently used.

Changes in the data cache directory are
Set to ``1'' when a processor store instruction occurs. This indicates to the cache control hardware that the version of the line in the cache has been updated and must write it back to main memory if the line is to be replaced. However, the line is disabled (V=
O), writeback is prohibited. I would like to point out again that this is not possible with the instruction cache.

(f) Realization of prototype The above memory hierarchy was realized as a prototype. The main memory was designed using a 1.0 MB pre-FE device with a cycle time of 300 nanoseconds. A dual cache was designed using bipolar storage of 16 bytes, each with a cycle time of 60 nanoseconds coinciding with the CPU's cycle time. Each cache contains 256 lines in each of the two associative sets, or a maximum of 512 lines. Moreover, the maximum size of each cache can be manually reduced to 8K or 4 bytes, thereby reducing the overall contents to 25 bytes each.
It can be reduced to 6 or 128 lines (see Figure 3).

(f-1) Physical Package The cache array, both instruction and data cache, utilizes bipolar transistor storage technology and is packaged into four cards. Each card is 2 to 8
There were 4 cards per cash, including 18 bits. The embodiments described herein are for illustrative purposes only. The general structure of such a cache is well within the scope of the architecture definition, control functions, and instruction format described herein to those skilled in the art of abutment.

(g) The cache interface to the cache-organizing CPU is 3 wide.
The interface to main memory is 72 bits wide (double word including harness) for retrieval or 36 bits for storage. It is desirable for the initial fetch to be able to access the A and B subsets simultaneously at the destination address. Various cache storage organizations are possible, assuming that the word at the destination address can be read from both associative subsets simultaneously.

This is because the subset in which the object resides is not known until that information is provided by a directory access later in the cache cycle. For this reason, and to save time, the directory and cache are accessed simultaneously.

If directory access indicates that the object does not exist in either subset A or B (a miss),
Data from the cache access is ignored and main memory is accessed for the line containing the target data. In the case of a data cache miss, it may be necessary to write back the lines currently in the cache before replacing them with new lines from main memory.

If the destination page address corresponds to a directory entry for subset A or B, the correct subset is immediately known and the destination data from the cache can be gated directly from the subset to the CPU. Using this strategy, the total time required to send data to the CPU is minimized.

Access to main memory due to cache miss tli
, 32/<ite, which is multiplexed into the cache as four consecutive double words.

This storage system architecture specifies that in the event of a cache miss, the double word containing the target word is first returned by the storage controller. remaining 3
Two double words are returned from successively adjacent addresses, generated by incrementing the destination address by double words, until all four double words contained in that line have been returned.

Since this first double word always contains the destination word, memory misses are handled in the data cache by combining CPU data with the first double word from main memory.

(h) Instruction Cache Retrieval A flowchart of the instruction cache retrieval hardware operation sequence is shown in FIG. 13 and summarized in a table in FIG. A block diagram of the data flow for both caches is shown in Figure 2.1.

Instruction cache fetch requests initiate accesses to the cache array and directory. Directory access is overlapped with cache access. Both caches are organized such that the target word of the fetch is busy accessed from both the A and B subsets simultaneously.

This is done without knowing in which subset the target data is present, or even if the target is not present in either subset at all.

(h-1) If the hit target address corresponds to a directory entry in a subset of A or B, the access to that directory is a hit. The correct subset is immediately known and the target data can be gated from the Hituken subset to the CPU if the line is valid. No additional time is required to access the cache array. The LRU bit for that directory entry is then switched to the opposite subset. Of course, the LRU may already indicate the opposite subset as a result of previous operations.

(h-2) Miss or Invalid Hit If the target address does not correspond to a directory entry in either subset A or B, the access to that directory results in a miss. Data accessed from the cache array is ignored and the fetch request (along with the destination address) is forwarded to main memory, which returns the 32-byte line as four 8-byte doublewords. The first doubleword returned is the specific 4-byte word pointed to by the destination address (as described above).
Must include word. To increase speed, this word is simultaneously bypassed to the CPU while the double word is stored in the cache. This data path is clearly shown in Figure 2.1. The next three double words are sent back from main memory in sequence and stored in the cache when they arrive.

It is possible that the first doubleword containing the object returned by main memory is actually the l4 doubleword of that line. In this case, the remaining three double words on that line are also returned sequentially, but starting with line q crossing. Thus, regardless of which double word arrives first, the other three double words are received sequentially.

It should also be noted that the lines retrieved from main memory contain as data a series of instructions to the CPU. It is assumed that the CPU contains a prefetch stack that is four levels deep.

This prefetch stack attempts to keep itself filled and constantly sends fetch requests to the instruction cache, thereby providing new instructions each machine cycle based on the requirements of the overall CPU architecture. In the case of an instruction cache miss, more than one of these prefetch levels may be empty. When a new line arrives from main memory, the cache continues to bypass data to the CPU until the end of the cache line is reached or the CPU prefetch mechanism becomes full and stops the bypass action. The number of words that are thus CPUK bypassed can be any number from a minimum of one word to a maximum of all eight words in the line.

(h-3) After a directory update error, the directory has a new destination address (pt)
The valid bit for the subset in which the new line was stored is set in rIJ and the LRU bit is switched to the opposite subset.

If the destination address encodes an invalid (V=0) directory entry, the result is an invalid hit and the hardware action is the same as if a miss had occurred, with the following two exceptions. First, the new line enters the coded subset regardless of the state of the LRU bit, and second, the address in the directory is not updated. This is because the address yielded a valid code, but the data is invalid and must be replaced. Following loading of a new line, the directory LRU bit is switched to the opposite subset and the valid bit for the stored subset is set on (to "1"). In this case too,
It should be noted that the only path in which the "valid" bit (VA or VB) can be zero is through the CPU using the "Instruction Cache Line Invalidation" instruction.

FIG. 5 summarizes this instruction cache retrieval hardware order described above.

(i) - The order of operation of the hardware for data expansion/cache retrieval is shown in FIG. 14 and summarized in FIG. The entire data flow diagram is shown in Figure 21.

(i-j) Hits The data cache retrieval procedure for valid hits is the same as the instruction cache retrieval procedure described above and need not be repeated.

(i-2) Miss or invalid hit The data cache retrieval operation order in the case of a miss or invalid hit is as follows:
This is similar to the instruction cache fetch order described above with two exceptions.

First, on a miss, the valid line that has been modified by CPU storage must be written back to main storage before it is replaced. Second, unlike the instruction cache, which can bypass up to eight words to the CPU prefetch stack when a miss occurs, the data e-cache only bypasses one word to the CPU on a miss.

When a fetch miss occurs, the line to be replaced is checked for changed bits and valid bits. A and B
Which subset of is to be replaced is determined by the LRU bit. If the line is invalid or unchanged, no writeback occurs and a fetch request for the target line is sent to main storage. The first doubleword of the line returned by main memory contains the target word, and the cache hardware strips out this word at the same time that the first doubleword is stored in the cache. , bypassing it directly to CPH. Following storage of the new line, the directory is updated as described for instruction cache fetches.

(i-3) Writing back If the line to be replaced is valid and has been changed, it must be written back to the main memory before a fetch request is issued for the replacement line.

The page address of the line to be rolled back is contained in a directory entry, and that address is provided to main memory for writing back. The cache takes four cycles to read the four double words on the writeback line, and multiplexer 5
2 divides them into a series of eight words and transfers them to the storage input register (SIR) of main memory (see Figure 2.1).

In the normal case, it may occur that an I/O gains access to main storage between writeback and issuing a fetch request for a new line, thereby stalling the data cache during the I/O operation. To prevent this from happening, a particularly high priority fetch request from the data cache can be issued to main storage, especially in the case of a data cache miss that involves a writeback. The effect of this high priority request is that the old (writeback) line
The purpose of this is to cause main memory to initiate automatic retrieval of new lines while loading into R. This allows the data
A cache-only back-to-back main memory cycle is provided, allowing fetches for new lines of main memory to occur before storing old lines. The old line is temporarily stored in SIR.

To implement this strategy, the data cache is accessed for the first double word of the line to be written back, sending the data cache controller the write back address, the first write back word, and a high priority request. When main memory acknowledges the request, the data cache immediately begins fetching the remaining three double words of the old line, changing the address into main memory from the old (writeback) address to the new (destination) address. Change to The writeback line is transferred to main memory SIR one word at a time. When main memory returns a new line of data, the data cache begins storing a series of four double words while the new line is being stored, and the target data is
Bypassed to PU. Next, directory information is updated.

FIG. 6 summarizes the sequence of operations of the data cache retrieval hardware as previously described, and FIG. 14 shows step-by-step details of the operations in flowchart form.

(j) Data cache record.

A flowchart of the sequence of operations for the data cache storage hardware is shown in FIG. 15 and summarized in FIG. Reference should also be made to Figure 2.1 for the data flow diagram.

A quick comparison of the flow diagrams of Figures 14 and 15 shows that the data cache retrieval and storage algorithms are quite similar. The main difference is simply CPtJ
is the direction of data flow between the cache and the cache. The following discussion of the storage process assumes familiarity with the retrieval process and focuses on the differences between the two.

Unlike a fetch request, a store request to a data cache does not automatically initiate an access to the cache array. Both subsets of the cache' array can be read simultaneously from a fetch operation, but only one subset can be written to for a store operation. Therefore, a storage operation cannot begin until the results of the directory access indicate whether the object is present in the cache, and if so, in which subset. All storage operations require extended cache cycles because accesses to the cache array cannot overlap with accesses to the directory as in the case of fetch operations.

To accommodate the required sequential access to the directory and cache array, storage cycles are
It must be expanded by 6.

The storage is organized as columns of 32 pit words.

Each word can be subdivided into two 16-bit half words or four 8-bit characters. Processor storage instructions are: 1.
Works on 2- or 3-character entities. These three types of processor storage are distinguished by the cache hardware as three different storage commands: storage 8 (1 byte), storage 16 (2 bytes), and storage 24 (3 bytes). The Rh diagram of data cache storage in FIG. 14 applies to all three storage commands.

The CPU supplies a 32-bit data word with each store command and pre-aligns the byte to be written within the word. The lowest two pits of the storage target address + the specific type of storage command are the four byte write gates (s in Figure 21).
o) Provide sufficient information to the data cache control hardware to determine which of (wo-w3) to activate.

(j-1) If the hit storage destination address exists in the directory, the subset to write to is identified and the cache cycle is expanded to accommodate the storage. 32-bit storage data word + generated parity (4 bits)
is applied to all array cards simultaneously. The subset selection intersection of the byte write gates determines which bytes are written. Following storage, the directory is updated by turning on the change bit for the hit line and switching the LRU pits to the opposite subset.

(j-2) If the miss or invalid hit storage target line is invalid or not in the cache,
The cache cycle is not extended and the line must be retrieved from main memory. If the line to be replaced is valid and has been modified, then writeback is required and the writeback mechanism operates exactly as described for data cache retrieval.

The data cache has an input byte multiplexer 48 (
(see FIG. 21). When there is a miss, this multiplexer is set up to combine the data from the CPU with the retrieved data returned by main memory.

The object of this storage is contained in the first double word of line data returned by main memory, so the CP
Combining U data only occurs when the first of four double words is stored in the cache. The last three doublewords and all bytes of the first doubleword not selected by the CPU are switched to the main memory fetch data path by the input multiplexer. During four double word stores all byte write gates are turned on and one subset is selected. The bytes modified by this storage are therefore controlled exclusively by the input multiplexer and subset selection.

Instruction cache fetches update the directory in the same way as data cache fetches, except that the modified bit is turned on if the replacement line receives the store following a memory miss (or invalid hit). Ru.

FIG. 7 summarizes the data cache storage node-ware procedures.

(k) Cache Line Invalidation A flowchart of the hardware invalidation operation sequence as applied to both caches is shown in FIG. 12 and summarized in FIG.

The instruction cache control hardware (shown in FIGS. 21 and 22) is designed to respond to a single cache management instruction in a processor color. This command is
Referred to as Instruction Cache Line Invalidation (INICL), its purpose is to set the valid bit of the directory to zero for the line identified by the destination address. If an instruction is changed in main memory, the line must be invalidated so that the cache accesses main memory for the updated information. The data cache responds to the data cache number line invalidation (INDCI) cache management command in the same manner. The cache array is not accessed since only the directory is involved in this management command.

The destination address may exist in either cache subset A or B, but not both.
It should be noted that only a single line is identified. Therefore, only one of the two valid bits of the directory entry for the destination address is affected. That is, Va or vb is affected.

Invalidation instructions allow a program to replace a line in the cache with the most recent version from main memory. The LRU bit is forced by the hardware to point to the subset containing the invalidated line, so that the replacement line enters that cache location.

The page address subfield of the object.

It is possible that it does not exist in the directory for either cache subset A or B. This is defined as a cache miss and must be handled by hardware procedures. For either (data or instruction) cache line invalidation instructions,
A miss eliminates the need to change the valid bit; the hardware simply does nothing.

FIG. 8 summarizes the INICL and INDCL hardware operation order.

(j) 7” Data Cache Line Load Data Cache Line Load (I, DCL) A flow diagram of the cache management command can be seen in FIG.
It is summarized in Figure 9. The purpose of this command is simply to
Alternatively, if the in is not already in the cache, load it from main memory into the cache.

(j-1) If the line is already in the cache and valid, no load occurs and the LRtJ pit of the directory is switched to the opposite subset.

(j-2) Miss or Invalid Hit In the case of a miss or an invalid hit, the instruction in question exhibits similar behavior as described above for data cache fetches. A fetch request for the absent line is transferred to main storage. If there is a mistake and the line to be replaced is valid and has been modified, a writeback occurs first. Lines returned from main memory are loaded into the cache, but the data is not bypassed to the CPU. Following the loading of a new 2-in, the valid bit for the stored subset is set to 'on' (ie '0') and the LRU bit is toggled to the opposite subset.

If a new line is loaded due to a miss, the directory is also updated with the new line's page address.

FIG. 9jd summarizes the hardware procedure for loading data cache line number.

←) Set Data Cache Line The Set Data Cache Line (SETDCL) cache management command can be seen in FIG. 17 and summarized in FIG. The purpose of this instruction is to establish a directory entry for the line if it is not already there, not to load the line from main memory into the cache. This can be used to prevent unnecessary retrieval from main memory if the line is to be modified by subsequent storage.

(m-1) If the hit line already exists in the cache, its directory entry is updated by setting the valid bit to "on" and the modified bit to "off."

(m-2) On a miss, if the currently existing line is valid and has been modified, this instruction forces a writeback.

Following a miss (with or without writeback), the directory is updated with the new destination page address, the valid bit is set on, the modified bit is set off, and the LRU bit is toggled to the opposite subset. .

No data transfer occurs unless writeback is required.

Figure 10 shows the data cache line set tab.
This is a summary of the software operation order.

(n) The flowchart of the data cache line storage cache life storage (STDCL) cache management commands can be seen in detail in FIG.
It is summarized in the figure.

The purpose of this instruction is to cause a valid and modified line to be written back so that main memory reflects the original version of the line. As is clear, this storage of a data cache line is not the result of a normal "fetch" or "store" operation.

(n-1) If the hit line is still in the cache, valid, and modified, a writeback occurs and the directory is updated by turning off the modification pit. The line is still kept in cache for future use.

(n-2) If the missed or invalid hit line is not in the cache, or if it is in the cache but is not valid or modified,
The hardware does not perform a writeback and exits the procedure.

Note that this instruction cannot complete in time for the line written back to main memory to be available for the next I/O instruction or instruction cache miss. A special synchronous version of this instruction can be used for this purpose and will be discussed below.

FIG. 11 summarizes the data cat and e-line storage hardware operation sequence.

(,) Store Data Cache Line Synchronization This instruction (STSDCL) operates in the cache exactly like the Store Data Cache Line (STDCL) described above. However, the processor waits until this instruction completes before proceeding to the instruction dream. Therefore, any I/O activity or instruction cache activity that occurs after execution of this instruction will have the latest version of the line available in main memory.

E. CONCLUSIONS In summary, the cache subsystem architecture disclosed herein is unique because it can minimize CPU idle time caused by references to storage. What is novel is that a number of special cache management instructions and some special control pits in the cache directory can be used in unique ways to minimize references to such main memory. It is a point.

These cache management instructions and directory control pits allow software to control the relationship between the contents of the cache subsystem and the contents of main memory.

This ability improves the effective cache hit ratio, thereby allowing the system to avoid unnecessary references to slower main memory.

Moreover, this cache subsystem architecture is novel in that it can improve access times when references to main memory are unavoidable. This ability is unique in that it uses separate caches for instructions and data that can overlap and access main memory independently, speeding up the flow of desired information from main memory to the CPU. This was caused by the use of a cache bypass mechanism for

The ability to allow instruction fetches to proceed independently of data fetches in the storage hierarchy, the prohibition of automatic "store through" from the CPU to main memory, and the special features handled by cache hardware. Coupled with the use of software cache management instructions, system performance is improved by allowing hardware and software functionality to interact harmoniously in novel ways.

[Brief explanation of the drawing]

FIG. 1 is a high-level organizational chart of this hierarchical storage structure. 21 and 22 are functional block diagrams of the storage hierarchy depicted in FIG. 1, showing details of data flow and functional hardware configuration. Figures 51 and 52 are detailed functional block diagrams of data cache addressing showing the basic elements of a cache directory and its associated control elements. Figure 4 shows three different cache sizes (4 to 13
FIG. 3 is a diagram of cache addressing, directory entries, and cache parameters for 16K and 16K). FIG. 5 summarizes the operations that occur in the cache subsystem during operation of the instruction cache retrieval hardware. FIG. 6 summarizes the operations that occur in the cache subsystem during operation of the data cache retrieval hardware. FIG. 7 summarizes the operations that occur in the cache subsystem during operation of the data cache storage hardware. FIG. 8 summarizes the operations that occur in the cache subsystem hardware during an instruction or data cache line invalidation operation. FIG. 9 summarizes the operations performed in the cache subsystem hardware during a data cache line load operation. FIG. 10 summarizes the operations performed in the cache Q subsystem hardware during data cache line set operation. FIG. 11 summarizes the operations that occur in the cache subsystem hardware during data storage cache line storage operation. It is something. FIG. 12 is a detailed flowchart of the operations that take place in the cache subsystem hardware during implementation of the "invalidate cache line" instruction. FIG. 13 is a detailed flowchart of the operations that the cache subsystem also performs in hardware during the execution of the Instruction Cache Fetch instruction. FIG. 14 is a detailed flowchart of the operations that occur in the cache subsystem hardware during the execution of a ``data cache fetch'' instruction. FIG. 15 is a detailed flowchart of the operations that occur in the cache subsystem hardware during the implementation of a ``store data cache'' instruction. Figure 16 shows "data cache line load"
2 is a detailed flowchart of operations performed in cache subsystem hardware during instruction execution; Figure 17 shows [Data cache line set]
2 is a detailed flowchart of operations performed in cache subsystem hardware during instruction execution; FIG. 18 is a detailed flowchart of the operations that take place in the cache subsystem hardware during implementation of a "store data cache line" instruction. Applicant International Business Machines Co., Ltd. Patent Attorney Oka 1)
Next Raw CPU instruction FIG, 3.1 CPU-z″-ta main memory input data FIG, 4 FIG, 8 FIG, l I (CPLI?fi) (CPU drinking ice) (CPIJ! fluent) (CPU key person) ) FIG, I7

Claims (1)

[Claims] (1) In a data processing device including a main memory and a store-in type cache storage device, an instruction cache portion of the cache storage device, a data cache portion of the cache storage device, and a data cache portion of the cache storage device. a cache directory that stores, for each memory location line, the high-order bits of the main memory address of the stored data and control bits indicating the state of said line; and instructions read and modified into said cache for said data. and means for invalidating a line corresponding to the changed instruction in the instruction cache, wherein the instruction cache has a write path only from the main memory. A data processing system equipped with