JPH02197373A - Method for soldering ic chip - Google Patents
Method for soldering ic chipInfo
- Publication number
- JPH02197373A JPH02197373A JP1016793A JP1679389A JPH02197373A JP H02197373 A JPH02197373 A JP H02197373A JP 1016793 A JP1016793 A JP 1016793A JP 1679389 A JP1679389 A JP 1679389A JP H02197373 A JPH02197373 A JP H02197373A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- circuit wiring
- laser light
- laser beam
- wiring part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005476 soldering Methods 0.000 title description 17
- 238000000034 method Methods 0.000 title description 14
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 230000001678 irradiating effect Effects 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 16
- 238000007740 vapor deposition Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000002310 reflectometry Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 238000010521 absorption reaction Methods 0.000 description 7
- 239000011651 chromium Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75261—Laser
- H01L2224/75263—Laser in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
- H01L2224/81224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Laser Beam Processing (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はフレキシブルプリント回路基板にフリップチッ
プ方式によりＩＣチップをレーザはんだ付けする方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of laser soldering an IC chip to a flexible printed circuit board by a flip-chip method.
ＩＣチップをフリップチップ方式によりフレキシブルプ
リント回路基板（以下単に基板と略称する）に実装する
とき、以下のようにして行なうことが知られている。第
４図はそのはんだ付け方法を説明するために必要な部材
を示した模式断面図である。第４図において、図示して
ない熱源を内蔵する温度調整可能な熱板１をはんだの融
点近くの温度とし、その上に基板２を載せ、次にＩＣチ
ップ３を吸引するための吸引孔４を有する図示してない
熱源を内蔵する温度調整可能なコレット５を適度に昇温
し、図示してない真空装置を用いて吸引孔４によりＩＣ
チップ３をコレット５に吸着させながら、基板２上の電
極パターン６にＩＣチップ３のはんだバンプ７を位置決
めした後、所定の荷重で加圧する。このとき熱板１とコ
レット５からはんだ付けに必要な熱が供給されているか
ら、はんだバンプ７が溶融し、ＩＣチップ３と基板２と
のはんだ付けが行なわれる。しかし、この方法は基板２
を載せる熱板１をはんだの融点まで昇温するので、当然
基板２は全体が加熱されることになり、熱容量の低い基
板２は熱変形もしくは熱劣化を生じて、第４図に示すよ
うな電極パターン６が剥離することがあり、またはんだ
付けに必要な個所以外の領域まで加熱されるという点で
基板２に対して好ましくない熱影響を与える。It is known that when an IC chip is mounted on a flexible printed circuit board (hereinafter simply referred to as a board) by a flip-chip method, it is carried out as follows. FIG. 4 is a schematic sectional view showing members necessary for explaining the soldering method. In FIG. 4, a temperature-adjustable heat plate 1 containing a built-in heat source (not shown) is brought to a temperature close to the melting point of solder, a board 2 is placed on it, and then a suction hole 4 is used to suck the IC chip 3. A temperature-adjustable collet 5 having a built-in heat source (not shown) is heated to an appropriate temperature, and the IC is heated through the suction hole 4 using a vacuum device (not shown).
While the chip 3 is being attracted to the collet 5, the solder bumps 7 of the IC chip 3 are positioned on the electrode pattern 6 on the substrate 2, and then pressurized with a predetermined load. At this time, since the heat necessary for soldering is supplied from the hot plate 1 and the collet 5, the solder bumps 7 are melted, and the IC chip 3 and the substrate 2 are soldered. However, this method
Since the temperature of the hot plate 1 on which the solder is placed is raised to the melting point of the solder, the entire board 2 will naturally be heated, and the board 2, which has a low heat capacity, will undergo thermal deformation or thermal deterioration, as shown in Figure 4. This has an undesirable thermal effect on the substrate 2 in that the electrode pattern 6 may peel off, or areas other than those required for soldering may be heated.
そのほかコレット５によってＩＣチップ３を位置決めし
、仮はんだ付けを行なった後、全体をリフロー炉に入れ
て昇温しＩＣチップ３を基板２にはんだ付けする方法も
あるが、これも基板２の熱変形や熱劣化、さらに電極パ
ターン６の剥離などの問題については第４図の場合と同
様であり、しかもはんだ付け工程が増すので好ましくな
い。Another method is to position the IC chip 3 using the collet 5, perform temporary soldering, and then place the whole thing in a reflow oven to raise the temperature and solder the IC chip 3 to the board 2. Problems such as deformation, thermal deterioration, and peeling of the electrode pattern 6 are the same as in the case of FIG. 4, and furthermore, the soldering process is increased, which is not preferable.
以上のように最近は基板２として、低熱容量の例えばポ
リイミド板などが従来のセラミックやガラスに代って用
いられるようになったため、４基板２の熱変形や熱劣化
の問題が起きている。As described above, recently, low heat capacity materials such as polyimide plates have been used as the substrate 2 in place of conventional ceramics and glass, resulting in problems of thermal deformation and thermal deterioration of the four substrates 2.
これに対してレーザ光を照射してＩＣチップを基板には
んだ付けする方法がある。第５図はこの様子を示した部
分的な模式断面図であり、第４図と共通の部分を同一符
号で表わしである。第５図において基板２の電極パター
ン６にＩＣチップ３のはんだバンプ７を位置決めした後
、矢印で示したレーザ光８をＩＣチップ３の裏面すなわ
ち回路配線部９とは反対の面から照射する。この方法は
前述のように熱板１を用いることなく、レーザ光８によ
る局所的な加熱であるから、基板２の熱変形や熱劣化の
問題が置きないという点では第４図の場合より勝ってい
る。On the other hand, there is a method of soldering the IC chip to the substrate by irradiating the IC chip with laser light. FIG. 5 is a partial schematic cross-sectional view showing this state, and parts common to those in FIG. 4 are indicated by the same reference numerals. In FIG. 5, after the solder bumps 7 of the IC chip 3 are positioned on the electrode pattern 6 of the substrate 2, a laser beam 8 indicated by an arrow is irradiated from the back surface of the IC chip 3, that is, the surface opposite to the circuit wiring section 9. As mentioned above, this method uses local heating using the laser beam 8 without using the hot plate 1, so it is superior to the case shown in FIG. 4 in that there is no problem of thermal deformation or thermal deterioration of the substrate 2. ing.
しかしながら、レーザ光を照射して行なうはんだ付け方
法にもなお問題が残されている。それは第５図のように
レーザ光８を照射してはんだ付けを行なうとき、ＩＣチ
ップ３の回路配線部９の密度が高く、はんだバンプ７の
密度が低い場合に、ＩＣチップ３内を透過するレーザ光
８の吸収率が回路配線部９において急激に増大すること
である。However, problems still remain with the soldering method using laser light irradiation. As shown in FIG. 5, when soldering is performed by irradiating a laser beam 8, when the density of the circuit wiring part 9 of the IC chip 3 is high and the density of the solder bumps 7 is low, the laser beam 8 passes through the inside of the IC chip 3. This is because the absorption rate of the laser beam 8 increases rapidly in the circuit wiring portion 9.
第６図はレーザ光８の照射方向からみて回路配線部９を
含むＩＣチップ３の全厚ｔとレーザ光８の吸収率との関
係を表わす線図である。第６図のようにＩＣチップ３内
を透過したレーザ光８はＩＣチップ３のみの厚さｔ、ま
でに４０〜５０％が吸収され、抵抗や金属膜などからな
る回路配線部９の厚さｔ１〜ｔでレーザ光８の吸収は急
激に増加する。そのため、回路配線部９の方がその近傍
のＩＣチップ母材より温度上昇が大きく、両者の間に著
しい温度差が生ずる。FIG. 6 is a diagram showing the relationship between the total thickness t of the IC chip 3 including the circuit wiring portion 9 and the absorption rate of the laser beam 8 when viewed from the irradiation direction of the laser beam 8. As shown in FIG. As shown in FIG. 6, 40 to 50% of the laser beam 8 transmitted through the IC chip 3 is absorbed by the thickness t of the IC chip 3 alone, and the thickness of the circuit wiring part 9 made of resistors, metal films, etc. Absorption of the laser beam 8 increases rapidly from t1 to t. Therefore, the temperature rise in the circuit wiring portion 9 is greater than that of the IC chip base material in the vicinity, and a significant temperature difference occurs between the two.
第７図ははんだ付け後の模式断面図であり、ＩＣチップ
３と回路配線部９との温度差による熱応力が発生して回
路配線部９は、第７図の一部を拡大して示した第８１！
Ｉのように遂には破損に至る。FIG. 7 is a schematic cross-sectional view after soldering, in which thermal stress is generated due to the temperature difference between the IC chip 3 and the circuit wiring section 9. The 81st!
As in I, it will eventually lead to damage.
本発明は上述の点に鑑みてなされたものであり、その目
的はレーザ光を照射してＩＣチップを基板に実装すると
き、ＩＣチップとその回路配線部との境界において大き
な温度差を生じることがなく、回路配線部を破損するこ
とがないはんだ付け方法を提供することにある。The present invention has been made in view of the above-mentioned points, and its purpose is to prevent a large temperature difference from occurring at the boundary between the IC chip and its circuit wiring when mounting the IC chip on a substrate by irradiating a laser beam. It is an object of the present invention to provide a soldering method that does not cause damage to circuit wiring parts.
上記課題を解決するために、本発明の方法はＩＣチップ
を基板に実装する際に、あらかじめＩＣチップの裏面に
、レーザ光の照射による回路配線部の温度勾配を緩やか
にする金属膜を形成しておくものである。In order to solve the above problems, the method of the present invention includes forming a metal film on the back surface of the IC chip in advance to soften the temperature gradient of the circuit wiring part caused by laser beam irradiation when mounting the IC chip on the substrate. It is something to keep.
本発明ではＩＣチップの裏面に、レーザ光に対して適当
な反射率をもつＯｒなどの金属膜をあらかじめ蒸着やス
パッタなどで形成しておいたために、このＩＣチップを
基板に位置決めした後レーザ光を照射すると、レーザ光
のほぼ６０％はこの金属膜に吸収され、残りが熱変換さ
れてＩＣチップの裏面から表面の回路配線部に至るまで
の厚さ方向に比較的緩やかな勾配をもって温度上昇する
のでＩＣチップと回路配線部との境界における急激な温
度差を生ずることな（、−様な温度ではんだバンプを溶
融させ基板上の電極パターンとのはんだ付けを行なうこ
とができる。In the present invention, since a metal film such as Or, which has an appropriate reflectance to the laser beam, is formed on the back surface of the IC chip by vapor deposition or sputtering, after the IC chip is positioned on the substrate, the laser beam is applied to the back surface of the IC chip. When irradiated with , approximately 60% of the laser light is absorbed by this metal film, and the rest is converted into heat, causing the temperature to rise with a relatively gentle gradient in the thickness direction from the back side of the IC chip to the circuit wiring section on the front side. Therefore, the solder bumps can be melted and soldered to the electrode patterns on the substrate at temperatures as low as 1 to 30 degrees without causing a sudden temperature difference at the boundary between the IC chip and the circuit wiring section.
以下本発明を実施例に基づき説明する。 The present invention will be explained below based on examples.
第１図は本発明によるはんだ付けの状態を第５図に做っ
て示した模式断面図である。第１図が第５図と異なる所
は第１図ではＩＣチップ３の裏面に、あらかじめ金属膜
１０を蒸着もしくはスバッタなどにより形成しであるこ
とであり、その他は第５図と同じであるから説明を省略
する。この金属膜１０はレーザ光８に対して適当な反射
率をもっていることが必要である。第２図は各種金属に
照射した光の波長と反射率との関係を示した線図である
。これらの金属のうち、比較的反射率の低い方の例えば
Ｃｒ （クロム）を用いて、金属膜１０を４〜５−程度
の厚さに裏面に形成したＩＣチップ３を基板２の電極パ
ターン６上に位置決めした後、例えばＹＡＧレーザ光（
波長１．０６ｎ）８を金属膜１０側から照射すると、レ
ーザ光８は照射面のＣｒ金属膜１０において約６２％が
反射し、残りの約３８％はここで熱変換されて、その熱
がＩＣＣチップ全体の温度上昇をもたらすことになる。FIG. 1 is a schematic cross-sectional view showing the state of soldering according to the present invention, compared to FIG. 5. The difference between FIG. 1 and FIG. 5 is that in FIG. 1, a metal film 10 is formed in advance on the back surface of the IC chip 3 by vapor deposition or spatter, and other aspects are the same as in FIG. 5. The explanation will be omitted. This metal film 10 needs to have an appropriate reflectance for the laser beam 8. FIG. 2 is a diagram showing the relationship between the wavelength of light irradiated onto various metals and the reflectance. Among these metals, for example, Cr (chromium), which has a relatively low reflectance, is used to form an IC chip 3 on the back surface of which a metal film 10 is formed to a thickness of approximately 4 to 5 mm. After positioning above, e.g. YAG laser beam (
When a wavelength of 1.06n) 8 is irradiated from the metal film 10 side, approximately 62% of the laser beam 8 is reflected by the Cr metal film 10 on the irradiated surface, and the remaining approximately 38% is converted into heat. This results in an increase in the temperature of the entire ICC chip.
その様子を第６図と比較するために第６図に做って金属
膜１０を備えたＩＣチップ３の全厚１Ｓとレーザ光８の
吸収率との関係線図を第３図に示した。第３図ではチッ
プ裏面からの厚さ方向に対してレーザ光８は金属膜１０
の厚さｔ、まで吸収率は急速に立ち上がるが、ＩＣチッ
プ３内では緩やかな傾斜となり、とくに回路配線部９に
相当するｔ、〜ｔ、の領域で吸収率の勾配が第６図のよ
うに急峻になることがない。そのため、ＩＣチップ全体
が一様に温度上昇し、ＩＣチップ３と回路配線部９との
間に大きな温度差は生じない。したがってＩＣチップ３
と基板２のはんだ付けを行なうに当たって、熱的応力の
発生に起因する回路配線部９の破損を招くことはないの
である。In order to compare the situation with FIG. 6, a relationship diagram between the total thickness 1S of the IC chip 3 provided with the metal film 10 and the absorption rate of the laser beam 8 is shown in FIG. . In FIG. 3, the laser beam 8 is directed toward the metal film 10 in the thickness direction from the back surface of the chip.
The absorption rate rises rapidly up to the thickness t, but has a gentle slope within the IC chip 3, and especially in the region t, ~t, corresponding to the circuit wiring portion 9, the absorption rate slopes as shown in FIG. It never becomes steep. Therefore, the temperature of the entire IC chip rises uniformly, and no large temperature difference occurs between the IC chip 3 and the circuit wiring section 9. Therefore, IC chip 3
When soldering the substrate 2 to the substrate 2, the circuit wiring portion 9 is not damaged due to thermal stress.
従来、裏面からレーザ光を照射してＩＣチップをフレキ
シブルプリント回路基板にはんだ付けするとき、ＩＣチ
ップ表面の回路配線部でレーザ光の吸収率が大きく、Ｉ
Ｃチップ母材との著しい温度差を生じ、そこに発生する
熱応力によって回路配線部が破損していたのに対し、本
発明では実施例で述べたごとく、レーザ光に対して適当
な反射率を有する例えばＣｒなどの金属膜をＩＣチップ
裏面に数μ被着し、この面からレーザ光を照射して、こ
のＩＣチップのはんだ付けを行なうようにしたため、レ
ーザ光の一部は金属膜で反射され、ここで吸収されて熱
変換されたレーザ光によるＩＣチップ内の温度上昇は一
様に緩やかになり、ＩＣチップ表面と回路配線部との界
面における温度差およびこの温度差に起因する熱応力の
発生を抑制し、密度の高い回路配線部の破損をなくすこ
とができる。Conventionally, when soldering an IC chip to a flexible printed circuit board by irradiating a laser beam from the back side, the absorption rate of the laser beam is large in the circuit wiring section on the front surface of the IC chip, and the I
A significant temperature difference with the base material of the C chip was generated, and the circuit wiring part was damaged due to the thermal stress generated there.In contrast, in the present invention, as described in the embodiment, the circuit wiring part has an appropriate reflectance for laser light. A few micrometers of a metal film, such as Cr, having a The temperature rise inside the IC chip due to the laser light that is reflected, absorbed, and converted into heat becomes uniformly gradual, and the temperature difference at the interface between the IC chip surface and the circuit wiring part and the heat caused by this temperature difference occur. It is possible to suppress the generation of stress and eliminate damage to high-density circuit wiring parts.
第１図は本発明におけるはんだ付け状態を示す模式断面
図、第２図は各種金属に対する光の波長と反射率との関
係を示した線図、第３図は本発明におけるチップの厚さ
とレーザ光の吸収率との関係を示した線図、第４図は従
来方法を説明するためのＩＣチップ周辺の部材を示した
模式断面図、第５図は同じくレーザ光照射による方法を
示した模式断面図、第６図は第５図におけるチップの厚
さとレーザ光の吸収率との関係を示した線図、第７図は
第５図のはんだ付け後の模式断面図、第８図は第７図の
一部拡大図である。
２：フレキシブルプリント回路基板、３：ＩＣチップ、
６：電極パターン、７：はんだバンブ、８：レーザ光、
９：回路配線部、１０：金属膜。
第４図
第５図
第６図
第７図
第８図Fig. 1 is a schematic cross-sectional view showing the soldering state in the present invention, Fig. 2 is a diagram showing the relationship between the wavelength of light and reflectance for various metals, and Fig. 3 is a diagram showing the relationship between the chip thickness and the laser beam in the present invention. A line diagram showing the relationship with light absorption rate, Fig. 4 is a schematic cross-sectional view showing parts around the IC chip to explain the conventional method, and Fig. 5 is a schematic diagram showing the method using laser light irradiation. 6 is a diagram showing the relationship between the chip thickness and laser light absorption rate in FIG. 5, FIG. 7 is a schematic sectional view after soldering in FIG. 5, and FIG. This is a partially enlarged view of FIG. 7. 2: Flexible printed circuit board, 3: IC chip,
6: Electrode pattern, 7: Solder bump, 8: Laser light,
9: circuit wiring part, 10: metal film. Figure 4 Figure 5 Figure 6 Figure 7 Figure 8
Claims (1)
プの前記はんだバンプをフレキシブルプリント回路基板
の所定個所に位置決めし、前記ＩＣチップの裏面からレ
ーザ光を照射することにより前記はんだバンプを溶融さ
せ、前記ＩＣチップを前記フレキシブルプリント回路基
板にはんだ付けするに際し、あらかじめ前記ＩＣチップ
の裏面に、前記レーザ光の照射による前記回路配線部の
温度勾配を緩やかにする金属膜を形成したことを特徴と
するＩＣチップのはんだ付け方法。1) Positioning the solder bumps of an IC chip having a circuit wiring section and solder bumps on the front surface at a predetermined location on a flexible printed circuit board, and melting the solder bumps by irradiating a laser beam from the back surface of the IC chip. , characterized in that, when the IC chip is soldered to the flexible printed circuit board, a metal film is formed in advance on the back surface of the IC chip to soften the temperature gradient of the circuit wiring portion caused by irradiation with the laser beam. How to solder IC chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1016793A JPH0671135B2 (en) | 1989-01-26 | 1989-01-26 | IC chip soldering method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1016793A JPH0671135B2 (en) | 1989-01-26 | 1989-01-26 | IC chip soldering method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02197373A true JPH02197373A (en) | 1990-08-03 |
| JPH0671135B2 JPH0671135B2 (en) | 1994-09-07 |
Family
ID=11926052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1016793A Expired - Fee Related JPH0671135B2 (en) | 1989-01-26 | 1989-01-26 | IC chip soldering method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671135B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02249247A (en) * | 1989-03-23 | 1990-10-05 | Casio Comput Co Ltd | Bonding of integrated circuit chip |
| US5481082A (en) * | 1993-07-19 | 1996-01-02 | Mitsubishi Denki Kabushiki Kaisha | Apparatus and method for die bonding semiconductor element |
| JP2006147880A (en) * | 2004-11-19 | 2006-06-08 | Citizen Miyota Co Ltd | Method and device for bonding semiconductor with solder bump |
| JP2009070906A (en) * | 2007-09-11 | 2009-04-02 | Shibuya Kogyo Co Ltd | Bonding machine |
| JP2009516378A (en) * | 2005-11-18 | 2009-04-16 | パック テック−パッケージング テクノロジーズ ゲーエムベーハー | Method for forming a contact structure between a microelectronic component and a carrier substrate, and an assembly unit formed by this method |
| JP2010010196A (en) * | 2008-06-24 | 2010-01-14 | I-Pulse Co Ltd | Laser reflow method and equipment |
| TWI403378B (en) * | 2007-09-11 | 2013-08-01 | Shibuya Kogyo Co Ltd | Bonding device |
| US20170141071A1 (en) * | 2015-11-17 | 2017-05-18 | Electronics And Telecommunications Research Institute | Method of fabricating a semiconductor package |
-
1989
- 1989-01-26 JP JP1016793A patent/JPH0671135B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02249247A (en) * | 1989-03-23 | 1990-10-05 | Casio Comput Co Ltd | Bonding of integrated circuit chip |
| US5481082A (en) * | 1993-07-19 | 1996-01-02 | Mitsubishi Denki Kabushiki Kaisha | Apparatus and method for die bonding semiconductor element |
| JP2006147880A (en) * | 2004-11-19 | 2006-06-08 | Citizen Miyota Co Ltd | Method and device for bonding semiconductor with solder bump |
| JP2009516378A (en) * | 2005-11-18 | 2009-04-16 | パック テック−パッケージング テクノロジーズ ゲーエムベーハー | Method for forming a contact structure between a microelectronic component and a carrier substrate, and an assembly unit formed by this method |
| JP2009070906A (en) * | 2007-09-11 | 2009-04-02 | Shibuya Kogyo Co Ltd | Bonding machine |
| TWI403378B (en) * | 2007-09-11 | 2013-08-01 | Shibuya Kogyo Co Ltd | Bonding device |
| JP2010010196A (en) * | 2008-06-24 | 2010-01-14 | I-Pulse Co Ltd | Laser reflow method and equipment |
| US20170141071A1 (en) * | 2015-11-17 | 2017-05-18 | Electronics And Telecommunications Research Institute | Method of fabricating a semiconductor package |
| US9853010B2 (en) * | 2015-11-17 | 2017-12-26 | Electgronics And Telecommunications Research Institute | Method of fabricating a semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0671135B2 (en) | 1994-09-07 |
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