JPH02197172A - High breakdown strength mosfet - Google Patents

Abstract

PURPOSE:To restrain a leakage current by a method wherein an island like first region and a second region surrounding the first region isolated from it are provided, where a second region cutout section which makes the second region an open loop is provided adjacent to both the side edges of a lead-out wiring of an intersection part of the second region with the lead-out wiring respectively. CONSTITUTION:A MOSFET of high breakdown strength composed of the following is provided: an island-like drain region 4; a conductive circular source region 16 which surrounds the region 4 being isolated from it; a poly-Si gate 8 provided adjacent to and along the region 16 between the region 4 and the region 16; and a drain lead-out wiring 14 which is connected to the region 4 and provided extending from it in a radial direction on a plane. For instance, overhang cutout sections 18b and 18c which make the region 16 an open loop are provided adjacent to, at least, both the side edges 14b and 14e of the lead-out wiring 14 of an intersection part 14a of the region 16 with the lead-out wiring 14. By this setup, an inverted layer is induced just under the intersection part 14a, but as the cutout sections 14b end 14e have been provided, the inverted layer induced is not linked to the open loop region 16 and a local channel is prevented from occurring and consequently a leakage current can be restrained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a high voltage MOS FET, and particularly relates to a high voltage MOS FET that includes a drain lead wiring extending from an island-shaped drain region in a planar radial direction and a loop-shaped source region. The present invention relates to a horizontal high-voltage MOSFET having the following characteristics.

[Conventional technology]

Conventionally, the structure of a horizontal high-voltage MOSFET used in intelligent switching devices, etc., has an N-type epitaxial layer 2 epitaxially grown on a P-type substrate 1, as shown in FIGS. P
An annular P-type isolation region 3 defined by N junction isolation and an island-shaped N+ region formed within the epitaxial layer 2
type drain region 4, an annular P-type body (channel diffusion) region 5 surrounding this drain region 4 and formed along the isolation region 3, and an annular N+-type body (channel diffusion) region 5 formed within the body region 5. A source region 6, an annular drain drift region 2a defined between the drain region 4 and the body region 5, and the drain drift region 2a.
an annular polysilicon gate (lx) extending over the gate oxide film 7 and the source region 6, a drain electrode 9 on the drain region 4, and a drain polysilicon portion 10 connected to the polysilicon gate 8 and the drain electrode 9; an annular polysilicon high specific resistance film 11 whose inner and outer peripheral edges are connected between;
A source electrode 12 connected to the source region 6, a drain lead wire 14 connected to the drain electrode 9 on the interlayer insulating film 13 and extended in the radial direction from the drain electrode 9, an annular isolation region 3, and a drain lead wire 14. A shield region 15 is provided between the two at the intersection of the two.

Polysilicon high resistivity film 11 is drain drift region 2
The shield region 15 is a resistive field plate that makes the electric field of a uniform, and prevents the formation of an inversion layer on the surface of the isolation region 3 due to the potential of the drain lead wiring 14.
It maintains PN junction isolation. In addition, the polysilicon high resistivity film 11 suppresses the expansion of the depletion layer by forming an accumulation layer on the surface of the drain drift region 2a due to the potential of the drain lead wiring 14, and prevents the avalanche voltage from decreasing. It also has a function of shielding the potential of the lead wiring 14.

As described above, in the conventional high voltage MOSFET, the presence of the polysilicon high resistivity film 11 and the shield region 15 shields and protects the surface layer portions of the drain drift region 2a and the isolation region 3 from the potential of the drain lead wiring 14. Because of this, it is possible to maintain a high withstand voltage.

[Problem to be solved by the invention]

However, in the conventional high voltage MOSFET described above, when the potential of the drain lead wiring 14 becomes a high potential,
Drain lead wiring 14 and annular polynolyric gate 8
An inversion layer is formed at the intersection, and a narrow channel C is formed between the source region 6 and drain drift region 2a at the intersection, resulting in an increase in leakage current. That is, a parasitic capacitance is inevitably generated at the intersection of the drain lead wiring j4 and the polysilicon gate 8 with the interlayer insulating film 13 interposed, and this parasitic capacitance is connected in series to each local gate term. Therefore, the drain lead wiring 14
This is not a problem when the potential is relatively low, but when it becomes high, the local gate capacitance is charged and an inversion layer is formed directly under the polysilicon gate 8 at the intersection.

In order to shield the polysilicon gate 8 at the intersection from the potential of the drain lead wiring 14, it is conceivable to newly interpose a shield region similar to the shield region 15 at the intersection. Since the parasitic capacitances are simply connected in series, when the potential of the drain lead wiring 14 becomes high, an inversion layer is generated directly under the polysilicon gate 8, and a channel C is formed.

Therefore, an object of the present invention is to provide a structure that prevents the formation of a channel even if an inversion layer is generated directly under the gate at the intersection due to the influence of the potential of the drain lead-out wiring, thereby suppressing an increase in leakage current. The objective is to provide a high voltage MOSFET.

[Means to solve the problem]

In order to solve the above-mentioned problems, the means taken by the present invention is to provide an island-shaped first region (for example, the drain region 4) and an annular second region of the same conductivity type (for example, the source region ), a gate (for example, a polysilicon gate 8) adjacent along the second region between the first region and the second region;
A high-voltage MO5FET including a lead wire (for example, a drain lead wire 14) connected to the first region and extending in a radial direction on the plane from the first region, and at least the lead wire at the intersection of the second region and the lead wire. Next to both side edges of the wiring, second region cutout portions (for example, overhang cutout portions 1.4b and 14c) are provided to make the second region into an open loop shape.

[Effect]

According to this means, an inversion layer is induced directly under the intersection by the potential of the extraction wiring, but a second layer to be wiped in an open loop is formed in the second region adjacent to at least both side edges of the extraction wiring in the intersection. Since the region cut-out portion is provided, the inversion layer induced at the intersection does not reach the open-loop second region, and no local channel is generated. For this reason,
Leakage current can be suppressed.

〔Example〕

Next, embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1 (A> is a sectional view showing an embodiment of a high voltage MOSFET according to the present invention, and FIG. 1 CB) is a plan view of the same embodiment. Note that in FIGS. 1(A) and ([3), the same parts as those in FIGS. 2(A) and (B) are given the same reference numerals, and their explanations are omitted.

In the figure, an island-shaped drain electrode 9 is formed on an island-shaped N+ type drain region 4 formed at the center of the substrate plane. An annular P-type body region 5 is formed inside the annular isolation region 3 surrounding the N++ drain region 9, and an open-loop source region 16 is formed within this body region 5. Further, a ring-shaped polysilicon gate 8 is adjacent to the open-loop source region 16 . Drain lead wiring 1 is connected to drain electrode 9.
4 is connected to the source region 16, which is the source defect 1 of the source region 16.
8 and extends in the radial direction on the plane.

The source missing portion 18 is provided as a source impurity-free region at the intersection of the source region 16 and the drain lead wire 14, and is located at the intersection 14a of the drain lead wire I4.
It consists of a crossing cutout 18a directly below and narrow overhang cutouts 18b and 18C adjacent to both side edges 14b and 14c of the drain lead wiring 14.

When a high potential is applied to the drain lead wiring 14, an inversion layer (N-type layer) is generated directly under the polysilicon gate 8 at the intersection or, in some cases, also in the intersection cutout 18a. However, no inversion layer is generated in the overhanging cutout portions 18b and 18G, and the P-type remains. That is, the overhanging missing portion 18b
, 18c are not affected by the potential of the drain lead wire 14 and serve as non-inversion layers, so no channel is formed at the intersection. Although it depends on the thickness of the interlayer insulating film 13, since the intersection cutout 18a exists and the P-type body region 5 is directly under the intersection 14a of the drain lead-out wiring 14, as described above, this surface layer An inversion layer may also occur. Therefore, the overhanging cutout portion 18b
, 13c are essential, but there is no intersection cutout 18a, and the area directly below the intersection 14a may be used as a source impurity doped region. It is also possible to form an open loop with a part of the polysilicon gate 8 removed at the intersection, but the drain lead wiring 14
In some cases, an inversion layer is formed under the partially removed gate portion due to the high potential of , and the importance of the partially removed portion is not so great.

In this way, since the source deletion portion 18 is actively provided at the intersection, even if a local inversion layer occurs, it will not communicate with the source region 16, so the intersection will not be affected. No channel is formed, and leakage current can be suppressed.

[Effects of the Invention] As explained above, the high voltage MO5FET according to the present invention
is at least an arched portion of the intersection between the annular second region of the same conductivity type that circles around the island-like first region and the lead-out wiring connected to the first region and extending in a radial direction on a plane. Since the second region has a second region cutout portion next to both edges of the wiring, which should be an open loop, even if an inversion layer is formed directly under the lead wire at the intersection, it will not be possible to form the channel before the channel is formed. Therefore, it is possible to eliminate the adverse effects caused by the potential of the lead wiring, such as an increase in leakage current.

[Brief explanation of the drawing]

FIG. 1(A) is a sectional view showing an embodiment of a high voltage MOSFET according to the present invention, and FIG. 1(B) is a plan view of the same embodiment. FIG. 2(Δ) is a sectional view showing an example of a conventional high voltage MOSFET, and FIG. 2(B) is a plan view of the conventional example. IP type semiconductor substrate, 2N-type epitaxial layer, 3
P-type iso-rayon region, 4N. type island-shaped drain region, 5 P type body region, 7 gate oxide film, 8 polysilicon gate, 9 drain electrode, I
O drain polysilicon part, 11 polysilicon high resistivity film, 12 source electrode, 13 interlayer insulating film, 14 drain lead wiring, 1.4a intersection, +4b, 14
c Side edge, 16 Open-loop N" type source region, 1
8 Source deletion part, 18a Cross deletion part, 18b,
18C overhang missing part. ] Figure Figure

Claims (1)

[Claims] 1) An island-shaped first region, an annular second region of the same conductivity type that surrounds the first region in isolation, and a gate adjacent along the second region between the first region and the second region; A high-voltage MOSFET including an extraction wiring connected to a region and extended in a radial direction on a plane from the second region, and of the intersection between the second region and the extraction wiring, at least adjacent to both side edges of the extraction wiring. A high voltage MOSFET characterized by comprising a second region cutout portion in which the second region is to be in an open loop shape.