JPH0219631B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to electrically rewritable read-only memories, and more particularly to improved electrically rewritable read-only memories of the metal nitride oxide semiconductor (MNOS) format. Regarding memory.

Electrically rewritable read-only memory (EAROM) is used as a programmable nonvolatile semiconductor memory device. Such memory devices in the form of individual memory cells consisting of metal nitride oxide semiconductor (MNOS) structures are formed by a source region, a drain region and an interface of an insulating material such as silicon dioxide and silicon nitride. It has a memory gate area. EAROM devices can be fabricated as integrated circuit (IC) chip components in predetermined patterns or arrays at high density and at relatively low cost.

The IC also includes a logic circuit, an address circuit, and a decode circuit for selecting a group of cells;
Each group is generally considered to constitute a word or select an individual cell.
EAROM requires low power and is relatively easy to erase and write by applying appropriate voltages to the gate electrodes of the memory cells. It has found wide utility in a variety of applications, such as radio and television tuners, program storage circuits, etc.

In this type of EAROM device, each cell is isolated from its neighbors so that any cell can be selected and read, written or erased without affecting other cells. This separation is
This is often provided by using channel stops between adjacent groups of cells. A channel stop is a region on a semiconductor device substrate between adjacent cells that has a large threshold voltage to prevent undesirable relationships between unrelated source-drain diffusions. have
This can be done by covering the highly doped substrate region between two unrelated source-drain diffusion regions with a thick insulating material. For example, in an N-channel device, the channel stop has thick field insulation.
P ⁺ format material. However, even techniques such as channel stopping require isolation in memory devices where adjacent memory cells (bits) must also be shielded from write operations performed on one of the adjacent bits. It will not completely solve the problem.

In EAROM devices, the channel shield is
It is defined as the ability to selectively write to some of the desired memory cells from an erased state without affecting other erased cells. In other words, the ability to write protect erased bits while other adjacent bits are being written. Good channel shielding is necessary and desirable in large, high density memory structures.
It is desirable to maintain good channel shielding for as many erase-write cycles as possible, as this increases device utilization.

In channel shield mode, the conductive path (channel) between the source and drain of an unselected erased bit (which must be channel shielded from neighboring bits) is approximately +
25V) is precharged to the write voltage. The gate (word line) is also raised to this write voltage and the substrate is at ground voltage. Thus, the source, drain and gate are at the same potential and the source and drain junctions are reverse biased. The gate electrode current that would otherwise be used to write this particular bit is now substantially shunted due to the reverse biased source and drain. This particular bit will not be written except by residual gate-to-substrate current. The smaller the amount of this residual gate current, the better the channel shielding becomes. Erase-
As write operations are repeated, the effects of this residual current accumulate and result in the bit losing its original erased state. Therefore, erasure-
The time and number of writes affect the channel shield. It is desirable to reduce the residual gate current in channel shield mode, and thus increase the number of erase-write cycles during which the channel shield is active.

This invention relates to EAROMs, and more particularly to improved EAROMs of the metal nitride oxide semiconductor (MNOS) type. EAROM has an improved channel shield while having the ability to be switched through a greater number of erase-write cycles than conventional EAROM devices.

According to the invention, in order to reduce the inherent tendency of memory cells adjacent to it to change from an erased state to a programmed state while a memory cell is being programmed, a channel shield is used. To increase the memory gate field, the memory gate field is reduced by appropriately forming an implant structure under the memory gate channel. Such a formation is such as to provide a substantially lower surface doping concentration to reduce the gate field while keeping the threshold voltage of the cell substantially constant. This is achieved according to a preferred embodiment of the invention by dual implantation of various impurity materials within the memory gate channel. First, a suitable material, such as boron, is implanted in N-channel type devices to establish the gate threshold voltage, ie, the voltage at which the device switches from one state to another. Then, for example, N-
For channel devices there is a second implant of an impurity material of the opposite conductivity type, such as phosphorous. this is,
It reduces the surface concentration created by the original impurity material and also reduces the field under the gate without substantially changing the threshold voltage. By reducing the field, we reduce the ability of charge to move within the gate dielectric,
This increases channel shielding and thus reduces gate-to-substrate current, which is the main cause of poor channel shielding.

Therefore, the main object of this invention is to have an improved channel shield in which the implant profile under the memory gate is double implanted with a suitable impurity material to match the implant profile.
Our goal is to provide EAROM.

Another object is to provide an EAROM in which the implant distribution under the memory gate is adapted to reduce the field of the gate.

Yet another object is to provide an EAROM with an improved channel shield in which the implant profile under the memory gate is double implanted with a suitable impurity material to match the implant profile.

Another object is to provide an improved N-channel EAROM in which the structure beneath the memory gate is double implanted with boron and phosphorus.

These and other objects of the invention will become more apparent with reference to the following description and attached drawings.

Referring to FIG. 1, a typical complete EAROM split gate memory cell 1 according to the present invention
A cross-sectional view of 0 is shown. This cell is greatly enlarged and not accurately drawn. Just 1
memory cells are described. There are large numbers of such cells, usually arranged in groups or words, and together with various other semiconductor circuits for logic, decoding and addressing, formed simultaneously, as is conventional in the semiconductor manufacturing industry. It should be understood that These are not shown as they do not form part of this invention.

P-MNOS devices can also be made, but
The EAROM cell 10 is exemplified as an N-MNOS type cell. EAROM cell 10 includes a substrate 12 of a suitable material, such as silicon, suitably doped with an N-type impurity, such as arsenic. Substrate 12 is
Provides support for an epitaxial layer 14 grown thereon and containing P-type impurity material, such as boron. The amount of impurity in the layer 14 is, for example, from approximately 1×10 ¹⁵ atoms/cm ³ to approximately 1×
It can be on the order of 10 ¹⁶ atoms/cm ³ . This cell is
Isolation diffusions 1 on each side diffused into the substrate through the epitaxial layer 14
separated by 6. This isolation diffusion portion is an N-type impurity region.

A pair of junction regions 20, 22 are formed by diffusion in the epitaxial layer 14 of the substrate and form the source and drain. Both junction regions 20 and 22 are doped with N-type impurities. Methods of forming diffusion regions 20, 22 are well known in the art, and any conventional method may be used, such as ion implantation. The source and drain diffusion channels are
The implanted arsenic/phosphorus has an impurity level on the order of about 10 ¹⁹ atoms/cm ³ to about 10 ²¹ atoms/cm ³ .

A region of thick insulating material 26, called field oxide and for example silicon dioxide several thousand angstroms thick, is located at the outer edge of each diffusion region 20, 22 on the top surface of epitaxial layer 14 of the substrate. Formed at the edges. This separates one memory cell from the next and forms a channel stop region. An opening is provided through the field oxide layer 26 for each electrode 50 and 52 to make electrical contact with the source and drain 20,22. Electrodes 50, 52 may be constructed of any suitable material, such as aluminum.

The memory gate region 30 of the cell is located between two vertical barriers 29 of field oxide layer 26 . Region 30 is a split gate region 3 of an insulating material, such as silicon dioxide, several hundred angstroms thick, called gate oxide.
2 on each side thereof. Between the two split gate oxide regions 32 is a tunnel region 34 over which is disposed a tunnel gate layer 36 of an insulating material such as silicon dioxide (SiO ₂ ). The relative thickness of non-tunnel split gate 32 and tunnel layer 36 is:
For example, the former ranges from about 400 Å to about 600 Å;
The latter ranges from about 10 Å to about 40 Å. These thicknesses control the switching characteristics of the device and the retention characteristics of the memory.

A layer 40 of an insulating material, such as silicon nitride (Si ₃ N ₄ ), connects the source and drain electrodes 50,
52 and on top of field oxide layer 26 and in memory cell region 30 and above split gate region 32 and tunnel region 34. The nitride layer has a thickness ranging from about 300 Å to about 600 Å. Due to the crystal structure of SiO ₂ and Si ₃ O ₄ , a charge storage region is formed at the interface 46 of tunnel gate region layer 36 and nitride layer 40 . A charge storage region also extends a distance into the nitride layer 40. To complete this structure, a gate electrode 54, made of aluminum, is placed on top of the nitride layer 40 in the memory cell area.

Impurity materials of opposite conductivity type are implanted into the epitaxial layer 14 in the gate region between the source and drain channels 20,22. These are, for example, boron as the first material and phosphorus or arsenic as the second material in an N-channel device. Boron implant dose and energy control the threshold voltage of the N-channel device, while phosphorus or arsenic implants are used to improve the channel shield. Double injection of impurities is
Reduces the field in the gate region and thereby improves channel shielding. This will be explained below.

In the overall operation of the EAROM of FIG. 1, consider that the drain and source are at ground potential. If a voltage of the appropriate amount and polarity is applied to the gate electrode 54, a charge of opposite polarity will
It will be drawn from the epitaxial layer of the substrate. For example, a negative voltage applied to gate electrode 54 causes positive charge carriers (holes) to tunnel from substrate 14 through silicon dioxide tunnel layer 36 and into the nitride layer at interface 46 and into the nitride layer. captured at a distance of Because silicon dioxide-silicon nitride is an extremely large insulator, charge remains trapped for extremely long periods of time. N channel EAROM
is written to a low conduction state (or turned off) by applying a positive voltage of, for example, +25 volts to gate electrode 54. This effectively causes negative charge to accumulate at the silicon dioxide-silicon nitride interface. This negative charge moves the device's threshold to a more positive level. In this write state, the EAROM operates in enhancement mode, ie, a positive charge must be applied to the gate to establish a conduction channel between source and drain. N channel's
A typical write state threshold for EAROM is approximately 6 volts.

The device is erased to a low threshold or high conduction state by applying a negative voltage (such as -25 volts) to gate electrode 54. This negative voltage draws positive charges (holes) to the interface 46, which in turn establishes a conduction channel under the memory gate 36. In the erased state, the area under the memory gate 36 operates in depletion mode, thus the two non-memory areas 32 acting as enhancement devices are connected in series.

The erased state threshold is therefore determined by the thickness of the gate in the non-memory region of the memory cell. The erased state threshold voltage is on the order of 1.5 volts. A fairly large difference, or window, between the write and erase threshold voltages allows reliable data decoding.

Controlling the threshold voltage V _T at which the device switches from one state (on/off) to another (off/on) by implanting appropriate impurities into the silicon beneath the gate region is publicly known.
For example, in an N-channel device, increasing the boron implant moves the device into enhancement mode, ie, the threshold becomes more positive. In P-channel devices, boron has the opposite effect, i.e. increasing boron implantation can transform the P-channel device from an enhancement mode to a depletion mode device (the threshold is (The result is negative.)

Referring to FIG. 2, the graph shows an interface 6 between a memory gate layer 36 of silicon dioxide and an epitaxial layer 14 of a silicon substrate.
The impurity concentration is plotted on the vertical axis as a function of the distance of the device to the substrate, with a vertical line indicating zero.

The solid curve 62 is the N-channel EAROM.
shows the impurity concentration due to boron implantation under the memory gate of . As noted, the peak of the boron impurity concentration is slightly below the interface 60.

In channel shield mode, the gates and drains of the erased memory transistors are biased to approximately +25 volts write voltage for N-EAROMS, and the sources are floated. The erased N-channel memory gate region 36 is a depletion device, and the enhancement non-memory gate region 32 is a +
It is turned on to 25V, so when the gate and drain are biased to +25 volts, the source will also float to +25 volts. This means that the source and drain are reverse biased with respect to the substrate and that source-gate-drain are at equal potential.

While one would initially think that the erased state would remain since the source, gate and drain are at the same potential, the electric field in the memory gate region terminating at the inversion layer in the silicon
Transferring the charge within the nitride layer again. Since the gate is positively biased with respect to the silicon, holes trapped at the silicon dioxide-nitride interface (recall the device in the erased state) can be injected into the silicon, and this Electrons from the inversion layer can be injected into the memory interface.

Over a period of time, the device is eventually written to due to such charge movement and thus poses a channel shielding problem. To reduce this problem, the electric field at the memory state that causes this charge movement should be made as small as possible. This can be accomplished by reducing the surface concentration of dopant or the like within the silicon. However, if the surface doping is arbitrarily reduced, the erase-write window, i.e., the difference between the erase and write threshold voltages, becomes smaller for the split-gate device, thereby making the erase - There may be problems when writing. This is undesirable. The purpose is to keep the threshold the same value and yet achieve greater channel shielding.

In general, channel shielding depends on the thickness of nitride layer 40 and the surface concentration of impurities within silicon 14. The higher the impurity concentration at the surface of the epitaxial layer, the greater the electric field strength and the higher the excitation level of the charge in the nitride layer, the more the charge is transferred from the nitride layer to the neighboring cell and the cell in question is erased. In this state, cells adjacent to the erased state are likely to be inverted to the written state. It is therefore desirable that the maximum point of impurity concentration be shifted to a point further below the interface 60. To achieve this, impurities of the opposite conductivity type, such as phosphorus, are also implanted very close to the Si-SiO ₂ interface 60. Phosphorus acts in the opposite direction to boron in terms of electrical conductivity. More effectively, it shifts the surface impurity concentration peak further to the right,
That is, the impurity is further shifted toward the epitaxial layer, and the surface concentration of impurities is reduced at the surface.
The concentrations of the two impurities are subtractive rather than additive, forming curve 66 rather than curve 62, ie, the surface concentration is reduced at the interface.

Additional shallow implants of phosphorus do not significantly change the width of the depletion layer. The width of this depletion layer is the hatched part 68
It is shown by. Therefore, the threshold voltage V _T
remains substantially the same, and the difference (window) between erase and write threshold voltages also remains distinctly constant.

Essentially, the use of phosphorus compensates for boron at the surface. The electric field between the gate and silicon depends on the surface impurity concentration. As the surface concentration decreases, the electric field also decreases,
And therefore the channel shielding is improved as described above.

Figures 3A-3F show this device at various stages in its manufacture. The N-type impurity substrate 12 provides mechanical stiffness to the epitaxially grown substrate layer 14 of P-type material by diffusion into a separation channel of N-type material in the substrate layer of P-type material. Stop 16 is grown. A layer 19 of silicon dioxide is grown across the entire surface of epitaxial layer 14 using conventional oxidation techniques.

Then source and drain regions 20 and 22
is placed in layer 14 by a suitable diffusion method. This is done through oxide layer 19 in a conventional manner. Source and drain regions 20 and 22 are N-type impurity material.

To create a field oxide layer 26, as shown in FIG. 3C, on the top surface of the previous oxide,
Another oxide layer is deposited. This is done by a pyrolysis reaction in a conventional manner. The field oxide layer is sufficiently thick, for example about 1 to 2 microns.

As shown in FIG. 3D, field oxide layer 26 is etched to form vertically upwardly extending walls 29 that define memory cell region 30. As shown in FIG. In the etched area 30, approximately
A 400 to 600 Å gate oxide 32 is thermally grown. The memory area 34 is then defined using photolithographic techniques.

Impurity implants occur in regions 30 and 34, with the implant in region 34 being the most important as it controls the characteristics of the memory and the properties of the channel shield. This is done, for example, by ion implantation. Typical implant doses are: Boron: 35KeV, typically 5.5×10 ¹² cm ⁻³ Phosphorus: 80KeV, typically 1.7×10 ¹² cm ⁻³ . This region 34 is etched to the surface of the epitaxial layer 14 to form a tunnel region for the gate region of the memory.

In the tunnel region 34, a layer 36 of silicon dioxide is grown with a thickness in the range of 10 to 40 Å. It is grown by a thermal reaction of oxygen with a silicon substrate. This can be done at atmospheric pressure, or alternatively, to improve the memory properties of the device, the tunnel oxide layer can be grown by a low pressure oxidation reaction. This is discussed in pending United States Patent Application Serial No. 120791, filed February 12, 1980, and assigned to the same assignee.

A layer of silicon nitride 40 is then deposited over the entire device. This is preferably done by chemical vapor deposition techniques. In a preferred method,
Ammonia gas (NH ₃ ) is flowed into the furnace at low speed and pressure along with other gases, such as dichlorosilane (SiH ₂ Cl ₂ ). The flow of ammonia gas and dichlorosilane gas is carried out until the nitride layer reaches the desired thickness. For example, this is anywhere from 300 Å to 600 Å. The ammonia to silane ratio is approximately
The range is 50:1.

Deposition of nitride layer 40 forms an interface 46 in the memory channel region between silicon dioxide layer 34 and nitride layer 40 in the tunnel gate region.
Tunneling through the thin oxide layer 34, with subsequent charge accumulation at the interface 46, produces the memory properties as previously discussed.

FIG. 1 shows the completed device, as previously described. The intermediate step of etching contact holes through the nitride and oxide layers to the source and drain regions was eliminated.
To complete the device, metal electrodes 50 and 52 for source 20 and drain 22 and electrode 54 for memory gate region 34 are then deposited, for example by suitable vapor deposition techniques, and formed by photolithographic techniques. be done.

The use of double implants of impurities increases the channel shielding capability of the EAROM compared to devices where only a single implant was performed.

This invention utilizes a split gate type
It has been described with respect to EAROM devices. It can also be used in flat gate devices. In a flat gate device, split gate region 32 is not present. Instead, the memory channel area extends over the entire area 30 between the vertical walls 29.

The invention has also been described with respect to N-channel EAROM. In a P channel device, if the same effect were to be achieved, then the critical impurity concentration for controlling V _T would be, for example, either phosphorus or arsenic. For example, boron may be used to shift the concentration peak.

[Brief explanation of drawings]

FIG. 1 is a side cross-sectional view of a complete split gate type EAROM cell according to the present invention. FIG. 2 is a graph showing the effect of surface concentration of impurities produced by double implantation. 3rd A
Figures 3-3F illustrate a split-gate EAROM at various stages of manufacture. In the figure, 10 is an EAROM split gate memory cell, 12 is a substrate, 14 is an epitaxial layer, 16 is an isolation diffusion, 19 is an oxide layer, 20 is a source region, 22 is a drain region, and 26 is a field. oxide layer, 29
3 is a vertical barrier, 30 is a memory gate region of a cell, and 3 is a vertical barrier.
2 is a split gate region, 34 is a tunnel region, 36 is a tunnel gate layer, 40 is a nitride layer,
46 is an interface, 50 and 52 are electrodes, 54 is a gate electrode, and 60 is an interface.

Claims (1)

Claims: 1. A substrate comprising a material of a first conductivity type, a source region and a drain region comprising a second conductivity type within the substrate, and a substrate formed between the source region and the drain region. a memory gate region, wherein the source and drain regions include two mutually overlapping layers of insulating material on the substrate in the memory gate region, and the charge is disposed between the two layers. electrodes are connected to an upper layer of insulating material of the source, drain and gate regions, the substrate in the memory gate region having a higher electrical conductivity than the substrate; a first impurity material of a first conductivity type forming a first region of the first conductivity type having a second impurity material of a second conductivity type opposite to the first conductivity type forming a second region of the first conductivity type; A second region is electrically rewritable and has a lower conductivity than the first region to form a relatively shallow areal concentration distribution of impurities in the memory gate region of the substrate. read-only memory device. 2. The two superimposed layers comprise a layer of silicon dioxide on the substrate and a layer of silicon nitride on top of the layer of silicon dioxide. equipment. 3. The method of claim 1, wherein the first impurity material is doped into the substrate in the memory gate region to obtain a desired threshold voltage for placing the device in a write state. Device. 4. The device of claim 3, wherein the conductivity type of the first impurity is opposite to the conductivity type of the source and drain regions. 5. The device of claim 4, wherein the conductivity type of the second impurity is the same as the conductivity type of the source and drain regions. 6. The device of claim 1, wherein the substrate is of P-type conductivity type material and the source and drain are of N-type conductivity material. 7. The device of claim 6, wherein the first impurity material in the substrate of the memory gate region is a P-type material and the second impurity material is of the N-type. 8. The substrate of the memory gate region is:
8. Device according to claim 7, doped with boron as said first impurity material. 9. The apparatus of claim 8, wherein the second impurity material is selected from the group consisting of phosphorus and arsenic. 8. The device of claim 7, wherein 10 boron is implanted in the substrate under the memory gate by ion implantation to obtain the desired written state threshold voltage. 11 Boron has an energy of 30 to 40 KeV,
In the range from about 5 x 10 ¹² cm ^-3 to about 17 x 10 ¹² cm,
11. The device of claim 10, wherein the device is implanted into the substrate by ion implantation. 12 In the substrate of the memory gate region, the second impurity material is phosphorous and has an energy of 70 to 80 KeV and a concentration of about 1×10 ¹² to about 2×
11. The device of claim 10, wherein the implantation is performed by ion implantation in the range of 10 ¹² cm ^-3 . 13 providing a substrate of a first conductivity type material; forming source and drain regions of a second conductivity type within said substrate; forming a memory gate region between the source and drain of the overlapping layers to allow charge to accumulate at the interface of the two layers; connecting an electrode to an upper layer of material; and applying a first impurity material of the first conductivity type to the substrate in the memory gate region to have a higher conductivity than the substrate. forming a first region of one conductivity type;
a second region of the first conductivity type by providing a second impurity material of a second conductivity type opposite to the first conductivity type in a region adjacent the surface of the substrate over the region of the first conductivity type; and forming a planar concentration distribution of impurities in the memory gate region of the substrate by making the conductivity of the second region lower than the conductivity of the first region. A method of manufacturing an electrically rewritable read-only memory, comprising steps.