JPH02195262A - Apparatus for detecting speed signal - Google Patents

Apparatus for detecting speed signal

Info

Publication number
JPH02195262A
JPH02195262A JP1014145A JP1414589A JPH02195262A JP H02195262 A JPH02195262 A JP H02195262A JP 1014145 A JP1014145 A JP 1014145A JP 1414589 A JP1414589 A JP 1414589A JP H02195262 A JPH02195262 A JP H02195262A
Authority
JP
Japan
Prior art keywords
signal
speed
pulse signal
pulse
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1014145A
Other languages
Japanese (ja)
Inventor
Hisashi Kinoshita
木下 久
Shinobu Kake
忍 懸
Masaki Hashikawa
橋川 正喜
Shigeo Mitani
三谷 重雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1014145A priority Critical patent/JPH02195262A/en
Publication of JPH02195262A publication Critical patent/JPH02195262A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To output sufficiently smoothed speed signal at an extremely low speed and fully cope with high speed and high resolution by outputting speed signals while switching over low speed and high speed. CONSTITUTION:A divider-circuit 6 divides a pulse signal P1 from a signal processing circuit 2 to output a pulse signal P2. A changeover switch 7 outputs the pulse signal P1 as a pulse signal P3 when speed of a driving source connected to a rotary encoder 1 is low and outputs the pulse signal P2 as the pulse signal P3 when the speed is high. A one-shot multi-oscillation circuit 8 for receiving this pulse signal P3 converts it into a pulse signal P4 having pulse width T2 and outputs it. An F/V conversion circuit 9 for receiving the pulse signal P4 converts the pulse sequence into speed signal S1 proportional to the number of pulses per certain time period. A polarity giving circuit 10 for receiving the speed signal S1 and rotation direction signal N reverses the polarity of the speed signal S1 according to the signal N to output it as speed signal S2.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、工作機械やロボットを駆動するデジタルサー
ボシステムのロータリーエンコーダの出力信号から系の
動特性を検出する速度信号検出装置に関するものである
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a speed signal detection device that detects the dynamic characteristics of a digital servo system that drives a machine tool or robot from the output signal of a rotary encoder of the system. .

(従来の技術) 従来の速度信号検出装置の一構成例を第3図に示し、そ
の動作原理を以下に説明する。
(Prior Art) An example of the configuration of a conventional speed signal detection device is shown in FIG. 3, and its operating principle will be explained below.

デジタルサーボシステムの駆動源に直結したロータリエ
ンコーダ(RE)1の出力である90”位相の異なるA
相信号とB相信号を入力とする信号処理回路2は、A相
信号とB相信号の各エツジを、一定時間幅T、のパルス
に変換したパルス信号P1と、A相信号とB相信号の位
相から回転方向を検出して回転方向N、とを出力する。
A with a 90" phase difference, which is the output of the rotary encoder (RE) 1 directly connected to the drive source of the digital servo system.
The signal processing circuit 2, which receives the phase signal and the B-phase signal as input, converts each edge of the A-phase signal and the B-phase signal into a pulse with a constant time width T, and generates a pulse signal P1, and the A-phase signal and the B-phase signal. The rotational direction is detected from the phase of , and the rotational direction N is output.

回転方向信号N、を入力とする電圧変換回路3は、回転
方向信号N8がハイの時はパルス変換回路4の電源電圧
を正にし、回転方向信号N工がローの時はパルス変換回
路4の電源電圧を負にした回転方向信号N2に変換する
。パルス変換回路4は3ステートICで構成し、パルス
信号P1をコントロール端子(C)の入力とし1回転方
向信号N2を入力ボート(I)に接続することで出力ポ
ート(0)には、パルス信号P1がハイの間入力ポート
の電圧が出力され、ローの間はハイインピーダンスとな
り、出力電圧は零となる。
The voltage conversion circuit 3, which receives the rotation direction signal N, makes the power supply voltage of the pulse conversion circuit 4 positive when the rotation direction signal N8 is high, and makes the power supply voltage of the pulse conversion circuit 4 positive when the rotation direction signal N8 is low. The power supply voltage is converted into a negative rotation direction signal N2. The pulse conversion circuit 4 is composed of a 3-state IC, and the pulse signal P1 is input to the control terminal (C), and the one rotation direction signal N2 is connected to the input port (I), so that the pulse signal is output to the output port (0). While P1 is high, the voltage at the input port is output, and while P1 is low, the impedance is high and the output voltage is zero.

パルス変換回路4の電源は絶対値の等しい正電源と負電
源で構成している。これによりパルス変換回路4の出力
は回転方向に1って極性の異なる。
The power supply of the pulse conversion circuit 4 is composed of a positive power supply and a negative power supply having the same absolute value. As a result, the output of the pulse conversion circuit 4 has a polarity that differs by one in the rotational direction.

パルス幅T、のパルス信号P、となる。パルス信号P2
を入力とする積分回路5は、前記パルス信号P2を積分
することで、平滑化され、デジタルサーボシステムの駆
動源の速度に比例した速度信号Sを出力する。
A pulse signal P having a pulse width T is obtained. Pulse signal P2
The integrating circuit 5, which receives as input, integrates the pulse signal P2 to output a smoothed speed signal S that is proportional to the speed of the drive source of the digital servo system.

(発明が解決しようとする課題) 上述した従来の構成においては、高速及び高分解能化し
ようとする下記の欠点が発生する。
(Problems to be Solved by the Invention) In the conventional configuration described above, the following drawbacks occur when attempting to achieve high speed and high resolution.

高速及び高分解能化すると、信号処理回路2の応答周波
数をアップし、パルス信号P□のパルス幅Tユを小さく
する必要がある。そのためパルス変換回路4を3ステー
トエCで構成することは困難となる。
Increasing the speed and resolution requires increasing the response frequency of the signal processing circuit 2 and decreasing the pulse width T of the pulse signal P□. Therefore, it is difficult to configure the pulse conversion circuit 4 with three state controllers.

また極低速においては十分平滑した速度信号Sが得られ
ない問題点があった。
Furthermore, there is a problem that a sufficiently smooth speed signal S cannot be obtained at extremely low speeds.

(課題を解決するための手段) 本発明は上記の課題を解決することを目的とし。(Means for solving problems) The present invention aims to solve the above problems.

デジタルサーボシステムの駆動源に直結したロータリー
エンコーダの90°位相の異なるA相信号とB相信号か
ら1回転方向信号N及び各相のパルスエツジを一定時間
幅T1のパルス信号P4に変換する信号処理回路と、前
記パルス信号Pユの1/nに分周したパルス信号P2を
出力する分周回路と、低速の場合はパルス信号P8を、
高速の場合はパルス信号P、を選択してパルス信号P、
として出力する切替スイッチと、前記パルス信号P3を
一定時間幅T2のパルス信号P、に変換するワンショッ
トマルチ発振回路と、前記パルス信号P4を速度信号S
1に変換するF/V変換回路と、前記速度信号S1及び
前記回転方向信号Nから、回転方向によって増幅率の等
しい反転増幅器と非反転増幅器を切替える極性付与回路
とで速度信号S2を出力するように構成したことを特徴
とする。
A signal processing circuit that converts the 1-rotation direction signal N and the pulse edge of each phase into a pulse signal P4 with a constant time width T1 from the A-phase signal and B-phase signal with 90° different phases of the rotary encoder directly connected to the drive source of the digital servo system. , a frequency dividing circuit that outputs a pulse signal P2 whose frequency is divided by 1/n of the pulse signal P, and a pulse signal P8 in the case of low speed,
For high speed, select pulse signal P,
a one-shot multi-oscillator circuit that converts the pulse signal P3 into a pulse signal P with a constant time width T2, and a one-shot multi-oscillation circuit that converts the pulse signal P4 into a speed signal S.
1, and a polarization circuit that switches between an inverting amplifier and a non-inverting amplifier with equal amplification factors depending on the rotation direction from the speed signal S1 and the rotation direction signal N to output a speed signal S2. It is characterized by being configured as follows.

(作 用) 本発明は、上記した構成により、低速と高速とを切替え
て速度信号を出力するため、極低速時にも十分平滑した
速度信号が出力でき、高速高分解能化されても十分対応
できる。
(Function) With the above-described configuration, the present invention outputs a speed signal by switching between low speed and high speed, so a sufficiently smooth speed signal can be output even at extremely low speeds, and it can sufficiently cope with high speed and high resolution. .

(実施例) 以下に本発明の一実施例を第1゛図のブロック図及び第
2図の極性付与回路により詳細に説明する。
(Embodiment) An embodiment of the present invention will be described in detail below with reference to the block diagram of FIG. 1 and the polarization circuit of FIG. 2.

なお、従来例と同じものは説明を省略する。Note that the description of the same components as in the conventional example will be omitted.

第1図において、分局回路6は信号処理回路2からのパ
ルス信号Pユを入力とし、パルス数を1/nに分周して
、パルス信号Pヨを出力する。切替スイッチ7では、ロ
ータリーエンコーダ1に接続した駆動源の速度が低速の
時は前記パルス信号P1をパルス信号P、として出力し
、高速の時は前記パルス信号P2をパルス信号P、とし
て出力する。
In FIG. 1, the division circuit 6 receives the pulse signal P from the signal processing circuit 2, divides the number of pulses into 1/n, and outputs the pulse signal P. The changeover switch 7 outputs the pulse signal P1 as a pulse signal P when the speed of the drive source connected to the rotary encoder 1 is low, and outputs the pulse signal P2 as a pulse signal P when the speed is high.

このパルス信号P3を入力とするワンショットマルチ発
振回路8では、パルス幅T2のパルス1号P4に変換し
て出力する。
The one-shot multi-oscillation circuit 8 which receives this pulse signal P3 as input converts it into a pulse No. 1 P4 having a pulse width T2 and outputs it.

またパルス信号P4を入力するF/V変換回路9では、
パルス列を一定時間毎のパルス数に比例した速度信号S
1に変換する0次に速度信号S□と回転方向信号Nとを
入力する極性付与回路10では、回転方向信号Nに応じ
て、速度信号Siの極性を反転させ、速度信号S2とし
て出力する。
Further, in the F/V conversion circuit 9 which inputs the pulse signal P4,
A speed signal S that is proportional to the number of pulses per fixed time for a pulse train
A polarization circuit 10, which receives the zero-order speed signal S□ to be converted to 1 and the rotational direction signal N, inverts the polarity of the speed signal Si according to the rotational direction signal N and outputs it as a speed signal S2.

第2図に示す極性付与回路10では、速度信号S□を入
力とし、回転方向信号Nがハイの時は、オペアンプ11
の非反転端子(+)に接続したFETIをオンして、す
でにオンしているFET2のソースに接続することで、
非反転端子(+)を、Ovにする。これにより、オペア
ンプ11の反転端子(−)に入力される速度信号S8を
入力とし、反転増幅して次式の速度信号S2を出力する
In the polarization circuit 10 shown in FIG. 2, the speed signal S□ is input, and when the rotation direction signal N is high, the operational amplifier 11
By turning on FETI connected to the non-inverting terminal (+) of , and connecting it to the source of FET2 which is already on,
Set the non-inverting terminal (+) to Ov. As a result, the speed signal S8 input to the inverting terminal (-) of the operational amplifier 11 is inputted, inverted and amplified, and the speed signal S2 of the following equation is output.

速度信号S2=速度信号S□×−二R,−・・・(1)
R1 FETIのオン電圧が温度により変化しても、FET2
も同様に変化するため、オフセット電圧の変動は少い。
Speed signal S2 = speed signal S□×-2R, -... (1)
Even if the on-voltage of R1 FETI changes due to temperature, FET2
changes in the same way, so there is little variation in the offset voltage.

また、回転方向信号Nがローの時は、FETIがオフし
て、オペアンプ11の非反転端子(+)は。
Further, when the rotation direction signal N is low, FETI is turned off and the non-inverting terminal (+) of the operational amplifier 11 is turned off.

速度信号S1と同電位となり、極性付与回路では、次式
の速度信号S、を出力する。
It has the same potential as the speed signal S1, and the polarization circuit outputs a speed signal S expressed by the following equation.

速度信号S@=速度信号S1・・・(2)そこで(1)
式に示す、RL=R,とすることで1回転方向が異った
時、極性の異なる速度信号を出力することができる。
Speed signal S@=speed signal S1... (2) Then (1)
By setting RL=R as shown in the equation, speed signals with different polarities can be output when the direction of one rotation is different.

(発明の効果) 以上説明したように本発明によれば、高速、高分解能化
しても、低速と高速とを切替えて速度信号を出力するこ
とによって、極低速時にも十分平滑した速度信号を出力
することできる。
(Effects of the Invention) As explained above, according to the present invention, even when high speed and high resolution are achieved, by outputting a speed signal by switching between low speed and high speed, a sufficiently smooth speed signal is output even at extremely low speeds. I can do that.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例におけるブロック図。 第2図は第1図の極性付与回路の一実施例における回路
図、第3図は従来例の回路図を示す。 1 ・・・ ロータリーエンコーダ、 2 ・・・信号
処理回路、 6 ・・・分周回路、 7 ・・・切換ス
イッチ、 8 ・・・ワンショットマルチ発振回路、 
9 ・・・ F/V変換回路。 10・・・極性付与回路、 p、、 p、、 p、。 P4・・・パルス信号、 N・・・回転方向信号、 S
l、S、・・・速度信号。 特許出願人 松下電器産業株式会社 第2図
FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a circuit diagram of an embodiment of the polarization circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of a conventional example. DESCRIPTION OF SYMBOLS 1... Rotary encoder, 2... Signal processing circuit, 6... Frequency division circuit, 7... Changeover switch, 8... One-shot multi-oscillation circuit,
9...F/V conversion circuit. 10...Polarization circuit, p,, p,, p,. P4...Pulse signal, N...Rotation direction signal, S
l, S,...Speed signal. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 2

Claims (2)

【特許請求の範囲】[Claims] (1)ロータリーエンコーダの90°位相の異なるA相
信号とB相信号から、回転方向信号N及び各相のパルス
エッジを一定時間幅T_1のパルス信号P_1に変換す
る信号処理回路と、前記パルス信号P_1の1/nに分
周したパルス信号P_2を出力する分周回路と、低速の
場合はパルス信号P_1を、高速の場合はパルス信号P
_2を選択してパルス信号P_3として出力する切替ス
イッチと、前記パルス信号P_3を一定時間幅T_2の
パルス信号P_4に変換するワンショットマルチ発振回
路と、前記パルス信号P_4を速度信号S_1に変換す
るF/V変換回路と、前記速度信号S_1及び前記回転
方向信号Nから、回転方向によって極性が変わる速度信
号S_2に変換する極性付与回路とで構成したことを特
徴とする速度信号検出装置。
(1) A signal processing circuit that converts the rotational direction signal N and the pulse edges of each phase into a pulse signal P_1 with a constant time width T_1 from the A-phase signal and B-phase signal of a rotary encoder having 90° different phases, and the pulse signal A frequency dividing circuit that outputs a pulse signal P_2 whose frequency is divided by 1/n of P_1, a pulse signal P_1 when the speed is low, and a pulse signal P when the speed is high.
a selector switch that selects and outputs the pulse signal P_2 as a pulse signal P_3; a one-shot multi-oscillator circuit that converts the pulse signal P_3 into a pulse signal P_4 with a constant time width T_2; and an F that converts the pulse signal P_4 into a speed signal S_1. 1. A speed signal detection device comprising: a /V conversion circuit; and a polarization circuit that converts the speed signal S_1 and the rotation direction signal N into a speed signal S_2 whose polarity changes depending on the rotation direction.
(2)前項(1)記載の極性付与回路が、回転方向によ
って増幅率の等しい反転増幅器と非反転増幅器を切替え
るよう構成したことを特徴とする請求項(1)記載の速
度信号検出装置。
(2) The speed signal detection device according to claim (1), wherein the polarization circuit according to item (1) is configured to switch between an inverting amplifier and a non-inverting amplifier having equal amplification factors depending on the direction of rotation.
JP1014145A 1989-01-25 1989-01-25 Apparatus for detecting speed signal Pending JPH02195262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1014145A JPH02195262A (en) 1989-01-25 1989-01-25 Apparatus for detecting speed signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1014145A JPH02195262A (en) 1989-01-25 1989-01-25 Apparatus for detecting speed signal

Publications (1)

Publication Number Publication Date
JPH02195262A true JPH02195262A (en) 1990-08-01

Family

ID=11852985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1014145A Pending JPH02195262A (en) 1989-01-25 1989-01-25 Apparatus for detecting speed signal

Country Status (1)

Country Link
JP (1) JPH02195262A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104019020A (en) * 2014-05-28 2014-09-03 中广核核电运营有限公司 Control system for main pump measurement circuit of digital nuclear power station

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104019020A (en) * 2014-05-28 2014-09-03 中广核核电运营有限公司 Control system for main pump measurement circuit of digital nuclear power station

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