JPH02192274A - Video signal processing circuit - Google Patents

Video signal processing circuit

Info

Publication number
JPH02192274A
JPH02192274A JP1121389A JP1121389A JPH02192274A JP H02192274 A JPH02192274 A JP H02192274A JP 1121389 A JP1121389 A JP 1121389A JP 1121389 A JP1121389 A JP 1121389A JP H02192274 A JPH02192274 A JP H02192274A
Authority
JP
Japan
Prior art keywords
signal
screen
sub
synchronization
horizontal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1121389A
Other languages
Japanese (ja)
Inventor
Tatsuo Yugawa
湯川 達雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1121389A priority Critical patent/JPH02192274A/en
Publication of JPH02192274A publication Critical patent/JPH02192274A/en
Pending legal-status Critical Current

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  • Processing Of Color Television Signals (AREA)
  • Studio Circuits (AREA)

Abstract

PURPOSE:To avoid the disturbance in a sub-screen by reading a sub screen signal from a sub screen generating circuit at no input of a main screen video signal and synchronizing the drive of a CRT with a sub screen video signal. CONSTITUTION:A synchronizing signal switching circuit 5 uses a signal 13 from a synchronizing signal detection circuit 2 to input sub screen horizontal and vertical signals 16, 17 from a synchronizing signal processing circuit 4 as a horizontal signal 18 and a vertical signal 19 to a sub screen generating circuit 7 and a CRT 9. When a main screen video signal is not inputted to the sub screen generating circuit 7, a sub screen signal 21 is read synchronously with the sub screen horizontal and vertical signals 16, 17, which are inputted to an RGB switching circuit 18. Thus, the disturbance in the sub screen is prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は映像信号処理回路に関し、特にピクチャー・イ
ン・ピクチャー方式の映像信号処理回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing circuit, and particularly to a picture-in-picture video signal processing circuit.

〔従来の技術〕[Conventional technology]

TV、VTR,VDP等の民生用画像機器において、主
画像に縮小した副画像を挿入することにより、2種類以
上の異なった画像を合成して表示するピクチャー・イン
・ピクチャー方式の映像信号処理回路を有するものがあ
る。
A picture-in-picture video signal processing circuit that synthesizes and displays two or more different images by inserting a reduced sub-image into the main image in consumer image equipment such as TVs, VTRs, and VDPs. There are some that have

従来のピクチャー・イン・ピクチャー方式の映像信号処
理回路は第2図に示すように、主画面用映像信号10を
処理する第1のビデオクロマ処理回路1と第1の同期信
号処理回路3、副画面用映像信号11を処理する第2の
ビデオクロマ処理回路6と第2の同期信号処理回路4、
副画面生成回路7およびRGB信号切替回路8とがら構
成され、第2のビデオクロマ処理回路6により復調され
た第2のコンポーネント信号20は、同期信号処理回路
4の出力信号16.17に同期して副画面生成回路7に
書き込まれ、圧縮処理をした後、同期信号処理回路3の
出力信号に同期して読み出される。これは、縮小した副
画面信号を第1のコンポーネント信号に挿入するために
は、主画面用映像信号と同期をとる必要があるからであ
る。
As shown in FIG. 2, a conventional picture-in-picture video signal processing circuit includes a first video chroma processing circuit 1 that processes a main screen video signal 10, a first synchronization signal processing circuit 3, and a sub-video chroma processing circuit 1. a second video chroma processing circuit 6 that processes the screen video signal 11 and a second synchronization signal processing circuit 4;
The second component signal 20, which is composed of a sub-screen generation circuit 7 and an RGB signal switching circuit 8 and demodulated by the second video chroma processing circuit 6, is synchronized with the output signal 16.17 of the synchronization signal processing circuit 4. After being written to the sub-screen generation circuit 7 and subjected to compression processing, it is read out in synchronization with the output signal of the synchronization signal processing circuit 3. This is because in order to insert the reduced sub-screen signal into the first component signal, it is necessary to synchronize with the main-screen video signal.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の映像信号処理回路は、主画面用映像信号
に同期して副画面信号を読み出すため、例えばTVの空
チヤンネル受信時のように、第1の同期信号処理回路か
ら出力される主画面用水平及び垂直信号がノイズにより
絶えず変化しているような場合、たとえ副画面用映像信
号が正常に入力されていても、主画面用映像信号が空チ
ャンネルであれば副画面の再生映像が乱れ、正常に表示
することができないという欠点がある。
The conventional video signal processing circuit described above reads out the sub-screen signal in synchronization with the main-screen video signal. If the horizontal and vertical signals for the main screen are constantly changing due to noise, even if the video signal for the sub screen is input normally, if the video signal for the main screen is an empty channel, the played video on the sub screen will be distorted. , it has the disadvantage that it cannot be displayed normally.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の映像信号処理回路は、主画面用映像信号を復調
して第1のコンポーネント信号を出力する第1のビデオ
クロマ処理回路と1、副画面用映像信号を復調して第2
のコンポーネント信号を出力する第2のビデオクロマ処
理回路と、前記第2のコンポーネント信号を圧縮して前
記第1のコンポーネント信号の特定の領域に挿入して合
成信号を形成するRGB信号切換回路とを有するピクチ
ャー・イン・ピクチャー方式の映像信号処理回路におい
て、前記主画面用映像信号から同期信号を検出して前記
主画面用映像信号の有無を検出する同期検出回路と、前
記主画面用映像信号から同期信号を分離し前記同期信号
に同期した主画面用水平及び垂直信号を発生させる第1
の同期信号処理回路と、前記副画面用映像信号を入力し
て副画面用水平及び垂直信号を発生させる第2の同期信
号処理回路と、前記主画面用水平及び垂直信号と前記副
画面用水平及び垂直信号とを入力して前記同期信号検出
回路の出力信号により制御し前記主画面用映像信号が入
力されているときには前記主画面用水平及び垂直信号を
出力し前記主画面用映像信号が入力されないときには前
記副画面用水平及び垂直信号を出力する同期信号切換回
路と、前記第2のコンポーネント信号を前記副画面用水
平及び垂直信号に同期させて入力し圧縮処理をした後前
記同期信号切換回路より出力される水平及び垂直信号に
同期して出力する副画面信号を前記RGB信号切換回路
に入力する副画面生成回路とを含んで構成される。
The video signal processing circuit of the present invention includes a first video chroma processing circuit that demodulates a main screen video signal and outputs a first component signal, and a second video chroma processing circuit that demodulates a sub screen video signal and outputs a first component signal.
a second video chroma processing circuit that outputs a component signal; and an RGB signal switching circuit that compresses the second component signal and inserts it into a specific area of the first component signal to form a composite signal. A picture-in-picture video signal processing circuit comprising: a synchronization detection circuit that detects a synchronization signal from the main screen video signal to detect the presence or absence of the main screen video signal; A first unit that separates the synchronization signal and generates horizontal and vertical signals for the main screen that are synchronized with the synchronization signal.
a second synchronization signal processing circuit that receives the sub-screen video signal and generates sub-screen horizontal and vertical signals; and a vertical signal, and is controlled by the output signal of the synchronization signal detection circuit, and when the main screen video signal is input, the main screen horizontal and vertical signals are output, and the main screen video signal is input. a synchronization signal switching circuit that outputs the horizontal and vertical signals for the sub-screen when the horizontal and vertical signals for the sub-screen are not input; and the synchronization signal switching circuit that inputs the second component signal in synchronization with the horizontal and vertical signals for the sub-screen and performs compression processing. and a sub-screen generation circuit that inputs a sub-screen signal to the RGB signal switching circuit, which is output in synchronization with the horizontal and vertical signals output from the RGB signal switching circuit.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

主画面用映像信号10は第1のビデオクロマ処理回路1
により復調されて第1のコンポーネント信号12を出力
し、RGB信号切替回路8へ入力される。一方、同期信
号検出回路2では主画面用映像信号10の有無を検出し
、同期検出信号13を同期信号切替回路5へ入力する。
The main screen video signal 10 is sent to the first video chroma processing circuit 1
The first component signal 12 is demodulated and outputted as the first component signal 12, which is input to the RGB signal switching circuit 8. On the other hand, the synchronization signal detection circuit 2 detects the presence or absence of the main screen video signal 10 and inputs the synchronization detection signal 13 to the synchronization signal switching circuit 5.

また、第1の同期信号処理回路3では主画面映像信号に
同期した水平信号14及び垂直信号15を発生し、同期
信号切替回路5へ入力する。
Further, the first synchronization signal processing circuit 3 generates a horizontal signal 14 and a vertical signal 15 synchronized with the main screen video signal, and inputs them to the synchronization signal switching circuit 5.

同様にして、副画面用映像信号11は第2の同期信号処
理回路4および第2のビデオクロマ処理回路6へ入力さ
れる。同期信号処理回路4では副画面映像信号11に同
期した水平信号16及び垂直信号17を発生し、同期信
号切替回路5へ入力する、同期信号切替回路5では、同
期信号検出回路2からの信号13により、主画面映像信
号入力時には同期信号処理回路3からの主画面用水平及
び垂直信号14.15を、または、無信号時には同期信
号処理回路4からの副画面用水平及び垂直信号16.1
7を、水平信号18、垂直信号19として副画面生成回
路7およびCRT9へ入力する。
Similarly, the sub-screen video signal 11 is input to the second synchronization signal processing circuit 4 and the second video chroma processing circuit 6. The synchronization signal processing circuit 4 generates a horizontal signal 16 and a vertical signal 17 synchronized with the sub-screen video signal 11 and inputs them to the synchronization signal switching circuit 5. The synchronization signal switching circuit 5 generates a signal 13 from the synchronization signal detection circuit 2. Therefore, when the main screen video signal is input, the main screen horizontal and vertical signals 14.15 from the synchronization signal processing circuit 3 are input, or when there is no signal, the sub screen horizontal and vertical signals 16.1 from the synchronization signal processing circuit 4 are input.
7 is input to the sub-screen generation circuit 7 and CRT 9 as a horizontal signal 18 and a vertical signal 19.

副画面生成回路7では、ビデオクロマ処理回路6からの
副画面用コンポーネント信号20を主画面用水平及び垂
直信号14.15に同期して書き込み圧縮処理をした後
、主画面映像信号入力時には主画面用水平及び垂直信号
14.15に、または、主画面映像信号が入力されてい
ないときには副画面用水平及び垂直信号16.17に同
期して副画面信号21を読み出し、RGB切替回路8へ
入力する。
The sub-screen generation circuit 7 writes and compresses the sub-screen component signal 20 from the video chroma processing circuit 6 in synchronization with the horizontal and vertical signals 14 and 15 for the main screen, and then converts it to the main screen when the main screen video signal is input. The sub-screen signal 21 is read out in synchronization with the horizontal and vertical signals 14.15 for the sub-screen, or in synchronization with the horizontal and vertical signals 16.17 for the sub-screen when the main screen video signal is not input, and is input to the RGB switching circuit 8. .

RGB信号切替回路8では、副画面生成回路7からの主
副切替信号22により、コンポーネント信号12と副画
面信号21とを切り替えて主副画面合成信号23をCR
T9へ入力する。
The RGB signal switching circuit 8 switches between the component signal 12 and the sub-screen signal 21 according to the main-sub-screen switching signal 22 from the sub-screen generation circuit 7, and converts the main-sub-screen composite signal 23 into CR.
Input to T9.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、主画面映像信号が無人
力時に、副画面生成回路からの副画面信号の読み出しお
よびCRTの駆動を副画面映像信号に同期させることに
より、主画面映像信号が無人力の場合にも安定した同期
が得られ、副画面が乱れることなく正常に表示すること
ができる効果がある。
As explained above, the present invention enables the main screen video signal to be changed by synchronizing the readout of the subscreen signal from the subscreen generation circuit and the driving of the CRT with the subscreen video signal when the main screen video signal is unattended. Even in the case of unattended operation, stable synchronization can be obtained and the sub-screen can be displayed normally without any disturbance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
従来の映像信号処理回路の一例を示すブロック図である
。 1・・・第1のビデオクロマ処理回路、2・・・同期信
号検出回路、3・・・第1の同期信号処理回路、4・・
・第2の同期信号処理回路、5・・・同期信号切替回路
、6・・・第2のビデオクロマ処理回路、7・・・副画
面生成回路、8・・・RGB信号切替回路、9・・・C
RT、10・・・主画面用映像信号、11・・・副画面
用映像信号、12・・・第1のコンポーネント信号、1
3・・・同期検出信号、14・・・主画面用水平信号、
15・・・主画面用垂直信号、16・・・副画面用水平
信号17・・・副画面用垂直信号、18・・・水平信号
、1つ・・・垂直信号、20・・・第2のコンポーネン
ト信号21・・・副画面信号、22・・・主副切替信号
、23・・・主副画面合成信号。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional video signal processing circuit. DESCRIPTION OF SYMBOLS 1... First video chroma processing circuit, 2... Synchronization signal detection circuit, 3... First synchronization signal processing circuit, 4...
- Second synchronization signal processing circuit, 5... Synchronization signal switching circuit, 6... Second video chroma processing circuit, 7... Sub-screen generation circuit, 8... RGB signal switching circuit, 9.・・C
RT, 10... Video signal for main screen, 11... Video signal for sub screen, 12... First component signal, 1
3...Synchronization detection signal, 14...Horizontal signal for main screen,
15... Vertical signal for main screen, 16... Horizontal signal for sub-screen 17... Vertical signal for sub-screen, 18... Horizontal signal, one... Vertical signal, 20... Second Component signals 21...Sub-screen signal, 22... Main-sub-screen switching signal, 23... Main-sub-screen composite signal.

Claims (1)

【特許請求の範囲】[Claims] 主画面用映像信号を復調して第1のコンポーネント信号
を出力する第1のビデオクロマ処理回路と、副画面用映
像信号を復調して第2のコンポーネント信号を出力する
第2のビデオクロマ処理回路と、前記第2のコンポーネ
ント信号を圧縮して前記第1のコンポーネント信号の特
定の領域に挿入して合成信号を形成するRGB信号切換
回路とを有するピクチャー・イン・ピクチャー方式の映
像信号処理回路において、前記主画面用映像信号から同
期信号を検出して前記主画面用映像信号の有無を検出す
る同期検出回路と、前記主画面用映像信号から同期信号
を分離し前記同期信号に同期した主画面用水平及び垂直
信号を発生させる第1の同期信号処理回路と、前記副画
面用映像信号を入力して副画面用水平及び垂直信号を発
生させる第2の同期信号処理回路と、前記主画面用水平
及び垂直信号と前記副画面用水平及び垂直信号とを入力
して前記同期信号検出回路の出力信号により制御し前記
主画面用映像信号が入力されているときには前記主画面
用水平及び垂直信号を出力し前記主画面用映像信号が入
力されないときには前記副画面用水平及び垂直信号を出
力する同期信号切換回路と、前記第2のコンポーネント
信号を前記副画面用水平及び垂直信号に同期させて入力
し圧縮処理をした後前記同期信号切換回路より出力され
る水平及び垂直信号に同期して出力する副画面信号を前
記RGB信号切換回路に入力する副画面生成回路とを含
むことを特徴とする映像信号処理回路。
A first video chroma processing circuit that demodulates a main screen video signal and outputs a first component signal, and a second video chroma processing circuit that demodulates a sub screen video signal and outputs a second component signal. and an RGB signal switching circuit that compresses the second component signal and inserts it into a specific area of the first component signal to form a composite signal. , a synchronization detection circuit that detects a synchronization signal from the main screen video signal to detect the presence or absence of the main screen video signal; and a main screen that separates the synchronization signal from the main screen video signal and synchronizes with the synchronization signal. a first synchronous signal processing circuit that generates horizontal and vertical signals for the main screen; a second synchronous signal processing circuit that receives the sub-screen video signal and generates horizontal and vertical signals for the main screen; The horizontal and vertical signals and the horizontal and vertical signals for the sub-screen are input and controlled by the output signal of the synchronization signal detection circuit, and when the video signal for the main screen is input, the horizontal and vertical signals for the main screen are input. a synchronization signal switching circuit that outputs the horizontal and vertical signals for the sub-screen when the main screen video signal is not input; and a synchronization signal switching circuit that inputs the second component signal in synchronization with the horizontal and vertical signals for the sub-screen. A video signal characterized in that it includes a sub-screen generation circuit that inputs into the RGB signal switching circuit a sub-screen signal that is output in synchronization with the horizontal and vertical signals output from the synchronization signal switching circuit after compression processing. processing circuit.
JP1121389A 1989-01-19 1989-01-19 Video signal processing circuit Pending JPH02192274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1121389A JPH02192274A (en) 1989-01-19 1989-01-19 Video signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1121389A JPH02192274A (en) 1989-01-19 1989-01-19 Video signal processing circuit

Publications (1)

Publication Number Publication Date
JPH02192274A true JPH02192274A (en) 1990-07-30

Family

ID=11771707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1121389A Pending JPH02192274A (en) 1989-01-19 1989-01-19 Video signal processing circuit

Country Status (1)

Country Link
JP (1) JPH02192274A (en)

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