JPH02191051A - Data processor - Google Patents

Abstract

PURPOSE:To detect at high speed whether desired data exist in a block or not by holding the request information of a request for the block transfer of the data and comparing the address out of the block of this request with the address out of the block of a following request. CONSTITUTION:A holding means 17 is provided to hold the request when a first request 1 is cache miss hit and a comparing means 19 is provided to compare the address in the request information of a second request 2 following to the first request 1 with the address in the request information held by the holding means 17. Then, a means 24 is provided to request the block transfer of the data from a main memory with responding to the second request 2 when the second request 2 is the cache miss hit and the compared result of the comparing means 19 shows dissidence. Thus, it can be detected at high speed that whether the desired data exist in the block which requested the block transfer of the data to the main memory or not exist due to a cache miss.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a data processing device having a cache memory.

Conventional technology In response to a cache miss request, a data block transfer request is made to the main memory. In this case, there are three cases in which subsequent requests are processed, and the processing is performed according to each case. Each one is different.

(2) When the subsequent request is a cash request: In this case, in order to guarantee the order of data, the processing of the subsequent request is waited until the block transfer process of the preceding request is completed.

■When the subsequent request hits the block for which the block transfer request was made and there is a cache miss: In this case, since the desired data exists in the block of the preceding request, the subsequent request cannot be processed. is made to wait until the block transfer processing of the preceding request is completed.

■If the subsequent request misses the cache and also misses the block for which the block transfer request was made; In this case, do not make the preceding block transfer request, and make the block transfer request of the subsequent request immediately after the request. Can be done.

Conventional data processing devices of this type detect the above three conditions and process subsequent requests. , Similar to ■, there is a type in which processing of the subsequent request waits until the block transfer request of the preceding request is completed, and after registering the address information of the preceding request in the cache directory, the subsequent request reindexes the cache directory. There is a type that starts over from scratch, detects a cache miss, and then requests a data block transfer to the main memory in response to a subsequent request.

With the conventional data processing device described above, subsequent requests may be made to wait even though they can be processed immediately, or
Also, if a preceding quest misses the cache, the address information must be registered in the cache directory, and then the cache directory must be indexed by the subsequent request to check the status of the subsequent request. There are drawbacks.

In recent large-scale computers, in order to speed up the processing, 1
Pipeline processing is common, in which one process is divided into multiple stages to parallelize the process.In order to reduce the machine cycle, which is determined by the delay time of each stage, the number of pipeline stages increases. There is a tendency.

Therefore, the stage for indexing the cache directory and the stage for determining cache hits and misses may not be the same stage, but may be divided into multiple stages, and in devices that operate at such high speed machine cycles, It is difficult to directly control the operation of subsequent requests using a signal that detects a cache mishit, so subsequent requests must be controlled at the stage following the stage that detected a cache mishit.

Therefore, if a cache miss is detected in a preceding request, a plurality of subsequent requests will be held between the stage of indexing the cache directory and the stage of determining a cache hit or miss.

In such a state, after registering the address information of the preceding request in the cache directory, in order to index the cache directory in the subsequent request and check the hit-miss status of the cache, the address information held in each of the above stages is required. Management of pipeline stages for evacuation of subsequent requests and indexing of cache directories by subsequent requests, and restoration of ejected subsequent requests to each pipeline stage requires very complex control and considerable The disadvantage is that it requires investment in hardware.

OBJECTS OF THE INVENTION An object of the present invention is to provide a data processing device that can improve the processing performance of subsequent requests following a quest or a cache miss.

Structure of the Invention According to the present invention, there is provided a data processing device having a cache memory that holds a partial copy of the contents of the main memory in units of blocks, wherein when the first request is a cache miss, the request information is held. a holding means for comparing an address in the request information of a second request following the first request with an address in the request information held in the holding means; and means for requesting data block transfer from the main memory in response to the second request in the case of a mishit and when the comparison result of the comparison means indicates a mismatch. is obtained.

Further, according to the present invention, there is provided a cache memory for holding a partial copy of the contents of the main memory in units of blocks, a cache directory means for recording a directory of the contents held in the cache memory, and an index result of the cache directory means. a first stage for indexing the cache directory means in response to a request; and a second stage for determining the cache hit status by the cache hit determination means using the index result. A pipeline processing type data processing device comprising: a cache miss request holding unit that holds request information of a request for which a cache miss has been determined; and a cache miss request holding unit that holds request information of a subsequent request following this request; an index result holding means for holding an index result of the cache directory for a request whose request information is held in the second stage; a comparison means for comparing the address with an address in the request information held in the cache miss request holding means, and a comparison result of the comparison means when the contents of the index result holding means indicate a cache miss; There is obtained a data processing apparatus characterized in that the data processing apparatus includes means for making a data block transfer request from the main memory in response to the request held in the second stage when the second stage indicates a mismatch.

Furthermore, according to the present invention, there is provided a cache memory for holding a partial copy of the contents of the main memory in units of blocks, a cache directory means for recording a directory of contents held in the cache memory, and an index for the cache directory means. a first stage that indexes the cache directory means in response to a request, and a second stage that uses the index result to determine the cache hit status by the cache hit determination means using the index result; a pipeline processing type data processing device comprising: a cache miss request holding means for holding request information of a request for which a cache miss has been determined; and a cache registration compartment for the request for which a cache miss has been determined. means for holding information, means for holding request information of subsequent requests following this request in each of the first and second stages, and an index result of the cache directory for the request whose request information is held in the second stage. an index result holding means for holding an index result holding means; a comparison means for comparing an address in the request information held in the second stage with an address in the request information held in the cache miss request holding means; When the content of the index result holding means indicates a cache miss and the comparison result of the comparison means indicates a mismatch, block data is retrieved from the main memory in response to the request for which the cache miss has been determined. The second stage is read out and registered in the cache memory, and then the address in the request information held in the second stage and the cache registration compartment information of the request for which the cache miss has been determined are used in the second stage. There is obtained a data processing apparatus characterized in that the data processing apparatus comprises means for reading desired data of a request held in the cache memory from the cache memory and sending it to the request source.

fire ship decoy Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the diagram, LARl is a logical address register that receives a request address from a request source, TLB2 is an address translation buffer that converts an address from a logical address to a real address, and AA3 is a block diagram of an embodiment of the present invention. , 4 is an address array which is a cache directory.

Comparator 5 is a comparator that compares the outputs of LARl and TLB2, and comparator 6.7 is a comparator that compares the outputs of TLB2 and AA3.4, respectively.

An inverting circuit 8.9 is an inverting circuit that inverts the outputs of the comparators 6 and 7, an AND circuit 10 is an AND circuit that takes the logical product of the outputs of the inverting circuit 8.9, and FFII is a flip-flop that receives the output of the AND circuit 10. , FF12 and FF13 are flip-flops that receive the outputs of comparators 6 and 7, respectively.

PAR14 is a real address register that receives the real address after address conversion, DAl, 5.16 is a cache data array that holds cache data, CMAR17 is a cache miss address register that holds the real address of a request that misses the cache, ■ bit 18 is C
This is a flag register that indicates that valid information is held in the MAR 14.

The comparator 19 compares the real address outside the block held in the CMAR 17 with the real address outside the block held in the PAR 14, and the NAND circuit 20 compares the output of the bit 18. The AND circuit 21, which is a NAND circuit that performs an AND with the output of one device, inverts the value, and outputs it, is connected to the NAND circuit 20 and the FF.
This is an AND circuit that performs logical product with the output of No. 11.

The selector 22 is a selection circuit that selects the output of DA15.16, and the DAR23 is a data array read register that receives read data from the cache selected by the selector 22.
MAR24 is a memory address register that receives the real address output from PAR14 and sends an address for a data block transfer request to the main memory.
This is an inverting circuit that inverts the output of F11.

The logical address held in LARl is the segment part S,
It consists of a page part P, an address L within the page,
S and P are converted to real addresses by TLB2, and L
A real address is also generated. This TLB2 is S
The remaining parts of S and P are registered as part of key in TLB2, and the real address corresponding to the logical address is registered as a data part at the same address in TLB2.

AA3 and AA4 are cache directories that manage block addresses of cache data arrays in which data is registered in units of blocks. In this embodiment, a cache block is assumed to be 64 bytes. AA3 and AA4 are addressed by the upper outside block address part ignoring the lower 6 bits (intra-block address) of L of LARl, and the remaining S and P parts are addressed by the real address that has undergone address conversion as a key part. be registered.

DA15.16 is a cache data array in which data in units of blocks is registered as a data portion at an address position corresponding to a cache directory. Data is read from the cache data array in units of data requested by the request source. In this embodiment, the unit of this data is assumed to be 8 bytes.

DA15 and DA16 are addressed by the upper 8-byte external address part of the real address corresponding to L of PAR14, ignoring the lower 3 bits (address within 8 bytes), and the corresponding 8-byte data are read out.

In the cache configuration of this embodiment, AA3 and DA15 are
This is a two-level cache configuration in which A4 and DA16 correspond to each other. That is, index AA3 and 4 at the same time,
It is determined which of the DA15 and DA16 the desired data is registered in, and the data read from the DA15 and DA16 is selected and sent to the request source. A
The desired data is found in DA15.1 by the index of A3 and 4.
If it is detected that the address does not exist in any of 6 (hereinafter referred to as a gear miss), the corresponding real address is sent to the main memory, and a block transfer of data is requested from the main memory. The block read from the main memory is registered in the cache, and the requested data is sent to the request source.

Next, the operation shown in FIG. 1 will be explained in detail. The memory access logical address requested from the arithmetic unit is accepted by LARl, and part of the address of LARl is stored in TLB2 and A.
A3 and 4 are addressed.

The address of TLB2 is part of S and P, and the remaining S
and P is compared with the part read from 'T' L B 2 in comparator 5. If the comparison results match, the TL
The data portion of B2, ie, the real address, is set in PAR14. The L of LARl is set in PAR14 as it is without undergoing address translation, and the address translation of the logical address accepted by LARl into a real address is completed.

If the comparison results in a mismatch, - as is well known in the film, an address conversion table on the memory is indexed and the logical address is converted to a real address, and the result is 7.
It is registered in r' L B 2 and the real address is PAR1.
It is set to 4 and address translation ends.

The address of AA3.4 is the out-of-block address part of L of LARI, and the real addresses registered in AA3.4 are supplied to comparators 6 and 7, respectively. at the same time,
The real address read from the data section of TLB2 is supplied to a partner of comparator 6.7. Comparator 6.7 outputs logic 1 if the comparison results in a match, and outputs logic 0 if there is a mismatch.

Suppose now that comparator 6 detects a match. Comparators 6, 7
The comparison results are set to 1, 2, 1, and 3, respectively, and are supplied to the inverting circuit 8.9.

FFs 12 and 13 are set to logic] and logic 0, respectively. The inverting circuit 8.9 inverts the output of the comparator 6.7 to a logic 0.0, respectively. It outputs a logic 1 and outputs it to the AND circuit 10.

AND circuit [10 performs the logical product of the outputs of the inverting circuit 8.9 and sets the result to FFII. Therefore, F F
1.1 is set to logic 0. This FF1l indicates a cash hit miss; logic 0 is set in the case of a hit, and logic 1 is set in the case of a miss. At the same time, when the real address is set to PARl4, DAl is set at an address outside 8 bytes of the real address corresponding to L of PARl4
, 5.16 are addressed, and 8-byte data is simultaneously read from DAl5 and DAl16 and supplied to the selector 22.

Logic 1. which is the output of FF12.13. The logic 0 is supplied to the selector 22, and as a result, the 8-byte data read from the DAl5 becomes valid in the selector 22, which is selected and supplied to the DAR23.

The logic 0 that is the output of the FF11 is inverted by the inverting circuit 25 and a logic 1 is output, which is supplied to the DAR 23 and output from the DAR 2.
The read data from DAl5 set to 3 is sent to the request source as valid data.

The real address set in PARl4 is CMAR17,
The logic O of the FFII is supplied to the MAR 24, but the logic O of the FFII is also supplied to the AND circuit 21, which outputs the logic O as a result of the logical product, and the pins 1 to 18, respectively. As a result, V bit 18 is set to a logic zero indicating that the contents of CMAR 17 are not valid, and the contents of MAR 24 are invalidated and no operations are directed to main memory.

Similarly, when a match is detected by the comparator 7, the DA
The 8-byte data read from l6 is output as valid data to the request source through DAR23.

Next, continuous request 1, which is the characteristic operation of the present invention,
．． 2 both miss the cache will be described in detail. The logical address of request 1 is LARl
When the address is accepted, TLB2 performs address translation and the real address is set in PARl4. A cache miss is detected in the indexes of AA3 and AA4. That is, comparator 6
, 7 both output logic 0 indicating that the comparison result does not match, and the FF
Both 12 and 13 are set to logic 0. Inverting circuit 8 9
inverts the outputs of the comparators 6 and 7 and outputs a logic 1, and the AND circuit 10 outputs a logic 1 indicating a cache miss as a result of the logical product, and sets the logic 1 in FFII.

At this time, the theoretical address of request 2 is LARl.
will be accepted. When the real address of request 1 is set in PARl4, DA1516 is addressed.
At this time, since FFII is outputting logic 1,
The inversion circuit 25 outputs a logic 0 that invalidates the contents of the DAR 23 as the inversion result, all read data from the DAl 5.16 becomes invalid, and data transfer from the DAR 23 to the request source is inhibited.

PARl4, CMAR17, and the out-of-block address are compared in comparator 19, and now ■ bit 18 is CMAR1
7 is invalid, and since this is supplied to the NAND circuit 20, the output of the NAND circuit 20 is forced to become a logic 1 and is supplied to the AND circuit 21. be done. As a result, in the AND circuit 21, FF1
The output of 1 remains valid, indicating a cache miss, and a logic 1 is output and supplied to the V bit 18 and MAR 24.

The real address of request 1 of PARl 4 is CMAR1
bit 18 is set to a logic 1 indicating that the contents of CMAR17 are valid. At the same time, the real address of request 1 of PARl4 is MAR24
is set to , and the logic 1 output of the AND circuit 21 causes
The contents become valid, and a block transfer request for the data of request 1 is sent to the main memory.

The real address of request 1 that caused a cache miss is CMA
At the same time as being set in R,17 and MAR24, the subsequent request 2 is translated into a real address by TLB2 and set in PAR14.

Furthermore, the result of indexing AA3.4 is FF111213
are set respectively. Similar to request 1, request 2 also misses AA3 and 4, and FF1l
, 12.13 have logic 1. Logic 0. Logic O is set. Therefore, the real address of request 2 set in PARl 4 invalidates any data read from DA 15.16, and data transfer from DAR 23 to the request source is inhibited.

At this time, the C that holds the real address of request 1 at the same time
The out-of-block address of MAR17 and the out-of-block address of the real address of request 2 set in PARl4 are compared. (2) Since the bit 18 outputs a logic 1, the NAND circuit 20 inverts the output result of the comparator 19 and outputs it as valid and supplied to the AND circuit 21.

As a result of the comparison, if there is a match, the comparator 19 outputs a logic 1, which is inverted by the NAND circuit 20 and a logic 0 is output from the AND circuit 2.
1. In this case, the out-of-block addresses match, indicating that the requested data of request 2 exists in the block of request 1, which previously requested a block transfer of data to the main memory.
The request for request 2 to transfer a block of data to the main memory is suppressed.

In other words, due to the logic 0 supplied from the NAND circuit 20 to the AND circuit 21, the logic 1 output from the FF 11 indicating a cache miss is changed to a logic 0, which is the same as when the cache is hit, as a result of the AND circuit 21. By outputting from the AND circuit 21, the contents of the MAR 24 that receives the real address of request 2 are invalidated,
Requests to transfer blocks of data to main memory are suppressed.

If the comparison result with one comparator is inconsistent, comparator 1
One outputs a logic 0, which is inverted by a NAND circuit 20 and a logic 1 is supplied to an AND circuit 21. In this case, the out-of-block addresses do not match, indicating that the requested data of request 2 does not exist in the block of request 1, which previously requested a block transfer of data to the main memory. If AA3 and AA4 are missed, a data block transfer request can be directly made to the main memory.

Now, since a logic 1 is being supplied from the NAND circuit 20 to the AND circuit 21, there is no cache miss and the FFI
The logical product of the output of I and the logic 1 is taken, and as a result, a permission signal is outputted from the AND circuit 21 to request a data block transfer to the main memory, and is supplied to the MAR 24.

The real address of request 2 set in PARl4 is set in MAR24, and a block transfer request for request 2 data is sent to the main memory in advance or in succession to a block transfer request for quest 1 data. .

In this way, by holding the request information of the request that previously requested a block transfer of data to the main memory and comparing the out-of-block address of this held request with the out-of-block address of the subsequent request,
The processing performance of the system is improved by quickly detecting whether the desired data exists in the block for which a subsequent request misses the cache and the block of data previously requested to be transferred to the main memory. can be improved.

FIG. 2 is a block diagram of another embodiment of the invention. In the figure, PARl4 is a real address register that receives a real address for indexing the cache directory; 3.
4 is an address array that is a cache directory, and comparators 6 and 7 are comparators that compare the outputs of PAR 14 and AA 3 and 4, respectively.

FF12 and FF13 are flip-flops that receive the comparison result of the comparator 6.7, that is, the cache directory index result; PAR27 is a real address register that receives the real address for indexing the cache data array from PAR14, DA], 5.16 is a cache data array that holds a copy of the data in main memory.

The inverting circuits 8 and 9 are inverting circuits that invert the outputs of the FFs 12 and 13, respectively, and the AND circuit 10 is an AND circuit that performs a logical product of the outputs of the inverting circuits 8 and 9.

MAR24 sets the real address in case of cache miss as P
A memory address register that receives the address of the data block transfer request from the AR27 and sends it to the main memory.The selector 22 transfers the output data of the DA15.16 to the FF12,1
DAR 23 is a data array read register that receives read data from the cache selected by selector 22.

FF11 is a flip-flop that receives the output of the AND circuit 10, CMAR17 is a cache miss address register that holds the actual address of a request that has a cache miss, and ■Bit 18 is a flag that indicates that valid information is held in CMAR17. The register and comparator 19 are comparators that compare the real address outside the block held in the CMAR 17 and the real address outside the block held in the PAR 27.

The NAND circuit 20 is a NAND circuit that takes the logical product of the output of the V bit 18 and the output of the comparator 19, inverts the value, and outputs it, and the AND circuit 21 is a combination of the NAND circuit 20 and the AND circuit 10.
The pipeline cycle control circuit 26, which is an AND circuit that takes the logical product of the outputs of the pipeline period control circuit 26, is a circuit that controls the synchronization of each pipeline.

Stage 1 is a stage for indexing the cache directory, and stage 2 is a stage for determining cache data array indexes, cache hits, and miss hits.

When the cache is indexed, AA3.4 is indexed at the same time, it is determined in which of DA15 and 1.6 the desired data is registered, and the data read from DA15 and 1.6 is selected. and sends it to the request source. The desired data is located in DA1 by the AA3.4 index.
If it is detected that it does not exist in either 5 or 16,
Sends the corresponding real address to main memory to request a block transfer of data from main memory. The block read from the main memory is registered in the cache, and the requested data is sent to the request source.

As described above, in this embodiment, the cache has a two-compartment configuration, but in reality, caches generally have a four-compartment to 16-compartment configuration.

Next, the operation shown in FIG. 2 will be explained in detail.

The logical address for memory access sent from the request source is converted into a real address by an address conversion control unit with a known configuration as shown in FIG.
Sera l- is carried out. When the real address is set in PAR14, AA3 and AA4 are indexed in the lower set address part of the out-of-block address part of the real address, and at the same time, the remaining key address part of the out-of-block address is supplied to the comparator 6.7. Then, a comparison is made with the key address part read from AA3 and AA4.

Comparator 6.7 outputs logic 1 if the comparison result is a match, and outputs logic O if it does not match, and sends the value to FF12.
, 13, respectively. At this time, PAR1
The real address of 4 is set in PAR27.

Assume now that a match is detected on the comparator 6 side and logic 1 and logic O are set in FFs 12 and 13, respectively. DA15
, 16 are addressed by PAR 27, and 8-byte data is read out as the index result and sent to selector 2.
2. Then, D according to the values of FF12 and FF13.
The 8-byte data of A15 is selected and set in DAR23.

On the other hand, the outputs of the FFs 12 and 13 are outputted to the inverting circuit 89, and the respective inverted results are supplied to the AND circuit 10. In this case, logic O1 and logic 1 are respectively supplied, so that logic 0 is output from AND circuit IO. The output of the AND circuit 10 indicates a hit or a miss; a logic 0 is output in the case of a hit, and a logic 1 is output in the case of a miss. This output is FF11
, and is supplied to the request source as a flag indicating whether the data in the DAR 23 is valid or invalid. In this case, since it is a cash hit case, a logic O is supplied from the FF 11 along with the data of the DAR 23.

The real address set in PAR27 is CMARl7.
, MAR, 24, but since the logic O of the output of the AND circuit 10 is supplied to the AND circuit 21, the AND circuit 21 outputs logic 0, and bits 18 and M
Supply to AR24.

As a result, ■ bit 18 is set to logic 0 indicating that the contents of CMAR17 are not valid, and MAR2
The contents of 4 are invalidated, and no operation instruction is given to the main memory.

Next, the characteristic operation of this embodiment, which is the operation when consecutive quests 1 and 2 both miss the cache, will be described in detail. Since request 1 misses the cache, logical O is set in both FFs 12 and 13 at the timing when the real address of request 1 is set in PAR 27.

At this time, the subsequent request 2 or PAR14 is set at the same time.

The mishit operation of request 1 in stage 2 will be described below. AND circuit 10 detects a cache miss and outputs logic 1, and AND circuit 21 . FF
Supply to II. The FFII notifies the request source that the data in the DAR 23 is invalid.

Since the ■ bit 18 is now set to 0, the NAND circuit 20 outputs a logic 1 to the AND circuit 21. As a result, the AND circuit 21 outputs a logic 1 as a result of the logical product of the output of the AND circuit 10 and the logic 1, and the MAR 24 and v
Supply bit 18.

Therefore, the real address of request 1 in PAR 27 that caused the cache miss is set as a valid address in MAR 24, and a block transfer request for the data of request 1 is sent to the main memory. Also, the real address of request 1 of PAR27 is set to CMAR17, and at the same time, V bit 18 is also set to logic 1 and CMAR1 is set to logic 1.
Indicates that the address of Rl7 is valid.

By the way, if a cache miss occurs in a certain request, subsequent requests must be stopped synchronously at each pipeline stage. To do this, it would be sufficient to directly use the output of the AND circuit 10 that detected the cache miss, but the control signals for synchronizing each pipeline stage require very complex logic (not shown). generated after

Therefore, in a device operating at a very high speed machine cycle like the present embodiment, if the output of the AND circuit 10 were directly used, the delay time of the control signal would not be enough.

Therefore, in this embodiment, the output of the AND circuit 10 is supplied to the pipeline synchronization control circuit F#126, which generates a pipeline synchronization control signal, and the flip-flop (not shown) in the circuit 26 generates a pipeline synchronization control signal. After receiving the same control signal, it is supplied to each pipeline stage.

Therefore, when a cache miss occurs in request 1, the real address of request 1 has already been set in CMARl7 and MAR24 at the timing when the pipeline synchronization control signal is issued from the synchronization control circuit 26, and the real address of request 1 is already set in CMARl7 and MAR24, and subsequent request 2 The real address is PAR27
, the real address of the new subsequent request 3 is P
Each is set in AR14.

In this state, let us consider a case where the conventional technique is used to detect that request 2 misses the cache and desired data does not exist in the block data of request 1 issued previously. First, after registering the address information of request 1 in the corresponding AA3 or AA4, the real address of request 3 held in PAR14 must be saved somewhere. Then, the real address of request 2 of PAR27 is PA
R, 14 and performs re-indexing of AA3.4. When a cache miss is detected, the real address of request 2 is supplied to the main memory via PAR27 and MAR24, and then the real address of request 3 is supplied to the PA
Must be restored to Rl 4.

Also, if request 2 or catshhit is made,
Since a block transfer request cannot be made to the main memory, request 2 must restart its processing after the block transfer processing of the preceding request is completed. New request restart recovery processing is required.

In this way, the use of the conventional technology in the device of this embodiment is as follows:
This is undesirable because it requires great control complexity and a considerable amount of hardware.

According to the present invention, in this case, subsequent requests 2 and 3 can be controlled while being held in stages 2 and 3.

Next, the control operation of the present invention will be described. Now, the real addresses of subsequent requests 2 and 3 are held in PAR27 and PAR14 by the pipeline synchronization control signal, and the index results of 3 and 4 by request 2 are FF
12 and 13 are held.

First, the comparator 19 compares the out-of-block address of the real address of request 1 that previously made a block transfer request to the main memory held in the CMAR 17 and the out-of-block address of the real address of request 2 held in the PAR 27. are compared. Since the real address of request 2 does not match the block address of request 1 issued previously, comparator 19 outputs a logic O indicating a mismatch and supplies it to NAND circuit 20 . Therefore, the NAND circuit 20 outputs a logic 1 and supplies it to the AND circuit 21.

Since request 2 is a case of a cache miss, the FFs 12 and 13 that hold the index results of AA3 and 4 by request 2 each hold a logic 0, and the AND gate 10 holds a logic 0 indicating that the quiche has been missed. It outputs 1 and supplies it to Antogame 1/21. Therefore, the AND gate 21 outputs a logic 1 and outputs it to the MAR 24.

The logic 1 signal of this AND gate 21 is the request 2
This indicates that the request 1 has missed the cache and the desired data does not exist in the block data of request 1 issued previously, and the block transfer request to the main memory of request 2 is Indicates that it can be issued.

Therefore, the real address of request 2 in PAR27 is M
It is accepted at AR, 24, and a block transfer request is issued to the main memory. During the processing of block transfers for request 1 and request 2, data from DA15゜16 is not used, and block data from request 1゜2 is transferred to DA.
15 or 16, the desired data is simultaneously sent to the request source through the DAR 23.

And request 1. During the block transfer process of request 2, the address information of requests 1 and 2 is registered in the corresponding AA 3 or 4 through separate paths (not shown). While request 1 and request 2 are undergoing block transfer processing, subsequent request 3 is kept waiting in PAR14.

Note that if one comparator detects that the out-of-block addresses of CMAR17 and PAR27 match, that is, the desired data of request 2 exists in the block data of request 1 issued previously. is detected, the comparator 19 outputs a logic 1, the NAND circuit 20 outputs a logic O, and the output of the AND circuit 21 becomes a logic O. As a result, the block transfer of request 2 to the main memory The request should be sent. Then, the block data of request 1 is transferred from the main memory,
After the desired data of request 1 is sent to the request source and the block data is registered in DA 15 or 16, the DA on which this block data is registered is indexed and the desired data of request 2 is read out. , is sent to the request source. Until this processing is completed, it is treated as a series of cache miss processing.

In this way, in this embodiment, the request information of the request that previously requested a block transfer of data to the main memory is held, and the out-of-block address of this held request is compared with the out-of-block address of the subsequent request. By doing this, it is possible to extremely easily detect whether a subsequent request misses the cache and whether or not desired data exists in a block that has previously requested a block transfer of data to main memory. This allows subsequent requests held on each pipeline to be processed as they are without performing very complex control such as saving and restoring operations.

FIG. 3 is a diagram 11772 which does not show another solid line example of the present invention, and parts equivalent to those in FIG. 2 are indicated by the same reference numerals.
To explain the differences from the example in the figure, 0MR28 is a cache miss compartment register that holds cache registration compartment information for requests that have cache misses, and select 29.30
is a selector that selects between the output of FFI 2.13 and the corresponding signals of CMR, 28. These selector 29
．． The selector 22 is controlled by the output of the selector 30.

Next, the control operation of this embodiment will be described. Now, let us consider a case where the subsequent request 2 misses the cache and the desired data does not exist in the block data requested by the preceding request.

And now, due to the pipeline synchronization control signal, the real addresses of subsequent requests 2 and 3 are set to PAR2.
7 and 14, respectively, and the index result of AA3.4 based on request 2 is held in FF12.13.

First, a block transfer request is made to the main memory in advance, which is held in CMAR17. A comparator 19 compares them. Since the real address of request 2 does not match the block address of request 1 issued previously, comparator 19 outputs a logic O indicating a mismatch and supplies it to NAND circuit 20 . Therefore, the NAND circuit 20 outputs a logic 1 and supplies it to the AND circuit 21.

Since request 2 is a case of a cache miss, FF12 and FF13 that hold the index results of AA3 and 4 by Rifnis).2 each hold logic O, and AND gate 10 indicates that the cache has been missed. A logic 1 indicating this is output and supplied to the AND gate 21. Therefore, AND gate 21 outputs logic 1 and MAR2
Output to 4.

The logic 1 signal of this AND gate 21 indicates that request 2 has missed the cache and that the desired data does not exist in the block data of request 1 that was issued previously. This indicates that it is possible to issue block transfer requests to main memory in succession.

Therefore, the real address of request 2 in PAR27 is M
It is accepted by the AR 24 and a block transfer request is issued to the main memory. During the process of transferring the block data of request 1 and request 2, the output signals of FFs 12 and 13 and the AND circuit 10 are treated as invalid signals, and the DAi
Data from 5.16 is not used, request 1.2
When the block data is registered in the DA 15 or 16, the desired data is simultaneously sent to the request source through the DAR 23.

And request 1. During the block transfer process of request 2, the address information of request 1 and request 2 is registered in the corresponding AA3 or AA4. While the transfer of block data of requests 1 and 2 is being processed, the subsequent request 3 is kept waiting in the PAR 14.

Next, consider a case where the subsequent request 2 misses the cache, but the desired data is present in the block data requested by the preceding request 1. and,
Suppose now that the comparator 19 detects that the out-of-block addresses of CMAR17 and PAR27 match. That is, in this case, since the comparator 19 outputs a logic 1 and the V bit 18 outputs a logic 1, the NAND circuit 20 outputs a logic 0 and supplies it to the AND circuit 21. Then, the AND circuit 21 outputs logic 0, and as a result, request 2
A block transfer request to the main memory is not sent, and the processing of request 2 is made to wait on the PAR 27 until the processing of the block data requested by request 1 is completed.

Then, until the block data requested by request 1 is transferred from the main memory, the cache registration compartment information of the block data of request 1 determined by a cache replacement algorithm circuit (not shown) is set to 0MR28. be done. This cache registration compartment information is information consisting of 2 bits, and indicates the compartment of the cache to be written to with a logic 1, and each bit corresponds to DA15.16. Therefore, the bit combination "10" and roIJI does not exist.

When the block data requested by request 1 is transferred from the main memory and registered in DA 15 or 16, and the desired data of request 1 is sent to the request source, processing of request 2 that is waiting in PAR 27 is started. Ru.

Since the desired data of request 2 exists in request 1 or the block data requested from main memory,
That is, request 1 and request 2 have the same block address. Therefore, in request 2, DA15.
16 and the data read from DA15 or 16 of the compartment indicated by 0MR28 is
Request 2 is the desired data.

Now, the AND gate 10 is outputting a logic 1 indicating a cache miss, so the selectors 29 and 30 are outputting CM
The output of R, 28 becomes valid, and the desired data of request 2 is read out to DAR 23 and transferred to the request source. Until this request 2 is processed or finished,
It is treated as a series of cache misses being processed.

Note that when the subsequent request 2 hits the cache, the AND gate 10 outputs a logic O indicating that it hits the cache, so the output of the AND gate 21 also becomes O, and the block transfer of request 2 to the main memory is performed. The request should be sent.

Request 2 is kept waiting in the PAR 27 until the cache miss processing of request 1 is completed. During this time, the index results for AA3 and 4 of request 2 are also FF12.1
It continues to be held at 3. However, until the cache miss processing of request 1 is completed, FF12, 1
Outputs 3 and 10 are disabled for cache control.

When the block data requested by request 1 is registered in the DA 15 or 16 and the desired data of request 1 is sent to the request source, the cache miss processing of request 1 is completed and the processing of request 2 is resumed. . At this time, FF12.13 and AND gate 1
The cache control information based on 0 becomes valid, and selector 2
9.30 selects the output of FF12.13. Then, the desired data of request 2 is read out from the DA 15L or 16 to the DAR 23 and sent to the request source.

As explained above, in this embodiment, since the request information and cache registration compartment information of the request that previously requested a block transfer of data to the main memory are held, it is extremely easy to detect the status of the subsequent request. This is easy to do, and can be processed as is without very complex control such as saving and restoring subsequent requests held on each pipeline.

According to the present invention, the following request is an A-yash miss, and whether or not the desired data exists in the block that was previously requested to transfer data to the main memory. This has the effect of improving the processing performance of the system because it can be detected easily and quickly.

[Brief explanation of the drawing]

1 to 3 are block diagrams of each embodiment of the present invention. Explanation of symbols of main parts 1...Logical address register 34...Address array 5.6, 7.19...Comparator 14.27...Real Address register 15.16
... Data array 17 ... Cache miss address register 18 ... Flag register 23 ... Data array read register 24 ... Memory address register 26・・・・・・
... Pipeline synchronization control circuit 28 ... Cache miss compartment register

Claims (3)

[Claims] (1) A data processing device having a cache memory that holds a partial copy of the contents of the main memory in units of blocks, wherein when the first request is a cache miss, a holding unit that holds the request information; a comparison means for comparing an address in the request information of a second request following the first request with an address in the request information held in the holding means; and means for requesting data block transfer from the main memory in response to the second request when the comparison result of the comparing means indicates a mismatch. (2) A cache memory that holds a partial copy of the contents of the main memory in block units, a cache directory means that records a directory of the contents held in the cache memory, and a cache hit state determined based on the index result of the cache directory means. a first stage that indexes the cache directory means in response to a request; and a second stage that uses the index result to determine a cache hit state by the cache hit determination means. The data processing device employs a pipeline processing method, and includes a cache miss request holding unit that holds request information of a request for which a cache miss hit has been determined, and a cache miss request holding unit that holds request information of a subsequent request following this request. means for holding each stage, index result holding means for holding an index result of the cache directory for a request whose request information is held at the second stage, and an address in the request information held at the second stage. and a comparison means for comparing the address in the request information held in the cache miss request holding means, and the contents of the index result holding means indicate a cache miss and the comparison result of the comparison means is and means for requesting data block transfer from the main memory in response to the request held in the second stage if a mismatch is indicated. (3) A cache memory that holds a partial copy of the contents of the main memory in units of blocks, a cache directory means that records a directory of the contents held in the cache memory, and a cache hit state determined based on the index result of the cache directory means. a first stage that indexes the cache directory means in response to a request; and a second stage that uses the index result to determine a cache hit state by the cache hit determination means. A data processing device using a pipeline processing method, comprising a cache miss request holding means for holding request information of a request for which a cache miss has been determined, and cache registration compartment information for the request for which a cache miss has been determined. means for holding request information of a subsequent request following this request in each of the first and second stages; and holding an index result of the cache directory for the request whose request information is held in the second stage. index result holding means, comparison means for comparing an address in the request information held in the second stage and an address in the request information held in the cache miss request holding means;
If the contents of the index result holding means indicate a cache miss and the comparison result of the comparison means indicates a mismatch, block data is retrieved from the main memory in response to the request for which the cache miss has been determined. is read out and registered in the cache memory, and then retained in the second stage based on the address in the request information retained in the second stage and the cache registration compartment information of the request for which the cache miss has been determined. A data processing device comprising means for reading desired data of a request being made from the cache memory and sending it to a request source.