JPH0219084A - Recording and reproducing device - Google Patents

Abstract

PURPOSE:To prevent the deterioration in picture quality by varying a level of a reproducing video signal in response to the output of the 1st and 2nd low pass filters. CONSTITUTION:The device is provided with an A/D converter 2 recording a signal while inserting a reference signal to a prescribed period of each recording channel at recording and quantizing the reproduced video signal of each channel at reproduction, arithmetic circuits 15a, 15b comparing levels V1, V2 of the 1st and 2nd prescribed periods of the quantized reproducing video signal with reference levels Vr1,Vr2 respectively, the 1st and 2nd low pass filters(LPF) 16, 17 connecting the output of the arithmetic circuits 10a, 10b and a correction circuit 13 connecting to an input of the A/D converter 2 and whose reproducing video signal level is varied with the output of the 1st and 2nd LPF. Then the gain of the correction circuit is controlled so that the level of the prescribed part of the reference signal of the reproducing signal of each channel is a prescribed value. Thus, the deterioration in the picture quality is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal recording and reproducing apparatus that records and reproduces a video signal by dividing it into m channels (m is an integer of 2 or more).

BACKGROUND OF THE INVENTION In recent years, in recording and reproducing devices such as video tape recorders, in order to reduce the bandwidth required for recording and reproducing wideband signals, it has been considered to divide the wideband signals into multiple channels for recording and reproducing. There is.

For example, the video signal YI→Y2→Y as shown in FIG. 9A
, →Y4→..., and the first transmission channel has an odd line video signal (Y, →Y3→...),
The second transmission channel has an even line video signal (Y2
→Y, →...), and the time axis length is determined during recording. ),
By performing time axis compression during playback, recording and playback of wideband signals can be realized using the same transmission path as before.

Here, we are considering a time-axis expanded luminance signal as the channel-divided signal, but it is also a time-division multiplexed signal in which the chrominance signal and luminance signal are time-axis multiplexed, or a time-division multiplexed signal in which the chrominance signal and the luminance signal are frequency-multiplexed. It is clear that the same thing can be said about composite signals.

Moreover, it is clear that the same thing can be said when the number of divided channels is three or more.

Problems to be Solved by the Invention However, in the above configuration, since the video signal is transmitted over multiple transmission channels during recording and playback, there may be problems when the recording circuit and the playback circuit have different characteristics between the channels (for example, , if there is a DC level difference between transmission channels, Δ
This results in a DC level difference of (2). ), the reproduced signal had the disadvantage of causing image quality deterioration such as line crawling and line flicker.

In view of the above-mentioned problems, the present invention provides a recording and reproducing apparatus that can actively correct the characteristic difference between channels and suppress the DC level difference and gain difference between channels to below the permissible limit or detection limit. be.

Means for Solving the Problems In order to solve the above problems, the recording and reproducing apparatus of the present invention includes:
An AD converter that inserts and records a reference signal in a predetermined period of each recording channel during recording and converts the playback video signal of each channel during playback, and a first and second predetermined quantized playback video signal. Period (D level) LtV,
・V2 (V, = V2') is set to the reference level V
1=Vr1 ・Vr2 (V1=Vr1=Vr2); a first and second low-pass filter (hereinafter referred to as LPF) connected to the output of the arithmetic circuit; and the AD converter. The correction circuit is connected to the input of the LPF and changes the level of the reproduced video signal according to the outputs of the first and second LPFs.

According to the present invention, with the above-described configuration, the gain of the correction circuit is controlled so that the level of a predetermined portion of the reference signal of the reproduced signal of each channel becomes a predetermined value, so that the characteristic difference between channels (
A signal with corrected DC level difference and gain difference) is obtained.

Embodiment A recording/reproducing apparatus according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a recording section of a recording/reproducing apparatus according to a first embodiment of the present invention. In FIG. 1, 1 is an input terminal for a video signal, 2 is an AD converter that converts an analog signal into digital data, and 3 is a channel division circuit that divides the output of the AD converter into two channels and expands the time axis. . 9 is a timing generation circuit that separates the horizontal synchronization signal from the input video signal and sets the insertion period of the reference signal; 10 is a timing generation circuit that sets the level of the XI and x2 parts according to the output of the timing generation circuit 9, respectively, V1=V
This is a reference signal generation circuit that generates reference signals (shown in FIG. 3) which are r1 and Vr2. 4a and 4b are adders that add the reference signal generated from the reference signal generation circuit 10 and the output signal of the channel division circuit 3. 5a and 5b are DΔ converters; 6 is a recording signal processing circuit that converts the analog signal into a signal suitable for recording on a magnetic tape; 7a and 7b are recording heads;
8 is a magnetic tape.

With the configuration shown above, during recording, a reference signal having a level of V1=Vr1 and Vr2 is inserted at a predetermined period within a period of 2H (H: horizontal synchronization interval) as shown in FIG. Become.

Next, FIG. 2 is a diagram showing a reproduction section. In FIG. 2, lla and llb are reproduction heads, and 12 is a reproduction signal processing circuit having functions such as demodulation.

13a is LPFI (16a) and LPF2 (17b
) is a correction circuit that changes the level of the input signal according to the output of the As shown in FIG. 5, the correction circuit 13a includes an input terminal 28a, a first AGC circuit 1 (29a) that is controlled according to the level of the X1 portion of the reference signal shown in FIG. a second AGC circuit 2 (30a) controlled according to the level of the X2 portion of the reference signal shown in FIG.
1a, and input terminals 32a and 33a for control signals of the AGC circuit. 14a is an AD converter connected to the correction circuit 13a, and 15a is the AD converter connected to the correction circuit 13a.
This is an arithmetic circuit that compares the digital data output from the converter with a predetermined value. As shown in FIG.
r1 corresponds to the level of the X1 portion in FIG. 6A, and Vr2 corresponds to the level of the X2 portion of FIG. 6A. ) and an input signal, switches 23a and 24a that switch between the reference level and the output terminal of the comparison circuit 22a, and output terminals 25a and 26a. In addition, the second channel includes a correction circuit 13b, an AD converter 14b, an arithmetic circuit 15b, and a correction circuit 16b.
The same applies to the configurations of the LPFI b and the LPF2 17b. Furthermore, 18 compresses the time axis of the two-channel signals of the AD converters 14a and 14b, and
Channel synthesis circuit that synthesizes into channels, 19 is DA
The converter 20 is an output terminal.

The operation of the recording/reproducing apparatus configured as described above will be explained below using FIGS. 2 to 7.

Further, FIG. 7 is a timing chart used to explain the operation, and is a timing chart used for explaining the operation of the arithmetic circuit 15a (+5b) and LP.
7A shows the time change of the output signal of F16a (16a, 17a, +7b) (FIG. 7A shows the time change of the arithmetic circuit, and FIG. 7B shows the time change of the LPF).

In FIG. 2, consider a case where the level of the X1 portion of the reference signal at time L0 of the signal output from the reproduced signal processing circuit 12 is higher than the reference level V1=Vr1 as shown in FIG. 6A. In FIG. 6, the scale on the vertical axis shows the value in hexadecimal, and the level at V r H is 04. The reproduced signal (FIG. 6A) is converted into digital data by the AD converter 14a and input to the arithmetic circuit 15a. As shown in FIG. 4, the digital data input from the input terminal 21a is compared with the preset reference level V1=Vr1 by the comparison circuit 22.
For example, if the output of the comparator circuit 22a is configured to be at the ligh level when the input digital data is greater than the 5fp level, the output of the comparator circuit 22a is connected to the switch 24a and the output terminal 2.
The old gh level signal is supplied to the LPFI (16a) via the LPFI (16a) (period from time t0 in FIG. Figure B) is supplied to the correction circuit 13a,
AGC circuit 1 (29a) gain is controlled. The AGC circuit 1 (29a) is configured such that the gain decreases as the level of the control n signal increases, and in the above state (Fig. 6A), the gain of the AGC circuit 1 (29a) decreases. It is in. That is, the level of the X1 portion of the reference signal shown in FIG. 6A approaches the reference level,
The control '+n''iH pressure of the AGC circuit 1 (29a) also changes from ■C0 to Vc as shown in FIG. When it becomes equal to t(i g h level and Lo
wThe average leveling time becomes equal, and AGC circuit 1 (2
The control voltage supplied to 9a) is V as shown in FIG. 7B.
c Converges to 1.

That is, the level of the X1 portion of the reproduced reference signal is (reference level V1=Vr1)+0. as shown in FIG. 6B.
It will converge to the level of 5LSB.

As described above, according to this embodiment, a reference signal is inserted at a predetermined period during recording, and the levels ■1 and ■2 (V, -V2) of the reference signal during the first and second predetermined periods are adjusted during playback. Each roughly set reference level V1=Vr1
・Compare with Vr2 (V1=Vr1wVr2) after converting it to digital data, and set AD according to the comparison result.
The level of the reproduced signal is corrected by controlling the AGC circuit connected to the input of the converter. Therefore,
It becomes possible to reduce the level difference between each channel of the reproduced signal to below the permissible limit or detection limit, and it is possible to eliminate image quality deterioration such as line crawling and line flicker.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 8 is a block diagram of a correction circuit in a recording/reproducing apparatus showing a second embodiment of the present invention.

In FIG. 8, 34 is an input terminal for the reproduced video signal, 3G
37 is a photoelectric conversion element whose resistance value changes according to a control signal supplied from the control terminal 40, and a predetermined DC? A DC power source supplies f pressure, 35 is a resistor for dividing the input signal, and 39 is an output terminal.

The operation of the correction circuit configured as above will be explained.

The DC voltage of the DC power supply 37 is expressed as the reference signal X2 shown in FIG.
If the level of the X1 part of the reference signal shown in FIG. 3 and the reference level V1=Vr are set to 2,
The level of the control voltage supplied to the photoelectric conversion element 36 changes depending on the result of the comparison.

At this time, the level of the input signal Vr2 does not change, that is, when controlling the X1 part of the reference signal, it does not affect other control loops.The same applies when controlling the X2 part of the reference signal. I can say that.

As mentioned above, the level of the reference signal during the predetermined period V, ・V,
is the reference level V1=Vr1 ・Vr2, Vl
- When controlled so that V1=Vr1, the level of Vr2 is controlled so that V2=Vr2, V1=V
By configuring the correction circuit so that the level of r1 does not change, the level of the reference signal for multiple predetermined periods can be controlled simultaneously, reducing the time required to correct the characteristic difference between channels. I can do it.

Note that in the first and second embodiments, the number of recording and reproducing channels is two, but it may be three or more channels.

Further, in the first and second embodiments, the reference signal is inserted every 2H, but it may be inserted every several H or IV (V: vertical synchronization interval).

Furthermore, in the first and second embodiments, the levels of the reference signals are compared at two locations, but there may be three or more locations.

In addition, in the first and second embodiments, a luminance signal is considered as a video signal that is time-axis expanded during recording, but a time-division multiplexed signal in which a chrominance signal and a luminance signal are time-axis multiplexed, or a chrominance signal and a luminance signal The signal may be a composite signal that is frequency-multiplexed.

Further, in the second embodiment, the correction circuit 13a (13b)
Although the above uses a charging conversion element, a correction circuit configured using a transistor or the like may also be used.

Effects of the Invention As described above, the present invention includes an AD converter that inserts and records a reference signal at a predetermined period during recording, and quantizes a reproduced video signal during playback, and a first AD converter of the quantized reproduced video signal. and the level ■1 ・V2 (
v+ = V2) respectively to a predetermined value V1 = Vr1 ・
an arithmetic circuit that compares Vr2 (V1=Vr1=Vr2), first and second LPFs connected to the output of the arithmetic circuit, and outputs of the first and second LPFs connected to the input of the AD converter. The level of the reproduced signal is corrected by comprising a correction circuit that changes the level of the reproduced video signal depending on the direction. Therefore, it becomes possible to reduce the level difference between each channel of the reproduced signal to a permissible limit or a detection limit or less, and it is possible to eliminate image quality deterioration such as line crawling and line flicker.

Furthermore, if the level v1v2 of the reference signal for a predetermined period is the reference level V1=Vr1 ・V1=Vr1, ■1=
By configuring a correction circuit so as not to change the level of Vr2 when it is fitted so that it becomes 1, and the level of V1=Vr1 when it is controlled so that V2 = Vr 2, the standard Control of a plurality of signals for a predetermined period can be performed simultaneously in a short time.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are configuration diagrams showing one embodiment of the present invention,
Figure 3 is a waveform diagram of a video signal with a reference signal inserted and time axis expanded, Figure 4 is an internal configuration diagram of the arithmetic circuit, Figure 5 is an internal configuration diagram of the correction circuit, and Figure 6 is the reproduced video. FIG. 7 is a timing chart showing the signal waveform of each part in FIG. 2. FIG. 8 is an internal configuration diagram of a correction circuit in another embodiment of the present invention. FIG. FIG. 2 is a signal waveform diagram in conventional channel division recording. 3... Channel division circuit, 6... Recording signal processing circuit, 9... Timing generation circuit,
lO...Reference signal generation circuit, 12-...
Reproduction signal processing circuit, 18...channel synthesis circuit, 22...comparison circuit. Name of agent: Patent attorney Shigetaka Awano

Claims (2)

[Claims] (1) A recording and reproducing device that divides a video signal into m channels (m is an integer of 2 or more) and records/reproduces it, and when recording, inserts a reference signal at a predetermined period of each channel, records, and reproduces the video signal. An AD converter that quantizes the reproduced video signal for each channel so that the level of the reference signal of each channel sometimes becomes a predetermined value, and a level V_1 of the quantized reproduced video signal for the first and second predetermined periods.・V_2
(V_1=V_2) respectively at a predetermined reference level Vr_
1・Vr_2 (Vr_1=Vr_2), and a first and second arithmetic circuit connected to the output of the arithmetic circuit.
and a correction circuit that is connected to the input of the AD converter and changes the level of the reproduced video signal according to the outputs of the first and second low-pass filters. Recording and playback device. (2) When the correction circuit is controlled so that V_1=Vr_1, the level of the reproduced video signal Vr_2 is adjusted so that V_2=Vr_1.
Vr of the time playback video signal controlled to be r_2
The recording and reproducing apparatus according to claim 1, wherein the recording and reproducing apparatus is configured so that the level of _1 does not change.