JPH02189928A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase latch-up resistance by forming an N-type diffusion region having junction depth deeper than an anode junction and concentration higher than an epitaxial layer into the epitaxial layer. CONSTITUTION:A first conductivity type fourth impurity region 51 having junction depth deeper than the junction depth of a second impurity region 62 and concentration higher than a semiconductor region 31 is shaped to at least one part of the semiconductor region 31 between the second impurity region 62 and a channel region 61. Consequently, since the high concentration region 51 is formed to the epitaxial layer 31 between the anode junction 62 and the channel region 61, the base region of a transistor constituting a thyristor, a greater part of holes injected from an anode 102 are recombined in the high concentration region 51, and probability that the holes reach to a collector, the channel region 61, through the epitaxial layer is reduced largely. Accordingly, the current amplification factor of the transistor is lowered, and a current level where the thyristor is turned ON can be elevated largely.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor devices such as power semiconductor integrated circuit devices, and particularly to lateral insulated gate bipolar transistors (
Hereinafter, it will be referred to as LIGBT. ) The present invention relates to a semiconductor device with improved latch-up resistance.

[Prior Art] Conventionally, horizontal double diffused MO8) transistors (hereinafter referred to as LDs) have been used as high-speed switching devices used in monolithic integrated circuit devices (hereinafter referred to as ICs).
It is called MO8. ).

Since this LDMO3 is a majority carrier device,
Unlike bipolar transistors, there is no accumulation of minority carriers and they operate at very high speeds. In addition, LDMO8 is
Unlike a normal lateral MOS transistor with a symmetrical source/drain structure, a double diffusion structure is used, so it is theoretically easy to increase the breakdown voltage. However, L
Since DMO3 is a majority carrier device, it does not have the conductivity modulation effect of a high resistivity layer. Therefore, as the specific resistance of bulk silicon increases, that is, the device breakdown voltage increases, its on-resistance increases rapidly.

The on-resistance of the LDMO 5 increases at a rate approximately equal to the 2.5th power of the withstand voltage. This increased on-resistance means increased power loss, thus requiring a larger chip size for heat dissipation.

On the other hand, in order to keep the on-resistance constant, it is necessary to increase the device area. This also results in an increase in chip size.

As described above, since the LDMO8 has excellent switching characteristics or has a large on-resistance compared to a bipolar transistor, the power supply voltage for use thereof has been limited to a low voltage of 100 V or less.

As a transistor that solves these problems in the LDMO 8, there is a lateral insulated gate bipolar transistor (hereinafter referred to as LIGET) that combines field effect (MOS) operation and bipolar operation.

This LIGBT will be explained using FIG. 7.

FIG. 7 is a partial cross-sectional view showing the L IGBT.

In the figure, a heavily doped n-type buried layer 21 is formed on a p-type silicon substrate. An n-type single crystal layer is formed on the n-type buried layer 21 by epitaxial growth. This n-type single crystal layer has a p-type isolation diffusion region 42.
．． They are electrically insulated from each other by 43. As a result, an n-type epitaxial island region 31 is formed. In this n-type epitaxial island region 31, a p-type anode diffusion region 62 having a deep junction depth, which becomes a drain region (also called an anode region in this case), and a p-type back gate diffusion region 61 are formed. There is. A polysilicon film is grown on the n-type epitaxial island region 31 via the silicon oxide film 2 as an insulating film, and an n-type doped gate electrode 71 is formed by diffusing phosphorus. Using this gate electrode 71 as a mask, a p-type back gate diffusion region 81 serving as a channel region and an n-type source region 91 are formed in a self-aligned manner. After forming the silicon oxide film 2 as an interlayer insulating film, contact holes for wiring are opened.
A wiring layer made of aluminum or the like is formed. This wiring layer is formed as a source electrode 101 and an anode electrode]02.

FIG. 8A is a partial sectional view showing the cross-sectional structure of the LDMO 8, and FIG. 8B is a circuit diagram showing its equivalent circuit. In the LDMO 5 shown in FIG. 8A, an n-type drain region 95 is used instead of the p-type anode diffusion region 62 shown in FIG.
is formed.

Therefore, the resistance of the n-type epitaxial island region 31 is directly connected to the specific MOS transistor, resulting in an increase in on-resistance.

FIG. 9A is a partial sectional view showing an enlarged cross-sectional structure of the LIGBT shown in FIG. 7, and FIG. 9B is a circuit diagram showing its equivalent circuit. According to this L I GBT, the 8th A
Because the n-type drain region 95 shown in the figure has been replaced by the p-type anode diffusion region 62, the inherent MO
At the same time as current flows through the S transistor, injection of minority carriers from this anode junction into the n-type epitaxial island region 31 begins. Therefore, by modulating the resistance of this n-type epitaxial island region 31, the on-resistance is reduced.

[Problems to be Solved by the Invention] As described above, according to the LIGBT, its on-resistance can be significantly improved due to the conductivity modulation effect of the epitaxial layer due to the anode junction. However, the injection of minority carriers from the anode junction risks causing major problems in the operation of the LIGBT.

As is clear from the equivalent circuit of the LIGBT shown in FIG. 9B, the LIGBT has a built-in thyristor composed of an npn transistor Q1 and a pnp transistor Q2. npn transistor Q1 is npn
This transistor has the type source region 91 as the emitter, the p-type back gate (channel) diffusion region 61.81 as the base, and the n-type epitaxial island region 31 as the collector. p
np) transistor Q2 has a p-type anode diffusion region 62
is an emitter, the n-type epitaxial island region 31 is a base,
This is a transistor whose collector is the p-type back gate diffusion region 61.81. This built-in transistor does not normally operate because the base and emitter of the transistor Q1 are short-circuited by the source electrode 101. However, if the resistance of this short circuit is Rs, then the collector current of transistor Q2 increases and when the voltage effect across this resistance Rs reaches approximately 0.6V, transistor Q
1 turns on and this thyristor operates (latch up). Once the thyristor is turned on, current continues to flow unless the main current is turned off. As a result, in this case, the current control ability of the LIGBT gate is lost, and the LIGBT no longer functions as a switching device.

LIGBT is characterized by its low on-resistance.

In other words, LIGBT has value as a large current device. Therefore, if the upper limit of current usage is restricted due to latch-up as described above, the value as a device will be greatly reduced.

Therefore, this invention was made to solve the above-mentioned problems, and it is an insulated gate bipolar transistor that is less likely to be limited in current usage by latch-up, that is, can improve latch-up resistance. An object of the present invention is to provide a semiconductor device having the following characteristics.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor substrate, first and second impurity regions of a second conductivity type, a third impurity region of a first conductivity type, and a gate. It is equipped with an electrode. The semiconductor substrate has a main surface, and a semiconductor region of a first conductivity type is formed therein. The first and second impurity regions are formed on the main surface of the semiconductor region at a distance from each other. The third impurity region is formed within the first impurity region. The gate electrode is formed on the surface of the first impurity region sandwiched between the semiconductor region and the third impurity region with an insulating film interposed therebetween. Thereby, the surface of the first impurity region constitutes a channel region. An insulated gate bipolar transistor is configured in which the second impurity region serves as a drain and the third impurity region serves as a source. At least a portion of the semiconductor region between the second impurity region and the channel region has a first impurity region having a junction depth deeper than that of the second impurity region and a concentration higher than that of the semiconductor region. A fourth conductive type impurity region is formed.

[Operation] In this invention, a fourth impurity region having a high concentration is formed in the semiconductor region between the second impurity region and the channel region. Therefore, the drain (anode)
A large number of carriers of the second conductivity type injected from the second impurity region recombine in the fourth impurity region of the first conductivity type, pass through the semiconductor region of the first conductivity type, and form the first impurity group. The probability of reaching the region, that is, the channel region, is greatly reduced. As a result, the current amplification factor of the transistor formed by the first and second impurity regions of the second conductivity type and the semiconductor region of the first conductivity type decreases, making it possible to significantly increase the current level at which the thyristor is turned on. It becomes possible.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIGS. 1A to 1D show a LIGBT according to the present invention,
1A and 1B are partial cross-sectional views sequentially illustrating manufacturing steps of a semiconductor device including an npn bipolar transistor (hereinafter referred to as npnTR).

First, referring to FIG. 1A, n-type buried layers 21 and 22 are formed in p-type silicon substrate 1. As shown in FIG. This n-type buried layer 21,
On top of 22 an n-type epitaxial layer is grown. Thereafter, by forming deep p-type isolation diffusion regions 41, 42, 43, the n-type epitaxial layer is formed into the n-type epitaxial island region 31 electrically insulated from each other.
．． It is separated into 32 parts. In the region where the npnTR is formed, a heavily doped n-type collector diffusion region 52 with a deep junction depth is formed to reduce collector resistance. At the same time, an n-type diffusion region 51 is similarly formed in the region where the LI GBT is formed.

Next, referring to FIG. 1B, p-type impurities are diffused to form a p-type base diffusion region 63 of npnTR. At the same time, by the same diffusion process, L
High concentration p-type back gate (channel) diffusion region 6] and P-type anode diffusion region 62 constituting IGBT
is formed. Thereafter, polycrystalline silicon is formed by chemical vapor deposition or the like via a silicon oxide film 2 as an insulating film formed on the surface of the silicon substrate 1. After this polycrystalline silicon is doped with phosphorus as an n-type impurity, it is processed into a gate shape. In this way, the gate electrode 7] is formed.

Referring to FIG. 1C, by diffusing a low concentration p-type impurity, a p-type back gate (
A channel) diffusion region 81 is formed. Furthermore, by diffusing phosphorus as a high concentration n-type impurity, L
n-type source region 9 that constitutes IGBT], npnT
An n-type emitter region 92 and an n-type collector region 93 constituting R are formed.

Finally, referring to FIG. 1D, after a contact hole for wiring is opened through the silicon oxide film 2 as an insulating film, a wiring layer is formed in each region using aluminum or the like. In the figure, source electrode 1-
01, an anode electrode 102, an emitter electrode 103, a base electrode 104, and a collector electrode 105 are shown.

In this way, a semiconductor device including an L I GBT and an npn bipolar transistor is manufactured.

In this example, the depth L)n of the junction constituting the npnTR
By utilizing the process of forming the type collector diffusion region 52, the P-type anode diffusion region 6 constituting the LI GBT is formed.
An n-type diffusion region 51 with a deep junction depth on the second side is formed.

Therefore, there is no need to add a new process, which is very advantageous in terms of manufacturing costs.

As shown in FIG. 1D, in the semiconductor device according to the present invention, there is an n-type diffusion region in the epitaxial layer that has a deeper junction depth than the at junction and has a higher concentration than the epitaxial layer. By being established,
The flow of injected carriers between the anode junction and the channel region is blocked by this n-type diffusion region.

That is, in order to eliminate the limitation on the current used due to latch-up, it is sufficient to increase the on-current of the thyristor above the actual current used. Since the on-current level of the thyristor is determined by the current amplification factor of the transistors Q1 and Q2 constituting the thyristor, it is sufficient to reduce the current amplification factor of at least one of the transistors. In this invention,
A high concentration region is formed in the epitaxial layer between the anode junction and the channel region, that is, in the base region of the transistor Q2 (see Figure 9B) constituting the thyristor. This results in a large amount of recombination in the high concentration region, greatly reducing the probability that it will pass through the epitaxial layer and reach the collector, that is, the channel region. As a result, the current amplification factor of transistor Q2 becomes smaller, making it possible to greatly increase the current level at which the thyristor is turned on.

Another embodiment of the invention is shown in FIGS. 2A and 2B. FIG. 2A is a partial cross-sectional view showing a cross-sectional structure according to another embodiment of the present invention, and FIG. 2B is a partially enlarged perspective view three-dimensionally showing the structure of only the anode portion in the structure shown in FIG. 2A. be. Another embodiment of the invention will be described with reference to these figures. In this embodiment, the p-type anode diffusion region 62 is surrounded by the n-type diffusion region 5 with a deep junction depth.

This structure uses the p-type anode diffusion region 62 as the emitter and the n-type anode diffusion region 62 as the emitter.
In order to suppress the operation of a vertical parasitic pnp (pnp) transistor having the epitaxial island region 31 as a base and the p-type silicon substrate 1 as a collector, this structure also suppresses the injection of carriers toward the substrate. As shown in FIG. 2B, in this structure, by changing the mask shape for forming the n-type diffusion region 51 with a deep junction depth, an n-type epitaxial island is formed between the channel region and the anode region. It becomes possible to freely set the cut width of the high concentration n-type diffusion region 51 formed in the region 31. Therefore, p-type anode diffusion region 62, n-type epitaxial island region 31, p-type back gate diffusion region 61 .
It becomes possible to control the current amplification factor of the pnp (pnp) transistor Q2 consisting of 81 and 81 by a mask pattern. As a result, it becomes possible to optimally design the ratio between the degree of conductivity modulation of the epitaxial layer and the margin against latch-up. That is, it is possible to avoid an unnecessarily large margin for latch-up and an increase in on-resistance.

FIG. 3 is a partial sectional view showing another embodiment of the invention. In this figure, an example of a LI GBT is shown where the source is at the same potential as the substrate. In this case, since the n-type buried layer 21 is formed only directly under the anode region, the L IGBT due to the presence of the n-type buried layer
At the same time, it is possible to prevent a decrease in the withstand voltage of the anode, and at the same time, it is possible to suppress punch-through between the anode and the substrate.

FIG. 4 is a partial sectional view showing still another embodiment of the invention. In this figure, the anode region is surrounded by an n-type diffusion region 5 with a deep junction depth, excluding all the n-type buried layers.
An example surrounded by 1 is shown. In this case, the n-type diffusion region 51 formed around the anode region acts as a stopper against the extension of the depletion layer from the substrate.
A mold embedding layer is not required, and the manufacturing process can be simplified.

FIG. 5 is a partial cross-sectional view showing an example in which an n-type diffusion region 51 with a deep junction depth is formed apart from an anode region. In this case, the p-type anode diffusion region 62 and the n-type diffusion region 51
The junction breakdown voltage created by this can be improved. Further, a characteristic can be obtained that can prevent a large voltage from being applied not only in the forward direction but also in the reverse direction.

FIG. 6 is a partial cross-sectional view showing an example in which an n-type diffusion region 51 with a deep junction depth and a p-type anode diffusion region 62 are electrically short-circuited. In this case, the holes accumulated in the n-type region during forward conduction can be extracted directly from the anode electrode 102, thereby making it possible to shorten the switching time.

Note that in the above embodiment, the p-type anode diffusion region 62 of the LIGBT and the heavily doped p-type back gate (channel) diffusion region 61 are formed by the same diffusion process; There is no problem in forming the p-type anode diffusion region 62 through processing. Furthermore, the present invention is also applicable to semiconductor devices in which the conductivity types shown in the above embodiments are reversed, p-type and n-type.

Embodiments of the invention are summarized as follows.

(a) The first impurity region of the first conductivity type is formed by the same diffusion process in forming the collector region with a deep junction depth of the bipolar transistor, which is simultaneously formed in another region of the semiconductor substrate.

(b) The fourth impurity region of the first conductivity type reaches a highly concentrated buried layer of the first conductivity type formed in the semiconductor substrate.

(c) The fourth impurity region of the first conductivity type is formed so as to surround the second impurity region of the second conductivity type, and the size of the notch made in this surround allows the insulated gate transistor to be On-resistance and latch-up tolerance are controlled.

(d) The fourth impurity region of the first conductivity type is electrically short-circuited to the second impurity region of the second conductivity type.

[Effects of the Invention] As described above, according to the present invention, the current amplification factor of at least one transistor constituting the built-in thyristor can be effectively lowered, so that the latch-up resistance can be improved. become.

[Brief explanation of the drawing]

FIGS. 1A, 1B, 1C, and 1D are partial cross-sectional views sequentially showing the manufacturing process of a semiconductor device according to the present invention. FIGS. 2A and 2B are a partially sectional view and a partially enlarged perspective view showing another embodiment of a semiconductor device according to the present invention. FIG. 3 is a partial sectional view showing a third embodiment of the semiconductor device according to the present invention. FIG. 4 is a partial sectional view showing a fourth embodiment of the semiconductor device according to the present invention. FIG. 5 is a partial sectional view showing a fifth embodiment of the semiconductor device according to the present invention. FIG. 6 is a partial sectional view showing a sixth embodiment of the semiconductor device according to the present invention. FIG. 7 is a partial cross-sectional view showing the structure of a conventional lateral insulated gate bipolar transistor. FIGS. 8A and 8B are a partial cross-sectional view showing the structure of a conventional lateral double-diffused MOS transistor, and a circuit diagram showing its equivalent circuit. FIGS. 9A and 9B are a partial cross-sectional view showing the structure of a conventional lateral insulated gate bipolar transistor, and a circuit diagram showing its equivalent circuit. ]9 In the figure, ] is a p-type silicon substrate, 2 is a silicon oxide film, 31.32 is an n-type epitaxial island region, and 5] is an n-type silicon substrate.
type diffusion region, 61.81 is a p-type back gate diffusion region,
62 is a p-type anode diffusion region, 71 is a gate electrode, 91
is an n-type source region. In addition, in each figure, the same code|symbol or the same number indicates the same part or a corresponding part.

Claims (1)

[Scope of Claims] A semiconductor substrate having a main surface and on which a semiconductor region of a first conductivity type is formed; and a semiconductor substrate of a second conductivity type formed at a distance from each other on the main surface of the semiconductor region. 1 and a second impurity region, and a third impurity region of the first conductivity type formed in the first impurity region.
and a gate electrode formed via an insulating film on the surface of the first impurity region sandwiched between the semiconductor region and the third impurity region, thereby A surface of the first impurity region constitutes a channel region, and in a semiconductor device having an insulated gate bipolar transistor in which the second impurity region is the drain and the third impurity region is the source, the second impurity region A first conductor having a junction depth deeper than a junction depth of the second impurity region and a higher concentration than the semiconductor region in at least a part of the semiconductor region between the region and the channel region. A semiconductor device comprising a fourth impurity region of a type.