JPH02188010A - Differential amplifier - Google Patents

Abstract

PURPOSE:To obtain a simple, fast, and high-gain circuit by making the voltage of the collectors or drains of a transistor(TR) pair for differential input constant by the current of a current source connected in parallel to a load and a constant voltage drop obtained by 1st and 2nd resistances. CONSTITUTION:NPN Type TRs Q1 and Q2 form the TR pair for the differential input, the bases are connected to input terminals 1 and 2, and the emitters which are connected in common are connected to a source voltage VEE terminal 200 through the current source I1. Further, the collectors of the TRs Q1 and Q2 are connected to the emitters of NPN TRs Q3 and Q4. Resistances R5 and R6 are connected between the bases and emitters of those TRs Q3 and Q4 and resistances R7 and R8 are also connected between the bases and a source voltage VCC terminal 100. Those TR Q3, resistance R5, resistance R7, TR Q4, resistance R6, and resistance R8 constitute the current source.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a differential amplifier, and in particular, the present invention relates to a differential amplifier, and in particular, the present invention relates to a differential amplifier, and in particular, to a difference between the bias current of a transistor for differential input, the current flowing to a load, and the current flowing to a source other than the load. This invention relates to a differential amplifier that improves differential gain by adding sums.

(Prior Art) Conventionally, the one shown in FIG. 4 has been known as a typical differential amplifier. This differential amplifier includes differential input transistors Q1.2 whose bases are connected to input terminals 1.2. Q
2 commonly connected emitters are connected to VE through a constant current source 3.
Connect the collector to the R terminal 200 and connect the collector to the load resistance R.
1 and R2 to the vCC terminal 100 and to the output terminal 4.5. Now, the resistance values of the load resistors R1 and R2 are Re-R1-R2, the differential input transistor Q1. The mutual fundductance of Q2 is g
ll, the gain Gl of this differential amplifier is expressed by the following equation.

Gl = gs x Rc
(1) As can be seen from this equation, in order to increase the differential gain of the differential amplifier, it is necessary to increase the value of the mutual conductance gs or the load resistance value Re. However, in this configuration, when the mutual conductance gs is increased, the voltage drop in the resistive load Re increases, and the power supply voltage must be increased accordingly.

Therefore, it is known to replace the load with an active load composed of PNP transistors in order to obtain a high differential gain, but integrated circuits are usually optimized for NPN transistors, so PNP ) The frequency characteristics of transistors are worse than NPN) transistors,
The frequency characteristics of the differential amplifier deteriorate. Therefore, for high-speed circuit applications, it is common to use a resistive load instead of an active load.

On the other hand, a circuit shown in FIG. 5 has been proposed as a differential amplifier with increased gain. In this circuit, current sources 12 and 13 are respectively connected in parallel with the load resistors R1 and R2 of the differential amplifier shown in FIG. According to this circuit, the load resistance R1,
By connecting current sources 12 and 13 in parallel with R2,
Differential bare transistor Q without increasing the current flowing to the load
1. By increasing the IA current of Q2 and increasing the mutual conductance g11 in equation (1), the gain can be increased.In other words, the differential amplifier shown in FIG. 5 uses transistors Q1. A circuit has been devised in such a way that the Q2A ear current is increased to increase the amount of change in the collector current of the differential pair transistors Q1 and Q2 due to the input signal, and all of that change flows to the resistive loads Rl and R2.However, If the current source is composed of a PNP transistor, the frequency characteristics will deteriorate as described above.

FIG. 6 shows a conventional example of a differential amplifier that increases gain using the above method and operates at high speed. Note that parts that are the same as those shown above are given the same symbols. The resistive load R1 in FIG. 5 has been replaced by a transistor Q3° voltage source VBB and a resistive load R3.

The base of the transistor Q3 is connected to the voltage source VBB, the emitter is connected to the collector of the transistor Ql, and the collector is connected to the negative resistance (
, IR3 are connected to the Vcc terminal 100, respectively. Similarly, the resistive load R2 in FIG.
4. It is replaced by voltage source VBB and resistive load R4. The base of the transistor Q4 is connected to the voltage source VBB, the emitter is connected to the collector of the transistor Q2, and the collector is connected to the Vcc terminal 100 through a resistive load R4.
There is C.

This circuit has transistors Q3 and Q4 connected in cascode to transistors Q1 and Q2, respectively, and transistors Q3. By not changing the potential of the emitter of transistor Q4, the influence of the frequency characteristics of current sources 12 and 13 is removed. However, in the circuit configuration of FIG. 6, the cascode transistor Q3. A voltage source VBB is required to be applied to the base of Q4, which increases the chip area and power consumption accordingly.

(Problem to be Solved by the Invention) Conventionally, in order to increase the gain of a differential amplifier while maintaining high speed, a current source is connected in parallel with the load to supply bias current to the differential pair transistor. , a circuit is used in which the mutual conductance is increased and the collector side of the differential pair transistor is made constant voltage by a cascode transistor and a voltage source, but this configuration requires a voltage source to be applied to the base of the cascode transistor. This has the disadvantage that the chip area and power consumption increase.

The present invention has been made in view of the drawbacks mentioned above, and an object of the present invention is to provide a high-gain differential amplifier without using a voltage source for cascode transistors and without losing much of its high-speed performance.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a first
a pair of transistors, a second pair of NPN transistors cascade-connected to the collector side or the drain side of the first transistor pair, and a first transistor pair connected between the base and emitter of the second transistor pair, respectively. a second resistor connected between the base of the second pair of transistors and the first power supply terminal, and a collector of the second pair of transistors and the second power supply terminal. and loads connected to each other, and the collectors of the second transistor pair serve as output terminals.

(Function) According to the present invention, since the voltage between the base and emitter of the second pair of NPN transistors (cascode transistors) is approximately constant, the current value flowing through the first resistor is approximately constant. . Since this current is supplied as a bias current to the first transistor pair for differential input, the mutual conductance of the first transistor pair can be increased.

On the other hand, the current flowing through the first resistor connected between the base and emitter of the second transistor pair simultaneously flows through the second resistor connected between the base of the second transistor pair and the first power supply terminal. It also flows.

Here, the base current of the second transistor pair is the same as the base current of the first transistor pair. Since the current flowing through the second resistor is negligibly small compared to the current flowing through the second resistor, the current flowing through the first and second resistors is approximately equal and has a constant value. Therefore, the voltage drop across the first and second resistors becomes constant, and the potential of the collector or drain of the first transistor pair also becomes constant.

Thus, according to the present invention, the current of the current source connected in parallel with the load and the first . Since the collector or drain of the transistor pair for differential power is made constant by the constant voltage drop obtained by the second resistor,
Does not require voltage source. For this reason, a simple circuit provides high speed,
A high gain differential amplifier can be realized.

(Example) Hereinafter, the present invention will be explained in detail using the drawings. In addition,
In the drawings referred to below, parts that are the same as those shown above are given the same symbols.

FIG. 1 is a circuit diagram showing the configuration of a differential amplifier according to an embodiment of the present invention.

NPN type transistor Q 1. The transistor Q2 is a differential input transistor pair, with bases connected to the respective input terminals 1.2, and commonly connected emitters connected to the power supply voltage vEE terminal 200 via the current source 11. In addition, the collectors of the transistors Ql and Q2 are NPN transistors Ql and Q2. transistor Q
4 emitters, respectively. These transistors Q3. Between the base and emitter of transistor Q4,
Resistors R5 and Il are connected, and resistors R7 and R8 are connected between the base and the power supply voltage Vcc terminal 100, respectively. These transistors Q3. Resistor R5, resistor R7 and transistor Q4. Resistor R8 and resistor R8 constitute a current source as described later. Also, Transistoro 3. Each collector of the transistor Q4 is connected to the output terminals 4 and 5, and is connected to the power supply voltage vCC terminal 100 via resistors R9 and RIO, which are loads of the differential amplifier, respectively.
It is connected to the.

Next, the operation of the differential amplifier configured as described above will be explained. However, it is assumed that the base current of each transistor is smaller than the collector current and can be ignored, and the values of the resistive loads R9 and R10 are equal.

a. DC characteristics When the differential input voltage is 0 (v), a current of (current value of It)/2 flows through the collector of the transistor Q1. The current is divided into transistor Q3 and resistor R5. The on-voltage VBE between the base and emitter of the transistor is almost constant and does not depend on the operating current, so the current flowing through the resistor R5 is given by VBE/(resistance value of R5), and its appearance is similar to that of the transistor Q3 above. A current source is added in parallel with the emitter.

Since this current flows through resistor R7, the base potential of transistor Q3 is determined. The collector current of transistor Q3 is (current value of It)/2- (VBE/ (R5(
7) Resistance value) Nanote, base potential of transistor Q3 V6. Collector potential V4 (terminal 4) is expressed by the following equation.

V6-Vec-R7X (VBE/R5) =-(
2) V4-Vec-R9X (11/2(VBE/
R5)) -(3) However, the resistance values of R5, R7, and R9 are R5, R7, and R9, respectively.
It shall be represented by 9. Also, the base potential V7 of the transistor Q4. The collector potential v5 (terminal 5) is similarly expressed by equations (4) and (5).

V7-Vcc-R8X (VBE/RQ) -(4
)V5-Vec-RIOX (II/2-(VB
E/R8)) ・(5) However, the resistance values of R8, R8, and R10 are R6 and R8, respectively.
It shall be expressed as ゜RIO.

b, AC characteristics When the differential input voltage changes from 0 (V) to v (V), the change icl in the collector current ICI of the transistor Ql is (
6) It can be expressed as follows.

i cl : (gm /2)Xv −(6
) This current flows through transistor Q3 and impedance Z5 (
If the changes in the currents flowing through the resistors R5 and 1c3 and iz5 respectively, then equation (7) holds true.

i cl = i c3 + l z5
-(7) In general, the current characteristics of a transistor are expressed by equation (8), so the differential input terminal is
The current characteristics of transistor Q3 when (V) is (9)
It can be shown as follows.

Ic=15Xexp (VBE/Vt)...
(8) Ic3+ic3 ”Is 3Xexp ((VBEB +vbe3)/V
t)...(9) However, Is is the saturation current of the transistor, and vbe3 is the ic
3, Vt represents the thermal voltage.

Therefore, ic3 and iz5 can be expressed as in equations (10) and (11).

1c3=Ic3 XIc3/Vt −(10)i
z5 = vbe3 /R5-(11) (10) and (1
The ratio with equation 1) is as follows.

ic3/1z5=R5XIc3/Vt...(12) Here, as an example, Ic8-2(IIA)VBE-1,5
(V) (in the case of a hetero-O junction bipolar transistor), ic3/iz5≦40, and most of the signal flows to transistor Q3. Therefore, equations (7) to (13) can be approximated.

iclshiic3...13) Differential gain Gl-gmXRIoad-(14) However, Rlo
It was designated as ad-R9-RIO.

Therefore, with the above-described circuit configuration, the gain of the differential amplifier can be increased without using a voltage source for the cascode transistors.

FIG. 2 shows transistor Q3. which is part of the circuit constituting the current source. The emitter of transistor Q4 and the differential input transistor Q1. A diode D with the number of antinodes is connected between Q2 and Q2.
FIG. 2 is a circuit diagram of a differential amplifier characterized in that I1 to DIN and D21 to D2M are connected in series. This results in
Transistor Q 1. The collector of Q2 and the transistor Q3. Since the potential difference between Q4 and the base can be expanded,
It is possible to increase the values of the resistors R5 and R6 that determine the current value of the current source, and high precision of the current source can be realized. Moreover, in this case, the offset voltage can be reduced.

Figure 3 shows resistors R9 and RIO connected to current source 14, which is an active load.
, I5. With this configuration, although the frequency characteristics deteriorate, the profit margin can be made extremely high.

Each of the above embodiments has been explained using a circuit using bipolar transistors.
It is clear that the present invention can also be applied to the case where an ET (ffi field effect transistor) type active element is used. Further, in each of the above embodiments, the first power supply terminal to which the second resistor is connected and the second power supply terminal to which the load is connected are connected to the same power supply V.
Although the CC terminal is used, it goes without saying that this may be used as another power supply terminal.

[Effects of the Invention] According to the present invention, a high-speed, high-gain differential amplifier can be realized without requiring a voltage source for the cascode transistor, and by simply adding a resistor between the base and emitter of the cascode transistor. Chip area and power consumption can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a differential amplifier according to one embodiment of the present invention, FIG. 2 is a circuit diagram of a differential amplifier according to another embodiment of the present invention, and FIG. 3 is a circuit diagram of a differential amplifier according to another embodiment of the present invention. A circuit diagram of a differential amplifier according to another embodiment, and FIGS. 4 to 6 are circuit diagrams each showing the configuration of a conventional differential amplifier. 1.2...Input terminal, 4.5...Output terminal, ■1~
15-...Current source, 100-VCC terminal, 200-V
EIE terminal. Applicant's agent Patent attorney Takehiko Suzue Figure 5 Figure 6

Claims (1)

[Claims] A first transistor pair for differential input, in which a differential input signal is input to each control pole and first power supply poles are commonly connected; and a second power supply for the first transistor pair. a second pair of NPN transistors connected in series on the pole side; a first resistor connected between the base and emitter of the second transistor pair; and a first resistor connected between the base of the second transistor pair and the first resistor. a second resistor connected between the collector of the second transistor pair and the second power terminal, and a load connected between the collector of the second transistor pair and the second power terminal; A differential amplifier characterized by having a pair of collectors as output ends.