JPH02187999A - Serial access memory - Google Patents

Abstract

PURPOSE:To contrive an exact redundancy relief by adding a jump function to each pointer by a redundant fuse and a pointer switching circuit. CONSTITUTION:When a failure is generated in a pointer 80-2, a redundant fuse 81b is disconnected, and also, a fuse 81b in a redundant pointer 80-4 is disconnected. As a result, the pointer 80-2 and the pointer 80-4 become an unuseable state and a useable state, respectively. Accordingly, at the time of access, the operation is executed as the pointers 80-1 80-3 80-4 80-1, shifted by jumping the pointer 80-2, and the redundancy use pointer 80-4 is used instead of the pointer 80-2. In such a way, by adding in advance a part of the redundancy use pointer 80-4 and only disconnecting the fuse 81b, a redundancy relief can be executed simply and exactly.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a serial access memory that performs serial access to data by specifying an address using a pointer, and in particular to a serial access memory in which a jump function for resolving defects is added to the pointer. It's about memory.

(Prior Art) Conventionally, various types of serial access memory for serially writing and serially reading data have been proposed, as described in Japanese Unexamined Patent Publication No. 175294/1983. An example of the configuration is shown in FIG.

FIG. 2 is a circuit diagram of a main part of a conventional serial access memory.

This serial access memory includes a plurality of complementary bit lines 11a and 11a connected to a memory cell array (not shown).
llb, 12a-12b, 13a-13b... pairs. In FIG. 2, only three bit line pairs are shown to simplify the explanation. Each bit line 11a・
llb to 13a and 13b are turned on by the register transfer signal RTS.

Transfer gates 21a and 21b to 2 to be turned off
3a, 23b, and transfer gates 31a, 31b
~33a and 33b, a complementary data bus 35a
, 35b. Each transfer gate 21
a.31a.

Between each pair of bit lines 11a/llb to 13a-13b between bit lines 21b/31b to 23a-33a and 23b/33b, a register 40- is made up of an inverter 41.42.
1 to 40-3 are connected to each other. In addition, a plurality of pointers 50- for register selection connected in a ring shape are provided.
1 to 50-3 are provided, and each pointer 50-1 to 50-5 is provided.
The outputs 550-1 to 530-3 of 03 are connected to each inverter 5.
5-1 to 55-3 and 2-person NOR gates 56-1 to 5
Transfer gate 31a-Blb through 6-3
33a and 33b, respectively. Each NOR gate 56-1 to 56-3 is turned on and off by register selection signal φDY. Each pointer 50-
1 to 50-3 are N-channel MOS transistors (hereinafter referred to as NMO3>51.53) which are turned on and off by complementary control signals λ and A, and an inverter 52.5.
They are each made up of 4.

FIG. 3 is a signal waveform diagram of the control signals A, λ and pointer outputs 550-1 to 550-3 in FIG. 2, and the operation of FIG. 2 will be explained with reference to this diagram.

When reading data stored in a memory cell array (not shown) through pairs of bit lines 11a, llb to 13a, 13b, the register transfer signal RTS is at a low level (hereinafter referred to as "LI+").
) to a high level (hereinafter referred to as "H"), and the transfer gates 21a, 21b to 23a, 23b
is turned on, and each bit line 11a, llb to 13a, 13
The data on the b pairs are transferred and held in each register 40-1 to 40-3 in parallel. Register selection signal φDY is “
From H to Ln, the outputs 5501 to 550-3 of each pointer 50-1 to 50-3 become j by the control signals A and A.
: When it comes to the term II HII, the inverters 55-1 to 55-5
5-3 and NOR game) through 56-1 to 56-3,
Each transfer gate 31a, 31b to 33a, 33
Pair b turns on sequentially, registers 40-1 to 40-3
The data therein is serially read out to data buses 35a and 35b.

In the case of writing, write data is transferred to data buses 35a and 35a.
5b to each register 40-1 to 40-3, and then bit lines 11a, llb to 40-3.
The data are written in parallel to the memory cell array via the pair 13a and 13b.

(Problems to be Solved by the Invention) However, the memory having the above configuration has the following problems.

(a) If a certain pointer 50-1 to 50-3 is defective, since they are connected in a ring,
All pointers 50-1 to 50-3 stop working and cannot be repaired.

(b) Certain registers 40-1 to 40-3,
Alternatively, if a memory cell connected to a bit line is defective, it is possible to repair the defective location by providing a redundant register or redundant memory.
It is necessary to provide a counter to know the position of the redundant switch, a control circuit for redundant switching, etc., which complicates the control during redundant switching, and it is difficult to solve these problems simply and accurately.

The present invention provides a serial access memory cell that solves the problems of the prior art, such as the pointer failure making it impossible to repair, and the complexity of redundancy relief measures when a register or memory cell is defective. It is something to do.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a memory cell array connected to a plurality of bit lines, and a transfer gate between each of the bit lines and a data bus. In a serial access memory that includes a plurality of connected registers for holding data and a plurality of pointers that shift based on a control signal and sequentially select each of the registers via the transfer gate, there is a redundancy system for relieving defects. Each pointer is provided with a fuse and a pointer switching circuit that short-circuits the shift signal path of the pointer when the redundant fuse is disconnected.

(Function) According to the present invention, since the serial access memory is configured as described above, when a pointer or the like is defective, if the redundant fuse of the pointer at the defective point is cut off, the pointer switching circuit is activated to remove the pointer at the defective point. The time between input and output of a pointer is shortened, and each pointer before and after the pointer is directly connected.

As a result, at the time of access, register selection is performed by skipping over the pointer of the defective location. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a main part of a serial access memory showing a first embodiment of the present invention.

This serial access memory has a memory cell array 60, which has a plurality of word lines 61-1, 61-2,
. . . and a plurality of complementary bit lines 62-1a=62-1
b, 62-2a/62-2b, 62-3a/62-3b
and a plurality of memory cells 63 connected to each word line and bit line pair. In FIG. 1, for ease of explanation, out of a plurality of bit line pairs,
Three pairs of bit lines 62-1a, 62-1b to 62-3a
, 62-3b pair only is shown. Each bit line 62-
The pairs 1a, 62-1b to 62-3a, 623b are turned on by the register transfer signal RTS.

Transfer gate 65 consisting of NMO8 in off-operation
-1a, 65-1b to 65-3a, 65-3b, and transfer gates 66-1a, 66-1b to 66-
3a, 66-3b, a complementary data bus 67a.
, 67b.

Each transfer gate 65-1a and 66-1a.

65-1b/66-1b ~65-3a-663a, 6
Each bit line 62-1a between 5-3b and 66-3b
-62-1b to 62-3a to 62-3b, registers 70-1 to 70-3 each including inverters 71 and 72 connected in antiparallel are connected, respectively. A plurality of pointers 80-1 to 80-3 for selecting these registers 70-1 to 70-3 are connected in a ring shape.

Each pointer 80-1 to 80-3 is an NMO 38 which is turned on and off by complementary control signals λ and A as in the conventional case.
1a, 83a, inverters 82a, 83a, redundant fuse 81b newly provided in this embodiment, NMO8
82b, 86b, inverters 83b, 84b, and P-channel type MOS transistor (hereinafter referred to as PMO8)
85b. NMO 381a is connected to the output side of pointer 80-3 at the previous stage.

This NMO881a has an inverter 82a, an NMO38
3a and an inverter 84a are connected in series, and a pointer output 380-1 is sent out from the inverter 84a. A pointer switching circuit is connected to the redundant fuse 81b connected to the power supply potential Vcc. The pointer switching circuit includes NMO882b, 86b, and inverter 83b.
.

84b and PMO385b, its NMO8
82 is connected between redundant fuse 81b and ground potential Vss, and inverters 83b and 84b are connected in series to NMO 382. Redundant fuse output 584b-1 from inverter 84b connects PMO 385b and NMO 88
6b and its PMO885b and N
MO386b is 1. A feedback connection is made between the pointer output 580-1 and the pointer input.

Output S80-1 to 58 of each pointer 80-1 to 80-3
0-3 and redundant fuse outputs 584b-1 to 584b-3
are connected to the two-man power NAND gates 90-1 to 90-3, respectively, and the NAND gates 90-1 to 90-3 are connected to each other.
The output of the register selection signal φDY is connected to two-man power NOR gates 91-1 to 91-3, respectively. The output of each NOR gate 911 to 91-3 is the output of each transfer gate 66-1a, 66-1b to 66-3a, 66-
3b, respectively.

Next, (i) normal operation without a cause of failure and (ii) operation at the time of relief from failure will be explained.

(1) Normal operation without cause of failure If there is no cause of failure, each pointer 80-1 to 80-3
Do not cut the redundant fuse 81b inside.

In this case, within each pointer 80-1 to 80-3,
The input of the inverter 83b is “IIH”, and its output is “°
Because of the low voltage, the redundant fuse output 5 of each inverter 84
84b-1 to 884b-3 are "Hll, 1MO885
b is off and NMO886b is on. Therefore, the output 580-1 of pointer 80-1 is
-2, the output 580-2 of pointer 80-2 is input to pointer 80-3, and the output 580-2 of pointer 80-3 is input to pointer 80-3.
0-3 are respectively connected to the input of pointer 80-1.

When reading data stored in the memory cell array 60, one of the word lines, for example 61-1, is selected by a row address decoder (not shown), and the data of the memory cells 63 in the column direction connected to the word line 61-1 are read. Each bit line 62
-1a, 62-1b to 62-3a, 62-3b appear above.

When the register transfer signal RTS changes from “Lu” to “H”,
Transfer gates 65-1a, 65-1b ~65-
3a, 65-3b are turned on, each bit line 62-1a, 6
The data above for pairs 2-1b to 62-3a and 62-3b are
The data is transferred and held in registers 70-1 to 70-3 in parallel. Register selection signal φDY changes from “Hll to II L”
II, each pointer 80 is controlled by control signals A and λ.
When the outputs 580-1 to 580-3 of -1 to 80-3 become "H°" around j, the NAND gates 90-1 to 90-3
and each transfer gate 66-1a, 66-1b to 66-3a through NOR gates 91-1 to 91-3.
, 66-3b are sequentially turned on, and the register 70-1
The data in ~70-2 is serially transferred to the data bus 67a,
67b.

In the case of writing, write data is transferred to data buses 67a, 6
7b and transfer gates 66-1a, 66-1b
~ Each register 70-1 via 66-3a and 66-3b
~70-3 are stored serially. Each register 70
When data is stored in -1 to 70-3, the register transfer signal RTS changes from "L" to "H" and all transfer gates 65-1a, 65-1b to 65-3a, 65-
3b is turned on, and the data in each register 70-1 to 70-3 is transferred to the bit lines 62-1a, 62-1b to 62-3a,
Transferred to pair 62-3b. Bit line 62-1a, 6
The data on the pairs 2-1b to 62-3a and 62-3b are written in parallel to the memory cells 63 in the column direction connected to the selected word line, for example 61-2.

(ii) Operation when resolving a defect For example, if pointer 80-2 is defective or register 7
0-2 or the memory cell 63 on the bit line pair 62-2a, 62-2b is defective, these cannot be used, so only the pointer 80-1.80-3 is used, so the pointer 80-2 Cut the redundant fuse 81b inside.

As a result, the input of the inverter 83b becomes "M+" and its output becomes "Hll", and the redundant fuse output 584b-2 of the inverter 84 becomes "L". Redundant fuse output 5
When 84b-2 becomes "L'°, 1MO885b is turned on, NMO386b is turned off, and the input of pointer 80-2 is connected to the input of the next stage pointer 80-3 through PMO385b. Also, the NAND gate 90-
The output of 2 is "H", and the output of NOR game) 91-2 is "H".
Since it becomes Lll, the transfer gate 66-2a.

66-2b is turned off and register 70-2 is not selected.

Therefore, when accessing the memory cell array 60, the pointer 80-2 is skipped and the pointers 80-1 and 80-1 are accessed.
This is done at points 0-3. As a result, pointers 80-1 and 80-3 that have no cause of failure can be repaired.

In the above description, a case has been described in which the defective pointer 80-2 is not used, but it is also possible to replace the defective pointer 80-2 with a redundant pointer. An example is shown in FIG.

FIG. 4 is a circuit diagram of a main part of a serial access memory showing a second embodiment of the present invention, and the same elements as those in FIG. 1 are given the same reference numerals.

In this serial access memory, pointer 8 in FIG.
In addition to the points 0-1 to 80-3, a pointer 80-4 for redundant replacement is added. That is, the pair of bit lines 62-4a, 62-4b connected to the redundant memory cells are connected to the transfer gates 65-4a, 65-4b, 66.
-4a-66-4b via data bus 67a, 67b
It is connected to the. Transfer gate 65-4a/6
A register 70-4 consisting of inverters 71 and 72 is connected between 6-4a, 65-4b and 66-4b. A redundant pointer 80-4 for selecting the register 70-4 is connected between pointers 80-3 and 80-1, and the output 580-4 and redundant fuse output 584b-4 of the pointer 80-4 are connected between the pointers 80-3 and 80-1. , transfer gate 66 via NAND gate 90-4 and NOR gate 91-4.
-4a and 66-4b. The redundant pointer 80-4 is the same as the other pointers 80-1 to 80.
-3 has almost the same circuit configuration, only PMO385b
is NMO8185b, NMO386b is PMO318
The only difference is that each is replaced with 6b.

FIGS. 5(a) and 5(b) are explanatory diagrams of the operation of FIG. 4, and FIG. 5(a) shows the state when redundant use is not used, and FIG. 5(b) shows the state when redundant use is performed.

In Figure 5 (a>), if there is no pointer quality, etc.
Each pointer 80-1 to 80-3 and redundant pointer 80
- Do not cut the fuse 81b in 4. In this case, in the redundant pointer 80-4, as shown in FIG.
-4 becomes II Hl+, NMO8185b turns on,
PMO8186b is turned off. Therefore, the input and output of the redundant pointer 80-4 are short-circuited via the NMO 3185b, and the redundant pointer 80-4 becomes unused.

In FIG. 5(b), for example, if a defect occurs in the pointer 80-2, the redundant fuse 81b in the pointer 80-2 is cut off, and the redundant fuse 81b in the pointer 80-2 is cut off.
The redundant fuse 81b in 4 is also cut off. As a result, the pointer 80-2 is in an unusable state, and the redundant pointer 80-2 is in an unusable state.
4 becomes available for use. Therefore, at the time of access, the operation is as follows: pointer 80-1 → 80-3 → 80-4 → 80-1, the pointer 80-2 is skipped and shifted, and the redundant pointer 80 replaces the pointer 80-2.
-4 will be used.

In this second embodiment, simply by adding the redundancy pointer 804@place and cutting the redundancy fuse 81b,
Redundancy relief can be performed easily and accurately.

Note that the present invention is not limited to the illustrated embodiment; for example, transfer gates 65-1a, 66-1a, 65-1b
-66-1b ~65-4a, 66-4a, 65-4
b - Configure 66-4b with other transistors such as PMO8, configure registers 70-1 to 70-4 with other circuit configurations, or configure pointer switching circuits in pointers 80-1 to 80-4 with other transistors. Various modifications are possible, such as using transistors and other circuit configurations.

(Effects of the Invention) As described in detail above, according to the present invention, each pointer is provided with a redundant fuse and a pointer switching circuit, and a jump function is added to each pointer, so that it is possible to simply disconnect the redundant fuse. , redundancy relief for defective registers and memory cells can be easily and accurately performed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a serial access memory showing the first embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional serial access memory, Fig. 3 is a signal waveform diagram of Fig. 2, and Fig. 4 is a circuit diagram of a conventional serial access memory. FIG. 5(a) is a circuit diagram of a serial access memory showing a second embodiment of the present invention. (b) is an explanatory diagram of the operation of FIG. 4. 60... Memory cell array, 61-1.61-
2...Word line, 62-1a, 62-1b ~
62-4a, 62-4b...Bit line, 63.
...Memory cell, 65-1a-65-1b ~6
5-4a/65-4b, 66-1a/66-1b ~6
6-4a, 66-4b...Transfer gate, 67 a, 67 b---Data bus, 70
-1 to 70-4...Register, 80-1 to 80
-3... Pointer, 80-4... Redundant pointer, 81b... Redundant fuse.

Claims (1)

[Claims] A memory cell array connected to a plurality of bit lines, a plurality of registers for holding data connected between each of the bit lines and a data bus via transfer gates, and a control signal. A serial access memory comprising a plurality of pointers that sequentially select each of the registers via the transfer gate by performing a shift operation based on the transfer gate, comprising: a redundant fuse for defect relief; and a signal for shifting the pointer when the redundant fuse is disconnected. A serial access memory characterized in that each pointer is provided with a pointer switching circuit that short-circuits a path.