JPH0218791A - Non-volatile memory control circuit - Google Patents

Abstract

PURPOSE:To reduce frequency to execute writing and to guarantee the service life of a non-volatile memory by executing the writing with new information to the non-volatile memory only when a device power source is turned off. CONSTITUTION:When the power source is inputted, a non-volatile memory 1 can executed the reading of the stored information and can execute the writing with the new information by selecting a writing mode. Even when the power source is turned off, this non-volatile memory 1 can continuously keep the stored information. Thus, the frequency to execute the writing can be reduced and the enough service life can be guaranteed for the non-volatile memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile memory control circuit, and particularly to a nonvolatile memory control circuit that controls a nonvolatile memory that can be written with new information.

[Conventional technology]

Traditionally, the non-volatile memory of microprocessor systems has been RAM with battery backup or EEPROM, which is a non-volatile memory to which new information can be electrically written, and it retains memory even when the power is turned off. The microprocessor writes and stores the information needed to do what it is doing.

[Problem to be solved by the invention]

However, the RA that performs the former battery backup
The above-mentioned conventional non-volatile memory using M has the drawbacks of having a limited battery life and being laborious and expensive to maintain.

Furthermore, conventional non-volatile memory using the latter EEPROM has a drawback that the number of times it can be written is limited, and if the microprocessor writes too frequently, it becomes unusable.

An object of the present invention is to write new information into a nonvolatile memory such as an EEPROM only when the device power is turned off, thereby reducing the number of writing operations and ensuring a sufficient lifespan for the nonvolatile memory. An object of the present invention is to provide a nonvolatile memory control circuit that can perform

[Means to solve the problem]

The nonvolatile memory control circuit of the present invention has the following features: (A> When the power is turned on, stored information can be read and new information can be written, and even when the power is turned off, the stored information can be stored.) (B) A non-volatile memory that can continuously store the data; (C) a memory evacuation signal for detecting power-off and evacuation of the contents of the volatile memory in the microprocessor system to the nonvolatile memory; and a memory save signal generation circuit which supplies power to operate the nonvolatile memory at least until the save operation is completed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a nonvolatile memory control circuit of the present invention.

The nonvolatile memory 1 in FIG. 1 is an EEPROM, and when the power is turned on, the stored information can be read out, and new information can be read out by selecting the write mode. can be written by.

Furthermore, the nonvolatile memory 1 can continue to store stored information even when the power is turned off.

On the other hand, the microprocessor system 2 is
R corresponds one-to-one to nonvolatile memory 1, which is ROM.
, AM, and after turning on the power, sends an address signal a and a control signal C to the volatile memory 1, reads out the contents of the nonvolatile memory 1,
It receives the data signal and writes it into the volatile memory 2-1, and executes program processing using the contents of the volatile memory 2-1.

In addition, the power supply operation detection circuit 3 detects the rise of the constant voltage Vcc when the device is powered on, and the constant voltage y when the device is powered off.
quickly detects the fall of cc and generates a power supply operation detection signal d that rises and falls respectively,
The signal is sent to the microprocessor system 2 and memory save signal generation circuit 4.

FIG. 2 is a circuit diagram showing an example of the power supply operation detection circuit 3.

Further, FIG. 3 is a time chart showing the operating waveforms of each signal.

In FIG. 2, the Zener diode D1 is used to set the reference voltage VRsr□ for generating the power supply operation detection signal d, and as shown in FIG. Voltage V cc is reference voltage V
Until Rer2 is exceeded, the Zener diode D1 is off, and the ground potential is applied to the base of the transistor Q2 through the resistors R4 and R5, so the transistor Q2 is turned off. The same V. . is applied, the transistor Q1 is also turned off, and the power supply operation detection signal d becomes the ground potential through the resistor R3.

Also, when the device is powered on, the constant voltage V c (H is the reference voltage V
Beyond R@y2, Zener diode D1 and )−
Transistor Q2 is turned on and V cc is applied to resistors R1, R
Since it is divided by 2, transistor Q1 is also turned on,
The power supply operation detection signal d quickly rises to a positive potential.

On the other hand, as shown in FIG. 3, when the device is powered off by turning off the power switch, a constant voltage ■ is applied. . is the reference voltage VRe
When the voltage drops below r2, the power supply operation detection signal d quickly falls to the ground potential.

Therefore, when the device power is turned on, the microprocessor system 2 uses a constant voltage V that is supplied for circuit operation.
The initialization operation can be performed by detecting that the power supply operation detection signal d rises when cc rises.

Next, the memory save signal generation circuit 4 detects that the power supply operation detection signal d falls prior to the fall of the constant voltage VDD supplied for circuit operation when the device power is turned off, The memory save suppression signal e can be quickly lowered.

Therefore, the memory evacuation signal generation circuit 4 suppresses the memory evacuation operation of the nonvolatile memory 1 while the device is in operation from the time the device is powered on, by sending the memory evacuation suppression signal e to the nonvolatile memory 1. Since the memory evacuation suppression signal e is quickly lowered at the time of disconnection, this fall of the memory evacuation suppression signal e means a memory evacuation signal.

Furthermore, the memory save signal generation circuit 4 saves the constant voltage VRAM operated by the nonvolatile memory 1 to the nonvolatile memory until at least the save operation for saving the contents of the volatile memory 2-1 in the microprocessor system 2 is completed. 1 and 2.

Therefore, the non-volatile memory 1 detects the fall of the memory evacuation suppression signal e in a state where the write mode for writing new information is selected by the control signal C from the microprocessor system 2. The microprocessor system 2 sends the control signal C to the processor system 2, receives the address signal a, the data signal S, and the control signal C from which the microprocessor system 2 has read the contents of the volatile memory 2-1, and writes new information to be saved. It can be performed.

FIG. 4 is a circuit diagram showing an example of the memory save signal generation circuit 4.

As shown in FIG. 4, the constant voltage circuit Z1 has a high constant voltage V
DD is supplied, and a constant voltage of 8 AM is supplied to the memory save signal generation circuit 1.

In addition, the Zener diode D2 is connected to the memory evacuation suppression Shingetsu (
Reference voltage Vyu1 for generating knowledge3. It is for setting
As shown in Figure 3, until the constant voltage VDD exceeds the reference voltage VR,r+ when the device is powered on, the Zener diode D2 is off, so the resistor R is connected to the base of the transistor Q4.
Since the ground potential is applied through 8 and R9, the transistor Q4 is turned off, and as a result, the transistor Q4 is turned off.
Since the constant voltage VRAM is supplied to the base of the resistor R7 through the resistor R7, the transistor Q3 is turned on, and the memory save suppression signal e is supplied with the power supply operation detection signal (a) through the resistor R6, and the power supply operation detection signal ( ” becomes a positive potential.
), but it remains at ground potential.

Also, constant voltage V when the device is powered on. D is the reference voltage VFL
When ar+ is exceeded, the Zener diode D2 and the transistor Q4 are turned on and the transistor Q3 is turned off, so that the memory save suppression signal e is supplied with the positive potential of the power supply operation detection signal d through the resistor R6.

On the other hand, when the device power is turned off, as shown in FIG. 3, the power supply operation detection signal d quickly changes from a positive potential to a ground potential, so that the memory save suppression signal e also quickly changes from a positive potential to a ground potential.

Next, the overall operation of this embodiment will be explained.

First, when the device power is turned on, the microprocessor system 2 detects that the power supply operation detection signal d rises and performs an initialization operation.

On the other hand, in the nonvolatile memory 1, the write mode is not selected in the initial state, so when the constant voltage □ is supplied, reading is possible but writing is not performed.

Therefore, the microprocessor system 2 reads the contents of the nonvolatile memory 1, writes them to the volatile memory 2-1, and executes program processing using the contents of the volatile memory 2-1.

When new data is written to the volatile memory 2 - 1 during program processing, the microprocessor system 2 selects a write mode for the nonvolatile memory 1 .

However, since the memory save suppression signal e of the memory save signal generation circuit 4 has risen, the memory save operation is not performed and is suppressed.

Finally, when the device power is cut off, the memory evacuation suppression signal e of the memory evacuation signal generation circuit 4 quickly falls;
The nonvolatile memory 1, which has become capable of memory saving operation, immediately saves the contents of the volatile memory 2-1 sent from the microprocessor system 2.

As described above, the nonvolatile memory control circuit of this embodiment performs writing by writing new information into a nonvolatile memory such as an EEPROM only when the device power is turned off. By reducing the number of times, it is possible to guarantee a sufficient lifespan of the nonvolatile memory.

As a result, the non-volatile memory control circuit of this embodiment can use non-volatile memory such as EEPROM to store constantly changing information in a microprocessor system, without using battery-backed RAM. I can do it.

〔Effect of the invention〕

As explained above, the nonvolatile memory control circuit of the present invention reduces the number of times writing is performed by writing new information into a nonvolatile memory such as an EEPROM only when the device power is turned off. This has the effect of ensuring a sufficient lifespan for the nonvolatile memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the nonvolatile memory control circuit of the present invention, FIG. 2 is a circuit diagram showing an example of a power supply operation detection circuit, and FIG. 3 is a time chart 1 showing the operation waveforms of each signal.・, FIG. 4 is a circuit diagram showing an example of a memory save signal generation circuit. DESCRIPTION OF SYMBOLS 1... Nonvolatile memory, 2... Microprocessor system, 2-1... Volatile memory, 3... Power supply operation detection circuit, 4... ...Memory save signal generation circuit, a...Address signal,
b...data signal, C...control signal,
d...Power supply operation detection signal, e...Memory save suppression signal, Di, D2...Zena diode, Ql, Q2. Q3. Q4...Transistor, R1, R2, R3, R4, R5, R6゜R7, R8,
R9-Resistance, Vcc, VDD, VRAM
・・・・・・Constant voltage, V Refl, V Rer2・
...Reference voltage, zl... Constant voltage circuit.

Claims (1)

[Claims] (A) When the power is on, stored information can be read and new information can be written, and even when the power is turned off, the stored information can be continued. (B) has a built-in volatile memory, reads the contents of the nonvolatile memory and writes it to the volatile memory after turning on the power, and programs using the contents of the volatile memory; a microprocessor system that executes processing; (C) detecting that power is cut off and sending a memory save signal to save the contents of the volatile memory in the microprocessor system to the nonvolatile memory; A nonvolatile memory control circuit comprising: a memory save signal generation circuit that supplies power to operate the nonvolatile memory until the save operation is completed.