JPH02187824A - Digital signal processor - Google Patents

Abstract

PURPOSE:To efficiently perform a branch processing by constituting a system so that the comparison processing of specific data with plural threshold values can be performed in parallel with an arithmetic processing and plural branch destinations can be designated corresponding to compared results. CONSTITUTION:A data judging apparatus performs the comparison of size relation of each of (n) threshold values set in advance as data targeted to be compared inputted from an arithmetic part via an output bus and supplied from a threshold value register group 15 by a comparator 17. And the apparatus judges the data area of targeted data by a conditional judging apparatus 19 based on (n) compared results supplied via the output bus 18. Plural branch destination addresses corresponding to each condition are stored in an address register file 24, and a branch destination address is outputted to the output bus 14 based on an address index signal supplied from the judging apparatus 19. A control circuit sets a program count value based on the address value of the branch destination address. Also, when all conditions are not satisfied at all, the count value of a program counter shows the next instruction address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processor.

[Conventional technology]

FIG. 7 shows, for example, IEEE, ICASSP86, P2O
3"A 50ns FLOATINGPOINT
5IGNAL PROCESSORVLSl” (hereinafter referred to as D
(abbreviated as SP), and in the figure, (1)
is a program memory, (2) is a control circuit that controls data transfer, arithmetic, branching, etc., (3) is an output bus that outputs control signals from the control circuit (2), and (4) is a control circuit (2).
) to the program memory (1), (5) is the output bus from the program memory (1) to the control circuit (2), (6) is the data memory, (7) is a multiplier, an arithmetic unit, An arithmetic section having a shifter, an accumulator, etc., (8) a data transfer bus, and (9) an output bus from the data memory (6) to the data transfer bus (8) and from the data transfer bus to the arithmetic section (7). , (10) are connected from the calculation unit (7) to the data transfer bus (8) and from the data transfer bus to the data memory (6).
).

Next, the operation will be explained. The basic operation of the DSP is controlled by a control circuit (2) according to a program read from a program memory (1), and includes instruction fetch, which is performed by inputting data read from a data memory (6) to an arithmetic unit (7). It consists of a series of processing operations: decoding, data reading, computation, and computation result writing.

By executing these in the vibe line processing, when the same instruction is executed continuously, the execution rate approaches that of one machine cycle per instruction. Therefore, in a process in which a single instruction is repeatedly executed, the processing speed increases as the instruction is executed continuously.

However, in a program that skips the currently executing process and branches to another process when a certain condition is satisfied based on the calculation result, before the continuous execution process ends to determine the condition, It is necessary to provide an intermediate checkpoint in the middle, interrupt continuous execution, compare certain operation result data with a specific data value, and perform branch processing based on the result.

FIG. 8 shows a processing flow in which an intermediate check is performed during a series of continuous execution processing, in which the result of the arithmetic processing is compared with a threshold value (step 5T8-1.8-2), and then, whether or not the cancellation condition is satisfied is shown. Step 5T8-3), Y
If ES, the process ends; if No, it is determined whether the final data has ended or not (Step 5T8-4); if No, the process returns to Step 5T8-1 and the above operation is repeated;
If YES, the process ends.

In motion compensation processing in image coding systems, absolute difference value accumulation is used to match between patterns, and the minimum pattern is detected. For example, if the value currently being accumulated exceeds the minimum value, The remaining accumulation is wasted;
In such cases, it is more efficient to move to the next routine.

It is useful to perform intermediate checks for this purpose, but
This involves interruption of processing and loss of processing time due to comparison/judgment. In addition, conventional DSPs can only make conditional judgments based on whether the data is positive or negative, and in order to determine the magnitude relationship with specific threshold data, first subtract the target data from the threshold. Processing efficiency is low because judgment is made based on results.

If there are multiple types of thresholds to be compared, the processing efficiency will further decrease. For example, in a case where the types of processing are divided into multiple types (n) depending on the range of data, comparisons with (n-1) thresholds and branch instructions based on the results are required, and at least (n-1) 1) It will involve a loss of X2 machine cycles.

[Problem to be solved by the invention]

Conventional digital signal processing processors are configured as described above, so in cases where branch processing is performed based on arithmetic results or intermediate results, if continuous processing is in progress, one-step processing is interrupted and subtraction and comparison processing is performed. Therefore, there was a problem that processing efficiency decreased.

This invention was made with the aim of solving the above-mentioned problems, and even in the middle of a series of continuous processing, comparison processing is executed without interrupting the continuous processing, and efficient branching processing is realized. The object of the present invention is to obtain a digital signal processing processor that can perform the following steps.

[Means to solve the problem]

The digital signal processing processor according to the present invention includes a control circuit including a program counter for controlling the address of instructions to be fetched, a data memory for data input/output, and an arithmetic unit output in the arithmetic unit in parallel with the operation of the arithmetic unit. , select either the logical shifter output or the multiplier output,
Simultaneously compare the magnitude relationship with n preset thresholds (n is an integer of 1 or more) for the selected output data,
Based on the n comparison results, it is determined in which area the output data exists among the data areas divided into (n+1) pieces by the n thresholds, and a preset value is set based on the determination result. m pieces (m
is an integer greater than or equal to 1).
If the conditions match, output the branch destination address information corresponding to the matched area limiting condition from among the m branch destination addresses preset corresponding to the m area limiting conditions, and The device is equipped with a data determiner that outputs a signal indicating that all conditions do not match when all conditions do not match.

[Effect]

The data determiner in this invention performs parallel comparison processing with multiple thresholds on the multiplier output every machine cycle, and selects a specific branch destination from among the multiple branch destinations in response to the comparison result. By selecting this option, comparison and judgment are always performed without interrupting continuous processing, making it possible to efficiently control complex branching processing.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same or corresponding parts as those in FIG. 7 are given the same reference numerals, and redundant explanation will be omitted.

(11) is a data judger, (12) is a data transfer bus (
8) and the data determiner (11), an input/output bus (13)
) is an output bus from the arithmetic unit (7) to the data determiner (11).

FIG. 2 is a block diagram showing the internal configuration of the data determiner (11). In FIG. A comparator for comparison, (19) is a condition determiner that determines the area of operation data based on the comparator output and compares it with the branch condition, and (20) holds address index information indicating the branch condition and its branch destination. condition register, (
24) is an address register file that holds branch destination addresses when multiple conditions of the condition register are met; (12) is an input/output bus; (13), (14).

(16), (18), (21), (22)
is the output bus.

FIG. 3 is a block diagram showing the internal configuration of the condition determination unit (19). In FIG. 3, (26) is an area determination circuit, (28) is a condition comparison circuit, (1g), (2t)
, (22), and (27) are output buses.

Next, the operation will be explained. In FIG. 1, a condition determiner (11) receives data to be compared which is inputted from an arithmetic unit (7) via an output bus (13) and an output bus from a preset threshold register group (15). The comparator (17) compares the magnitude relationship with each of the n thresholds supplied via the output bus (16), and the n comparison results (size The relationship is rOJ, rlJ
(expressed by 1 bit), the condition determiner 19
Determine the data area of the target data.

Figure 4 shows the setting of the threshold value aO...a9 (
This shows an example of division of n+1) areas 0, 4, comparator output, and area determination, and here it is assumed that bits are set to "1" according to area numbers.

The area determining circuit (26) of the condition determining unit (19) determines the area of data based on the comparator output from the comparator (17) supplied via the output bus (18), and generates an index signal indicating the area. Output to the output bus (27). The condition comparison circuit (28) uses this area index signal and the output bus (
If the condition is satisfied by comparison with the condition signal supplied from the condition register (20) via the output bus (21), the address index indicating the branch destination address is sent to the output bus (21).
2) Output.

FIG. 5 shows an example of the format of the condition signal held in the condition register (20).
O to f4 indicate area 0 designation flag to area 4 designation flag, which are 1 when designated and 0 when not designated. Multiple conditions 1 to m can be specified, and the conditions to be compared are prioritized and compared in order. As soon as the conditions are met, the conditions are sent to the condition determiner (19) via the output bus (22). It is assumed that an address index signal is output from.

The address register file (24) stores multiple branch destination addresses according to each condition, and the output bus (24) stores multiple branch destination addresses according to each condition.
2) outputs a branch destination address signal to the output bus (14) based on the address index signal supplied from the condition determiner (19). Based on the address value thus output, the control circuit (2) sets the count value of the built-in program counter to this address value and branches.

If all conditions are not satisfied, the address index signal is "OFF", the address signal output from the address register file (24) is also "OFF", and the count value of the program counter is set to the next instruction. Indicates the street address.

Regarding the data supplied via the output bus (13) from the arithmetic unit (7) to be checked by the data determiner (11), the arithmetic operation unit, multiplier,
By making it possible to specify one of the outputs of the accumulator, etc. by a command such as mode setting, and checking it with the data determiner (11) every machine cycle, the processing time for comparing data ranges can be reduced. loss can be prevented.

FIG. 6 shows a continuous processing flow including an intermediate check. First, initial settings such as comparison target selection, threshold data set, branch address set, branch condition set, etc. are performed (step 5T6-1), and then calculation is performed. Processing and condition determination processing are repeated in parallel through a loop several times for processing data, and when conditions 1 to 3 are met, addresses A to C are output.

〔Effect of the invention〕

As described above, according to the present invention, comparison processing with multiple threshold values is performed on certain data in parallel with arithmetic processing, and multiple branch destinations can be specified according to the comparison processing results. This configuration has the effect that complex branch processing can be efficiently controlled.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a digital signal processor according to an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of a data determiner, and FIG. 3 is a block diagram showing the internal configuration of a data determiner. 4 is an explanatory diagram showing an example of data area determination, FIG. 5 is an explanatory diagram of condition data indicating branch conditions, FIG. 6 is a flowchart of continuous calculation processing including data determination, and FIG. 7 is an explanatory diagram showing an example of data area determination. FIG. 8 is a block diagram showing the overall configuration of a conventional digital signal processor. FIG. 8 is a flowchart of continuous arithmetic processing including data determination in the conventional digital signal processor. In the figure, (1) is a program memory, (2) is a control circuit, (6) is a data memory, (7) is an arithmetic unit, and (11) is a control circuit.
) is a data judge. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent: Patent Attorney Masuo Oiwa (2 others) Internal configuration diagram of condition determination unit Figure 3 Diagram of data area determination 0 Explanation diagram Figure 4 Explanation diagram of condition data Figure 5 Conventional digital signal processing processor Brono, r ;z
j Figure 7: Continuous operation processing 9') Flowchart diagram Flowchart diagram of conventional continuous operation processing Figure 8 Procedure amendment (voluntary) 5. Detailed explanation of the invention of the specification to be amended; A field for a brief description of the drawing. 6. Contents of the amendment 1, Indication of the incident, Patent Application No. 2, Name of the invention: Digital signal processing processor

Claims (1)

[Claims] In a digital signal processing processor whose basic operations are fetching and decoding a built-in microprogram, reading data according to the contents of the microprogram, performing operations, and writing operation result data, A control circuit with a built-in program counter for address control, a data memory for data input/output, and a selection of the arithmetic unit output, logic shifter output, or multiplier output in the arithmetic unit in parallel with the operation of the arithmetic unit. The preset number of n (n is 1) is set for the selected output data.
At the same time, the magnitude relationship is compared with the threshold value (an integer greater than or equal to It is determined whether it exists in the area, and the determination result is sequentially compared with m area limiting conditions (m is an integer of 1 or more) specifying a preset data area, and if the conditions match, the above Output branch destination address information corresponding to the matched area limiting condition from among the m branch destination addresses set in advance in response to the m area limiting conditions, and if all m conditions do not match; and a data determiner that outputs a signal indicating that all conditions do not match, and the control circuit updates the program counter based on the branch destination address information output from the data determiner to determine the branch destination. A digital signal processing processor characterized in that when an instruction address is generated and the output of the data determiner is a mismatch signal, the next instruction address is generated by simply incrementing the program counter by 1.