JPH02187021A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02187021A JPH02187021A JP725689A JP725689A JPH02187021A JP H02187021 A JPH02187021 A JP H02187021A JP 725689 A JP725689 A JP 725689A JP 725689 A JP725689 A JP 725689A JP H02187021 A JPH02187021 A JP H02187021A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- melting point
- point metal
- high melting
- metal material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010409 thin film Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000002844 melting Methods 0.000 claims abstract description 32
- 239000007769 metal material Substances 0.000 claims abstract description 29
- 230000008018 melting Effects 0.000 claims abstract description 28
- 239000010408 film Substances 0.000 claims abstract description 26
- 239000007789 gas Substances 0.000 claims abstract description 19
- 239000011261 inert gas Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- 229910018503 SF6 Inorganic materials 0.000 claims description 7
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 7
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 238000004140 cleaning Methods 0.000 abstract description 3
- 238000004299 exfoliation Methods 0.000 abstract 2
- 239000000203 mixture Substances 0.000 abstract 1
- 230000002269 spontaneous effect Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
この発明は、高融点金属材料薄膜を半導体基板上に選択
的に形成するようにした半導体装置の製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device in which a thin film of a high melting point metal material is selectively formed on a semiconductor substrate.
〈従来の技術〉
半導体装置における半導体基板と配線材料との間の電気
的接続を得るためには、従来は、配線材料と半導体基板
との間で直接電気的接触を形成するようにしていた。第
３図はこのような方法を用いて製造されたＭＯＳｌ−ラ
ンジスタの断面図である。この第３図において、３１は
半導体基板、３２はソース部、３３はドレイン部、３４
はゲート部、３５はＬＯＣＯ９酸化膜、３６はフィール
ド酸化膜（絶縁膜）、３７はアルミニウムあるいはその
合金等の配線材料である。このＭＯＳ）ランジスタは、
ソース部３２およびドレイン部３３の絶縁膜開孔部３８
において、配線材料３７とソース部３２およびドレイン
部３３との間で直接電気的接触を形成している。<Prior Art> In order to obtain electrical connection between a semiconductor substrate and a wiring material in a semiconductor device, a direct electrical contact has conventionally been formed between the wiring material and the semiconductor substrate. FIG. 3 is a cross-sectional view of a MOS l-transistor manufactured using such a method. In FIG. 3, 31 is a semiconductor substrate, 32 is a source portion, 33 is a drain portion, and 34 is a semiconductor substrate.
35 is a gate portion, 35 is a LOCO9 oxide film, 36 is a field oxide film (insulating film), and 37 is a wiring material such as aluminum or its alloy. This MOS) transistor is
Insulating film openings 38 in source part 32 and drain part 33
, direct electrical contact is formed between the wiring material 37 and the source section 32 and drain section 33.
〈発明が解決しようとする課題〉
しかしながら、上記従来の方法では、段差被覆性が悪く
、素子の微細化に伴い、フォトリソグラフィー工程での
アライメントマージンが少ないことや、アスペクト比の
増大に伴う配線の信頼性低下などが問題となっていた。<Problems to be Solved by the Invention> However, with the above-mentioned conventional method, step coverage is poor, alignment margins in the photolithography process are small as elements become smaller, and wiring problems occur due to increased aspect ratio. Problems included reduced reliability.
そこで、最近になって、微細コンタクト部にコンタクト
プラグとしての高融点金属材料薄膜を形成するコンタク
トプラグ技術を用いて、上記のような絶縁膜開孔部（コ
ンタクト開孔部）の基板上に上記高融点金属材料薄膜を
形成し、その上に配線材料を形成するような方法がとら
れるようになった。Therefore, recently, contact plug technology has been developed to form a thin film of a high-melting point metal material as a contact plug in a fine contact area. A method has come to be used in which a thin film of a high melting point metal material is formed and a wiring material is formed thereon.
ところで、これまでのコンタクトプラグ技術においては
、コンタクト開孔部を形成するための絶縁膜のドライエ
ツチング後に、基板材料のエツチングによるダメージ層
の除去のためのプラズマエツチングおよびコンタクト開
孔部の自然酸化膜除去のための湿式洗浄を行い、その後
、そのコンタクト開孔部の基板上に高融点金属材料薄膜
を形成するようにしていた。しかしながら、この方法で
は、上記金属材料薄膜の形成工程とそれ以前の工程との
間で大気にさらされるため、また枚葉式で高融点金属材
料薄膜を形成するために処理されるまでの経過時間の違
いなどにより、金属材料薄膜形成直前の半導体基板のコ
ンタクト開孔部の表面状態の再現性を得ることが困難で
あり、そのために半導体基板表面と高融点金属材料薄膜
との界面の状態に良好な再現性が得られず、電気的接触
抵抗にばらつきを生じるとか、電気的接触抵抗が大きく
なるといった欠点があった。また、上記エツチングには
四弗化炭素（ＣＦ４）ガスや三弗化窒素（Ｎ Ｆ ３）
ガスが一般に用いられるが、基板に対するダメージが大
きいことから、ダメージの少ない六弗化硫黄（ＳＰｓ）
ガスが用いられる傾向にある。しかしながら、Ｓ Ｆ
ｅガス単体中では低印加電圧での放電が起こりにくいた
め安定したエツチングができず、膜はがれの発生といっ
た構造上の不安定さが生じたり、また、この種のエツチ
ングは絶縁膜開孔のためのエツチングに引き続いて行な
われるため、高融点金属材料薄膜の形成までに装置間の
移動で大気にさらされたり、高融点金属材料薄膜形成ま
でに時間がかかることなどから、絶縁膜開孔部の汚染を
回避できないという欠点があった。By the way, in the conventional contact plug technology, after the dry etching of the insulating film to form the contact opening, plasma etching is performed to remove the damaged layer caused by etching of the substrate material, and the natural oxide film of the contact opening is removed. Wet cleaning is performed for removal, and then a high melting point metal material thin film is formed on the substrate in the contact opening. However, in this method, it is exposed to the atmosphere between the process of forming the metal material thin film and the previous process, and the elapsed time until the single wafer process is performed to form the high melting point metal material thin film. It is difficult to obtain reproducibility of the surface condition of the contact hole in the semiconductor substrate immediately before the formation of the metal material thin film due to differences in the thickness of the metal material thin film. However, there are drawbacks such as poor reproducibility, variations in electrical contact resistance, and increased electrical contact resistance. In addition, carbon tetrafluoride (CF4) gas and nitrogen trifluoride (NF3) are used for the above etching.
Sulfur hexafluoride (SPs), which is less damaging, is commonly used, but because it causes more damage to the substrate.
Gas tends to be used. However, S.F.
In e-gas alone, discharge is difficult to occur at low applied voltages, so stable etching is not possible, resulting in structural instability such as film peeling, and this type of etching may cause holes in the insulating film. Since etching is performed subsequent to the etching of the high melting point metal material thin film, it is exposed to the atmosphere during transfer between devices and it takes time to form the high melting point metal thin film. The drawback was that contamination could not be avoided.
そこで、この発明の目的は、高融点金属材料薄膜と半導
体基板との電気的接触抵抗を小さくすることができ、ま
た、高融点金属材料薄膜の膜はがれを生じることのない
半導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the electrical contact resistance between a thin film of a high melting point metal material and a semiconductor substrate, and that does not cause peeling of the thin film of a high melting point metal material. It is about providing.
〈課題を解決するための手段〉
この発明は、高融点金属材料薄膜を形成する反応室と同
一室内で、被処理基板が大気にさらされることなく、薄
膜形成直前に処理されるため、汚染の心配がなく、また
、分圧が下がると放電が起きやすくなり放電が均一にな
るというＳ Ｆ ｅガスの特性に着目してなされたもの
であり、表面が絶縁膜により部分的に被覆された半導体
基板の露出表面上のみに高融点金属材料薄膜を選択的に
形成するようにした半導体装置の製造方法において、上
記高融点金属材料薄膜を形成する反応室と同一反応室内
において被処理基板が大気にさらされることなく、上記
高融点金属材料薄膜を形成する直前に、六弗化硫黄ガス
に不活性ガスを添加した混合ガスにより上記半導体基板
の露出表面をエツチングして薄層を除去するようにした
ことを特徴としている。<Means for Solving the Problems> In the present invention, the substrate to be processed is processed immediately before forming the thin film in the same chamber as the reaction chamber in which the thin film of the high-melting point metal material is formed without being exposed to the atmosphere, thereby reducing contamination. It was created by focusing on the characteristics of SF-e gas that there is no need to worry about it, and that when the partial pressure decreases, discharge occurs more easily and the discharge becomes uniform. In a method for manufacturing a semiconductor device in which a thin film of a high melting point metal material is selectively formed only on the exposed surface of a substrate, the substrate to be processed is exposed to the atmosphere in the same reaction chamber as the one in which the thin film of the high melting point metal material is formed. Immediately before forming the thin film of the high-melting point metal material, the exposed surface of the semiconductor substrate is etched with a mixed gas of sulfur hexafluoride gas and an inert gas to remove the thin layer without exposure. It is characterized by
〈作用〉
表面が絶縁膜により部分的に被覆された半導体基板の露
出表面を六弗化硫黄ガスに不活性ガスを添加した混合ガ
スによりエツチングして薄層を除去し、その直後に同一
反応室内において大気にさらすことなくその露出表面上
のみに高融点金属材料薄膜を選択的に形成する。このよ
うに、六弗化硫黄ガスに不活性ガスを添加した混合ガス
を用いているので、六弗化硫黄ガスの分圧が下がり、放
電が起きやすく放電が均一になって安定したエツチング
がおこなわれ、高融点金属材料薄膜の膜はがれが生じな
い。また、エツチング及び高融点金属材料薄膜の形成が
各処理基板ごとに連続して行なわれるため、各処理基板
ごとの成膜状態のばらつきが少ない。また、上記エツチ
ングをして薄層を除去した直後に高融点金属材料薄膜を
形成するようにしているので、電気的接触抵抗が小さく
なる。<Operation> The exposed surface of the semiconductor substrate, whose surface is partially covered with an insulating film, is etched with a mixed gas of sulfur hexafluoride gas and an inert gas to remove the thin layer, and immediately thereafter, the exposed surface of the semiconductor substrate is etched in the same reaction chamber. A thin film of high-melting point metal material is selectively formed only on the exposed surface without exposing it to the atmosphere. In this way, since a mixed gas of sulfur hexafluoride gas and an inert gas is used, the partial pressure of the sulfur hexafluoride gas is lowered, making it easier for discharge to occur and making the discharge uniform, resulting in stable etching. Therefore, peeling of the high melting point metal material thin film does not occur. Furthermore, since the etching and the formation of the high melting point metal material thin film are performed continuously for each processing substrate, there is little variation in the film formation state for each processing substrate. Further, since the refractory metal material thin film is formed immediately after the thin layer is removed by etching, the electrical contact resistance is reduced.
〈実施例〉 以下、この発明を図示の実施例により詳細に説明する。<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.
第１図はこの発明の一実施例の半導体装置の製造方法を
説明するための工程断面図である。FIG. 1 is a process sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
第１図（ａ）に示すように、まず、半導体基板１のコン
タクト部の絶縁膜２をエツチングし、０．８μｍ角以下
のコンタクト開孔部５を作る。そして、このコンタクト
開孔部５におけ４半導体基板表面にできた自然酸化膜３
を湿式洗浄により除去すると第１図（ｂ）の状態となる
。次に、第１図（ｃ）に示すように、コンタクト開孔部
５に高融点金属材料薄膜を選択的に形成する反応室と同
一反応室内において、ＳＦｅガスと不活性ガス（例えば
、ヘリウムガス）との混合ガスによりコンタクト開孔部
５の半導体基板を表面から５０人〜３００人程度（図中
４で示す部分）エツチングしてダメージ部を除去する。As shown in FIG. 1(a), first, the insulating film 2 at the contact portion of the semiconductor substrate 1 is etched to form a contact opening 5 of 0.8 μm square or less. A natural oxide film 3 formed on the surface of the semiconductor substrate 4 in this contact opening 5
When removed by wet cleaning, the state shown in FIG. 1(b) is obtained. Next, as shown in FIG. 1(c), SFe gas and an inert gas (for example, helium gas ) to remove the damaged portion by etching the semiconductor substrate in the contact opening 5 from the surface by approximately 50 to 300 etches (the portion indicated by 4 in the figure).
エツチング時の基板温度は室温付近から８０℃位までが
適切であった。引き続いて同一反応室内において、第１
図（ｄ）に示すように、高融点金属材料薄膜６をコンタ
クト開孔部５の基板表面上のみに選択的に、絶縁膜２の
厚さに相当する厚さまで形成する。The appropriate substrate temperature during etching was from around room temperature to about 80°C. Subsequently, in the same reaction chamber, the first
As shown in Figure (d), a high melting point metal material thin film 6 is selectively formed only on the substrate surface of the contact opening 5 to a thickness corresponding to the thickness of the insulating film 2.
このようにして形成された高融点金属材料薄膜は、膜は
がれが発生せず、また、電気的接触抵抗値は従来の方法
で形成されたものに比べ約１／２〜！１５に低減するこ
とが確認されている。The high melting point metal thin film formed in this way does not peel off, and the electrical contact resistance value is about 1/2 that of that formed by conventional methods! It has been confirmed that this decreases to 15.
第２図は本実施例の製造方法を適用して作成したＭＯＳ
−ＦＥＴの断面図である。ここで、２１は半導体基板、
２２はソース部、２３はドレイン部、２４はゲート部、
２５はＬＯＧＯＳ酸化膜、２６はフィールド酸化膜（絶
縁膜）、２７はアルミニウムあるいはその合金等の配線
材料、２８はコンタクトプラグとしての高融点金属材料
薄膜である。このＭＯＳ−ＦＥＴは通常のＭＯ３製造プ
ロセスにおいて、第１図で説明したように、ソース部２
２やドレイン部２３上の絶縁膜２６をエツチングしてコ
ンタクト開孔部２９を形成し、この開孔部２９のみに選
択的に高融点金属材料薄膜２８を絶縁膜２６の厚さに相
当する厚さに形成する。Figure 2 shows a MOS manufactured by applying the manufacturing method of this example.
- It is a sectional view of FET. Here, 21 is a semiconductor substrate,
22 is a source part, 23 is a drain part, 24 is a gate part,
25 is a LOGOS oxide film, 26 is a field oxide film (insulating film), 27 is a wiring material such as aluminum or its alloy, and 28 is a high melting point metal material thin film as a contact plug. In the normal MO3 manufacturing process, this MOS-FET has a source part 2,
2 and the insulating film 26 on the drain part 23 to form a contact opening 29, and selectively coat the high melting point metal material thin film 28 only in this opening 29 to a thickness corresponding to the thickness of the insulating film 26. to form.
その後、配線材料２７を形成１２、上記高融点金属材料
薄膜２８を介してこの配線材料２７とソース部２２およ
びドレイン部２３との電気的接続を得るようにしている
。Thereafter, a wiring material 27 is formed 12, and electrical connection between the wiring material 27 and the source section 22 and drain section 23 is obtained via the high melting point metal material thin film 28.
このように、電気的接触抵抗が小さく、安定した構造の
コンタクトプラグを形成して、配線材料と基板との間の
電気的接続を得るようにしているので、第３図の従来例
におけるような素子の微細化に伴う配線の信頼性低下な
どあ問題がなく、素子の信頼性が向上すると共に、高集
積化が容易に図れ、高機能デバイスの実現が可能となる
。In this way, a contact plug with a stable structure and low electrical contact resistance is formed to obtain an electrical connection between the wiring material and the substrate, so that it is possible to obtain an electrical connection between the wiring material and the substrate. There is no problem such as deterioration in reliability of wiring due to miniaturization of elements, the reliability of the elements is improved, high integration is easily achieved, and high-performance devices can be realized.
〈発明の効果〉
以上より明らかなように、この発明の半導体装置の製造
方法によれば、表面が絶縁膜により部分的に被覆された
半導体基板の露出表面を六弗化硫黄ガスに不活性ガスを
添加した混合ガスによりエツチングして薄層を除去し、
その直後に同一反応室内において大気にさらされること
なくその露出表面上のみに高融点金属材料薄膜を選択的
に形成することにより、電気的接触抵抗が小さく膜はが
れの生じない高融点金属材料薄膜を形成することができ
、従って、素子の信頼性の向上、高集積化が図れ、高機
能デバイスの実現が可能となる。<Effects of the Invention> As is clear from the above, according to the method for manufacturing a semiconductor device of the present invention, the exposed surface of a semiconductor substrate whose surface is partially covered with an insulating film is exposed to sulfur hexafluoride gas and an inert gas. The thin layer is removed by etching with a mixed gas containing
Immediately after that, by selectively forming a high melting point metal thin film only on the exposed surface in the same reaction chamber without exposing it to the atmosphere, we can create a high melting point metal thin film with low electrical contact resistance and no peeling. Therefore, the reliability of the element can be improved and the degree of integration can be increased, making it possible to realize a highly functional device.
第１図はこの発明の一実施例の半導体装置の製造方法を
説明するための工程断面図、第２図は上記製造方法を用
いて作製したＭｏｓ〜ＦＥＴの断面図、第３図は従来の
製造方法を用いて作製したＭＯＳ−ＦＥＴの断面図であ
る。
！・・半導体基板、
２・・・フィールド酸化膜（絶縁膜）、３・・・自然酸
化膜、４・・・エツチングされた部分、５・・・コンタ
クト開孔部、
６・・・高融点金属材料薄膜。FIG. 1 is a process cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a Mos~FET manufactured using the above manufacturing method, and FIG. FIG. 2 is a cross-sectional view of a MOS-FET manufactured using the manufacturing method. ! ... Semiconductor substrate, 2... Field oxide film (insulating film), 3... Natural oxide film, 4... Etched portion, 5... Contact opening, 6... High melting point metal Material thin film.
Claims (1)
板の露出表面上のみに高融点金属材料薄膜を選択的に形
成するようにした半導体装置の製造方法において、 上記高融点金属材料薄膜を形成する反応室と同一反応室
内において被処理基板が大気にさらされることなく、上
記高融点金属材料薄膜を形成する直前に、六弗化硫黄ガ
スに不活性ガスを添加した混合ガスにより上記半導体基
板の露出表面をエッチングして薄層を除去するようにし
たことを特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device in which a high melting point metal material thin film is selectively formed only on the exposed surface of a semiconductor substrate whose surface is partially covered with an insulating film, the high melting point metal material thin film is Immediately before forming the high melting point metal material thin film, the semiconductor substrate is heated in the same reaction chamber as the reaction chamber in which it is formed, without exposing the substrate to the atmosphere, using a mixed gas of sulfur hexafluoride gas and an inert gas. 1. A method of manufacturing a semiconductor device, characterized in that a thin layer is removed by etching the exposed surface of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1007256A JPH0744161B2 (en) | 1989-01-13 | 1989-01-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1007256A JPH0744161B2 (en) | 1989-01-13 | 1989-01-13 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02187021A true JPH02187021A (en) | 1990-07-23 |
| JPH0744161B2 JPH0744161B2 (en) | 1995-05-15 |
Family
ID=11660949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1007256A Expired - Fee Related JPH0744161B2 (en) | 1989-01-13 | 1989-01-13 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744161B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62291918A (en) * | 1986-06-12 | 1987-12-18 | Matsushita Electric Ind Co Ltd | Selective deposition of metal |
| JPS6341014A (en) * | 1986-08-06 | 1988-02-22 | Sanyo Electric Co Ltd | Epitaxial growth method |
| JPS63125681A (en) * | 1986-11-12 | 1988-05-28 | Matsushita Electric Ind Co Ltd | Thin film forming device |
-
1989
- 1989-01-13 JP JP1007256A patent/JPH0744161B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62291918A (en) * | 1986-06-12 | 1987-12-18 | Matsushita Electric Ind Co Ltd | Selective deposition of metal |
| JPS6341014A (en) * | 1986-08-06 | 1988-02-22 | Sanyo Electric Co Ltd | Epitaxial growth method |
| JPS63125681A (en) * | 1986-11-12 | 1988-05-28 | Matsushita Electric Ind Co Ltd | Thin film forming device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0744161B2 (en) | 1995-05-15 |
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