JPH0218626B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault information transfer system in a duplex-configured switch.

In general, in a switch with a duplex configuration, if one system (one system) of the duplex system is in operation and the other system is a standby system, if a fault occurs in the system in operation, the fault information will be sent. It is necessary to urgently transmit the information to the standby system and switch the system. that time,
Before sending a system switching request to the system control device, the processor of the faulty system sends fault information to the memory of the standby system via the communication control device, and the system that has newly entered operation notifies maintenance personnel of the fault. There are possible ways. However, this method has the following drawbacks.

(1) Since it cannot be guaranteed that the operation of the faulty system is normal, the method of unilaterally sending data from the faulty system to the normal system may accidentally destroy the memory contents of the normal system.

(2) Depending on the nature of the disability, there is no guarantee that disability information will always be sent.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fault information transfer method for a duplex exchange that allows fault information to be accurately and smoothly transmitted from a faulty system to a backup system.

The gist of the present invention is to add a function that can display fault details to a system control device, and to enable fault information in the faulty system to be read out to the normal system under the control of the normal system after system switching when a specific fault occurs. This is what I did.

The present invention will be explained in detail below with reference to FIGS. 1 and 2.

FIG. 1 shows the configuration of an example of a dual exchange system according to the present invention. The 0 system A is used as an act system, and the 1 system B is used as a standby system, but both the 0 system and 1 system have almost the same hardware configuration. The 0 system is connected to the processor 1, the memory device 2, the 0 system processor bus 3, the system control device 4, and the communication control device 5, and the 1 system is connected to the processor 11 and the memory device 1.
2, 1 system processor bus 13, system control device 14, and communication control device 15, the system control devices 4 and 14 are connected by an intersystem crossover bus 21, and the communication control devices 5 and 15 are connected by internal communication control. They are each interfaced by a bus 20. With this system configuration, during steady operation, the 0 system is operated as the active system and the 1 system is operated as the standby system, and if some kind of failure occurs in the 0 system, which is the active system, the 1 system becomes the active system, and the 0 system becomes the active system. The system immediately switches to the standby system, but this switching is performed after the failure type and whether failure information is stored are displayed on the system control device of the 0 system.

The system control devices 4 and 14 are system consoles having lamps, key switches, etc., and monitor the operating status of each system, and the information obtained by this monitoring is transmitted to the system control device 14 of the other system via an intersystem crossover bus 21. , 4. Monitoring information includes, in addition to normal monitoring information, failures seen from the internal hardware perspective, failures seen from the software perspective, other system-detectable failure status information, failure type information, and memory device information when a failure occurs. 2 includes information on whether or not fault information is stored, and by displaying this monitoring information in the system control devices 4 and 14, maintenance personnel can easily grasp the system status. It's summery.

The above are common functions of the system control devices 4 and 14, but the system control devices 4 and 14 also have the 0 system,
It has a switching function that switches the 1 system and 0 system to the active system and the 0 system and 1 system to the standby system when the 1 system fails. Now, the system control device 4,
Processor 14 is monitored by processors 1 and 11 from the displayed monitoring information, but after system switching, processors 1 and 11 look at the failure type information at the time of failure and determine whether it is the other system, that is, the active system. This is the place where it is possible to confirm which part of the system or system 1 the failure has occurred in, and to report the necessary information to the maintenance personnel and take the necessary actions. Speaking of failures here, the failure that has the greatest impact is the failure of the processors 1 and 11 themselves. Various other problems may occur, but
Memory device 1, 1 in the event of a specific failure
A process is performed to read the previous information (including failure information) stored in the memory device 2 into the memory device 12, 12 of the other party. For example, when reading stored information from the memory device 2, the processor 11 generates a read command;
This is done by sending the data to the memory device 2 via the communication control device 15, bus 20, and communication control device 5. Data read from the memory device 2 is stored in the memory device 12 via the bus 3 → communication control device 5 → bus 20 → communication control device 15 → bus 13 → memory device 12. This operation means that the memory device 2 moves from being under the control of the processor 1 to being under the control of the processor 11 when a specific failure occurs in the 0 system. Specific examples of fault information include the type of faulty device (part),
These include the contents of the processor's status register, the contents of the processor's data register, the contents of the processor's address register, and a group of error counters indicating failure frequency. In addition, for example, in case of a communication failure such as a power outage of each device in the 0 system,
A message to that effect is displayed on the system control device 14 via the system control device 4, and the notification processing is performed from the normal system 1. Furthermore, the communication control devices 5 and 15 are used for data communication between the 0 system and the 1 system, and normally the information from the 0 system, which is the active system, must be sent to the 1 system, which is the standby system, to the minimum necessary. Rather, it is provided for the purpose of transferring this information.

Now, let me explain the operation. Normally, system 0 operates as an active system, and system 1 stands by as a standby system. Processor 1 in the active system performs necessary processing, and performs predetermined data read and write operations with the memory device 2. Processing is taking place. Also,
Necessary data is also exchanged with other terminals via the bus 3. Furthermore, the system control device 4
In this case, the 0 system is monitored, and when a failure of some kind occurs, failure display (latches) such as failure type information is performed.
The system control device 14 in the standby system receives the monitoring information displayed on the system control device 4 via the intersystem cross bus 21, and similarly displays (latches) the monitoring information. The communication control device 5 also uses the bus 3.
Bus 20 receives information for transfer from
It is transferred to the standby system via the communication control device 15. Therefore, the 1st system receiving this transfer information is substantially synchronized with the 0th system.

Here, if some kind of failure occurs in the act system, the failure type information etc. will be sent to the system control device 4,
It will be displayed on the 14th. There are three types of failure type information: the first is processor failure "11", the second is failure to communicate due to a failure in the communication control device, etc. "10", and the third is memory of system 0, which is the failed system that caused the failure. A first method involving accumulation of failure information in the device 2;
Failure other than the second is "01". Therefore, if the occurrence of a failure related to the third failure is displayed in the system control device 14 and a display indicating that failure information is stored in the memory device 2 is displayed, the 1st system is established as the active system. In addition, the processor 11 sends an information read command to the memory device 2 along the route of bus 13 → communication control device 15 → bus 20 → communication control device 5 → bus 3 → memory device 2, and reads the stored information one after another. . This read information passes through the above path in the opposite direction and is stored in the memory device 12.

Furthermore, if the display in the system control unit 14 is a failure type related to a processor failure or communication failure, the 1 system will be established as the active system regardless of whether or not the failure information of the 0 system is stored in the memory device 2. maintenance personnel are now being notified of processor failures and communication failures. In the case of the third failure mode "01", the processor 11 reads the failure information, but the result of this operation is checked for errors.
If an error occurs, take appropriate action at that point, for example, start up system 1 as an active system,
The maintenance personnel are now notified of the error. Even when no error occurs, the 1st system is actually started up as an active system.

As mentioned above, if some kind of failure occurs in the act system, the act system will be switched, but
FIG. 2 shows a block configuration of an example of the system control device 4. As shown in FIG. System control device 14
The block configurations are also the same, but the system control device 4 includes a system switching section 40 that controls system switching;
A status display unit 41 that displays the type of failure and whether or not failure information is stored in the memory; and a processor failure detection unit 4 that detects a failure of the processor 1.
It is composed of 2. Here, assuming that the active system is the 0 system and the standby system is the 1 system, we will explain the operation procedure for system switching.If a third failure occurs in the 0 system, then the active system 0
The system processor 1 writes information on the detected fault to the memory device 2, and then sets fault information indicating that the fault details can be recognized and an indication that the fault information has been stored in the memory device 2 in the status display section 41. After that, a system switching instruction is sent to the system switching unit 40. System switching unit 4 that received system switching instructions
0 sets the 0 system as a standby system, and then instructs the system switching unit of the system control device 14 of the 1 system, which is another system, to switch the system using the intersystem crossing bus 21. Then, in response to the system switching instruction, the system switching unit of the system control device 14 of the 1st system switches the 1st system from the standby system to the active system, notifies the processor 11 that the system switching instruction has been received, and completes the system switching operation. do.
Furthermore, when performing a system switchover due to communication failure from the 0 system to the 1 system, the processor 1 indicates to the status display unit 41 that the failure type is communication failure, and then instructs the system switchover unit 40 to perform system switchover. I'm starting to do it.
Furthermore, in the case of a processor failure, the processor 1 itself cannot instruct the system switching unit 40 to perform system switching, so if the processor failure detection unit 42 detects a failure in the processor 1, it will notify the status display unit 41 that the processor has failed. After a certain type of failure occurs, the system switching unit 40 is instructed to perform system switching.

By the above operation, the information stored in the memory device 2 of the 0 system, which is the faulty system, can be regularly stored in the memory device 12 of the 1 system, which is the normal system.
This ensures that when system 1 is switched from the standby system to the active system, system 1 is not affected by system 0, which is the faulty system, and in particular that the fault information is effectively stored in memory device 2. Since the processor 11 reads the fault information and stores it in the memory device 12 upon seeing this display, the normal system 1 does not suffer from the adverse effects of the faulty system 0. Furthermore, since the failure information is reliably stored in the memory device 12 of system 1, which is the normal system, at the time of system switchover, the smooth transition of system 1 to the active system and the smooth transition of system 0 after system switchover are ensured. We were able to carry out the necessary separation work. Furthermore, for other fault indications, the first system, which was a standby system, does not store fault information in the memory device 12, so erroneous information due to the fault will not be stored in the memory device 12. This shows that the standby system 1 is not adversely affected by the faulty active system.

According to the present invention described above, the contents of a normal memory device can be protected from erroneous processing in a faulty system in a duplex system, and fault information can be reliably collected. Furthermore, by having the system control device display the failure type and accumulated failure information of the failure system, the standby system (standby standby system) can be
It was possible to reliably notify the failure type and whether failure information had been accumulated. This has made reliable system switching possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an example of a dual exchange system according to the present invention, and FIG. 2 is a diagram showing the block configuration of an example of the system control device in FIG. 1. 1, 11... Processor, 2, 12... Memory device, 4, 14... System control device, 5, 15
... Communication control device, 20 ... Internal communication control bus,
21...Intersystem crossing bus.

Claims (1)

[Scope of Claims] 1 Consists of a 0-system processor system that normally operates as an active system, and a 1-system processor system that normally operates (standby) as a standby system,
Each of the above processor systems consists of a processor, a memory device, a system control device, a communication control device, and a common bus that interfaces these devices. In a dual-system exchange configured such that the communication control devices of the 0-system and 1-system processor systems are connected via a communication control bus for information transmission, the communication control devices of the 0-system and 1-system processor systems are
The system control device of the system processor system monitors failures in the 0 system, displays the type of failure when a failure occurs, and displays whether or not the failure information has been stored in the memory device of the 0 system. The system control device of the 1-system processor system captures and displays the fault type of the 0-system and the presence or absence of fault information storage via the inter-system crossover bus, and the 1-system processor system Looking at the display contents, only when a failure other than a processor failure or a communication failure occurs, and when failure information is stored, the above 1 system common bus, communication control device, communication control bus, 0 system communication control device, common A fault information transfer method for a dual-system exchange characterized in that fault information stored in a 0-system memory device is read and stored in a 1-system memory device via a bus. 2. Switching from the 0 system to the 1 system in the act system is performed when a processor failure, a communication failure, or any failure other than these failures is displayed in the system control device of the 0 system.Claim 1 Fault information transfer method described in section.