JPH02185067A - Horizontal insulated-gate bipolar transistor - Google Patents

Abstract

PURPOSE:To obtain a horizontal insulated-gate bipolar transistor having sufficiently low ON resistance by forming an insulating layer partly on a base region adjacent to an anode region, forming a carrier absorption region, and controlling the degree of conductivity modulation effect. CONSTITUTION:Holes 16 implanted from a P<+> type anode region to a n-type base region 2a by the application of a voltage to an anode electrode and a gate electrode 8 are advanced toward a p-type base region 4. In this case, the holes 16 are absorbed to a p-type silicon substrate 1 due to the presence of an insulating layer 20 but not fed out, and advanced toward the p-type base region 4 in the n-type base region 2a, thereby generating sufficient conductivity type modulation effect for the n-type base region 2a. On the other hand, a boundary region between the p-type silicon substrate and the n-type base region 2a to the part underneath the p-type base region 4 from the 3nd of the insulating layer 20 becomes a hall absorption region 23, the holes due to the conductivity type modulation effect are all prevented from arriving at the p-type base region 4 to be latched up. Thus, high breakdown strength and low ON resistance are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a lateral insulated gate bipolar transistor.

(Prior Art) A lateral DMOSFET (LDMOS) is a device used when a high breakdown voltage and a large number of outputs are required.

As shown in FIG. 6, which shows an example of an n-channel LDMO 8, this LDMOS consists of an isolation region 3 made of a p-type diffusion layer within an n-type epitaxial layer 2 formed on the surface of a p-type silicon substrate 1. The n-type epitaxial layer 2 in the element region surrounded by the isolation region 3 is used as a drain region, and the base region 4 made of a p-type diffusion layer is formed in the n-type epitaxial layer 2. In the base region 4, a source region 5 made of an n-type diffusion layer and a base contact region 6 made of a p♦ type scattering layer are formed.

A gate electrode 8 is formed on the substrate surface adjacent to the source region via a gate insulating film 7, and a source electrode contacting the source region 5 and the base contact region 6 is formed on the upper layer via an interlayer insulating film 9. 10 are formed.

Further, in the n'J1 epitaxial layer 2, a drain contact region 11 made of an n-type diffusion layer is formed at a predetermined distance from the p-type base region 4, and a drain electrode 12 is connected to this. .

Further, the isolation region 3 is connected to a ground potential via an isolation ground electrode 13.

Such an LDMO 9 has the advantage that a high breakdown voltage can be easily achieved by optimally selecting the resistivity and layer thickness of the n-type epitaxial layer 2 constituting the drain region, or the position of the drain contact region 11. do.

Furthermore, if a p-type substrate is used and the element formation region is surrounded by the isolation region 3, element isolation can be easily achieved, allowing multiple LDMOs 8 to be integrated on the same substrate,
Other ICs can also be integrated.

Because of these characteristics, LDMO3 is suitable for ICs such as EL drivers that require high voltage resistance and multiple output stages.
Widely used in the output stage of

However, such an LDMO3 also has a drawback in that the on-resistance during operation is high due to the high specific resistance of the drain region. For this reason, there is a problem that it cannot be used for devices that require large current output.

A lateral insulated gate bipolar transistor (LIGBT) is available as a solution to these drawbacks.

As an example of this LI GBT, as shown in FIG. 7, an n-channel type LI GBT is connected to the drain contact region 11 of the n-channel type LDMO 8 shown in FIG. Instead, a p◆ type scattered layer is formed and this is used as the anode region 14, and the other part is LDM.
It is formed in exactly the same manner as O5, the drain electrode 12 becomes the anode electrode 15, and the n-type epitaxial layer 2 acts not as a drain region but as an n-type base region 2a.

During operation of this LI GBT, a large amount of holes 16 are injected from the anode region 14 into the n-type base region 2a, so that the n-type base region 2a is injected due to the conductivity modulation effect.
The specific resistance of a decreases by 1 to 3 orders of magnitude.

Therefore, LIGBT has a significantly lower on-resistance than LDMO3 even with the same breakdown voltage, and can also be used as an output stage element of an IC that requires high breakdown voltage and large current capacity.

However, since the p-type silicon substrate 1 is grounded for element isolation, the hole 16 in the n-type base region 2a
Therefore, the holes 16 injected from the anode region 14 are sucked out into the p-type silicon substrate 1 while flowing into the p-type base region 4 . As a result, the hole 16 in the n-type base region 2a
Although the concentration of is sufficiently high in the vicinity of the p-type anode region 14, it rapidly decreases as it moves away from the p-type anode region 14, so that the conductivity is not sufficiently modulated over the entire n-type base region 2a, and the on-resistance is low compared to the hole concentration to be injected. There is a problem that is not low enough.

(Problems to be Solved by the Invention) As described above, in the conventional lateral insulated gate bipolar transistor, the holes 16 injected from the anode region 14 enter the p-type silicon substrate 1 while flowing through the n-type base region 2a. It is sucked out and the n-type base region 2
There was a problem in that the conductivity modulation effect could not be sufficiently exhibited in the a, and the on-resistance could not be made sufficiently low.

The present invention has been made in view of the above, and an object of the present invention is to provide a lateral insulated gate bipolar transistor with sufficiently low on-resistance.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the present invention, in a lateral insulated gate bipolar transistor, an insulating layer is formed under at least a part of the base region adjacent to the anode region, and a carrier sucking region is formed to conduct conduction. The degree of degree modulation effect is controlled.

(Function) According to the above configuration, due to the presence of the insulating layer formed at least in part under the base region adjacent to the anode region,
Confining carriers within the base region increases the carrier concentration and effectively exhibits the conductivity modulation effect, while forming a carrier sucking region to prevent latch-up, which was a trade-off relationship in conventional L I GBTs. It becomes possible to control the conductivity modulation effect and latch-up resistance at a high level.

(Example) Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

Example 1 As shown in FIG. 1, this LIGBT is different from the conventional LIGBT shown in FIG.
From below 4 to the isolation sun region 3, an insulating layer 20 made of a silicon oxide layer is interposed in the boundary region between the n-type base region 2a and the p-type silicon substrate 1, and on the p-type base region 4 side, an n-type The base region 2a is characterized by being in direct contact with the p-type silicon substrate 1 to form a hole sucking region, and the other parts are similar to the conventional LIG.
It is exactly the same as BT. Note that the same parts are given the same symbols. Further, in the case of a breakdown voltage of 500V, the horizontal distance between the p-type anode region 14 and the p-type base region 4p is about 40 μm.
The length of the insulating layer 20 was about 35 μm, and the length of the suction region 23 was about 5 μm.

For manufacturing, a normal semiconductor manufacturing process is used, and the insulating layer 20 is easily formed by the SIMOX method or the like.

Next, the operation of this LIGBT will be explained.

In this LIGBT, first, by applying a voltage to the anode electrode and the gate electrode 8, holes 16 injected from the p-type anode region into the n-type base region 2a advance toward the p-type base region 4. At this time, due to the presence of the insulating layer 20, the holes 16 are not sucked out to the p-type silicon substrate 1 and proceed through the n-type base region 2a toward the p-type base region 4. 2a to produce a sufficient conductivity modulation effect. Therefore, the on-resistance of this LIGBT is reduced.

On the other hand, the boundary region between the p-type silicon substrate 1 and the n-type base region 2a from the end of the insulating layer 20 to below the p-type base region 4 becomes a hole sucking region 23, and all the holes due to the conductivity modulation effect are transferred to the p-type base region 4. It is possible to prevent latch-up from reaching region 4.

As described above, this LIGBT has high breakdown voltage and low on-resistance.

Example 2 Next, a second embodiment of the present invention will be described.

In this example, as shown in FIG. 2, an insulating layer 20 made of a silicon oxide layer is formed in the boundary region between the n-type base region 2a and the p-type silicon substrate 1 over the entire element region surrounded by the isolation region 3. In addition to intervening, p
It is characterized in that a hole sucking region 21 made of a p-type diffusion layer is formed on the surface of the n-type base region 2a located between the ten-type anode region and the p-type base region 4. This is exactly the same as the LIGBT of the first embodiment shown in FIG.

As a result, there is no need for patterning when forming the insulating layer, which simplifies manufacturing, and the epitaxial layer can be formed uniformly over the entire area, resulting in a LIGB with better characteristics.
It becomes possible to form a T.

Embodiment 3 Furthermore, in the second embodiment, the hole extraction region 21 is formed of a p-type diffusion layer, but a Schottky junction may be used as the hole extraction region.

That is, as shown in FIG. 3 as a third embodiment, a source electrode 10 made of an aluminum layer contacts a part of the surface of an n-type base region 28 through a contact hole formed in an interlayer insulating film 9, and a Schottky A junction may be formed, and this Schottky junction may serve as the hole extraction region 22. Since this source electrode 10 side is negatively biased, this Schottky junction effectively functions as a hole sucking region.

In these second and third embodiments, the position and area of the hole sucking region can be freely adjusted, and thereby the conductivity modulation effect and latch-up resistance can be controlled at a high level.

Furthermore, in these second and third embodiments, the n-type base region 2a is completely isolated from the substrate by the insulating layer 20 and the isolation run region 3, so that the conductivity type and impurity concentration of the substrate can be controlled. It has the advantage of being free to choose.

Embodiment 4 Taking advantage of the above advantages, instead of the p-type silicon substrate 1 on which the n-type epitaxial layer 2 is formed, an n-type substrate on which a buried insulating layer is formed may be used.

That is, as shown in FIG. 4 as a fourth embodiment, an n-type substrate 25 having an embedded insulating layer 20 formed therein is used, and the same structure as in the first to third embodiments is formed in this n-type substrate 25. Form an element region.

This significantly reduces costs. Also, CMO
When integrated on the same substrate as 8, this LIGBT can be manufactured using almost CMO3 manufacturing rules, making it extremely practical.

Example 5 Furthermore, in each of the above examples, nJll
As an isolation region on the side of the heath region 2a, p
Although a type diffusion layer is used, the isolation region 26 may be formed of an insulating layer made of a silicon oxide layer, as shown in FIG. 5 as a fifth embodiment. The other parts are the same as those in the previous embodiment.

When a p-type diffusion layer is used as the isolation region as in the embodiment described above, a distance of several + μ- or more from the p-type anode region 14 is ensured to ensure a breakdown voltage between the n-type base region 2a and the p-type anode region 14. However, in this case, since the insulating layer is used as an isolation region, this distance is no longer necessary, and the device area can be reduced.

Further, in this case, since the entire bottom surface of the n-type base region 2a is insulated from the substrate 1 by the insulating film 20, a high breakdown voltage can be maintained even if the thickness of the n-type base region 2a is reduced. Therefore, the field oxide film formed in the normal LOGO8 process can be used for the insulating layer 26 in this isolation region, which makes it possible to manufacture the tC simultaneously with the tC integrated in the same substrate. This makes it possible to manufacture the product without increasing the number of manufacturing steps.

Note that in this example, there is no need to take space outside the p-type anode region 14 to maintain the breakdown voltage;
Centering around the mold base region 4 and n+ source region 5,
The p-type anode region 14 can be formed in a ring shape around the periphery.

Additionally, a groove formed to reach the insulating layer may be used as the isolation region. Furthermore, this groove may be filled with an insulator.

〔Effect of the invention〕

As described above, according to the LI GET of the present invention, the insulating layer formed at least partially under the base region adjacent to the anode region, and the carrier sucking region formed on the upper surface or lower surface of the base region. By controlling the distribution of injected carriers in the base region and controlling the degree of conductivity modulation effect, it is possible to increase the breakdown voltage and reduce the on-resistance at the same time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an L I GBT according to a first embodiment of the present invention, FIG. 2 is a diagram showing an LXGBT according to a second embodiment of the present invention, and FIG. 3 is a diagram showing a LXGBT according to a second embodiment of the present invention. FIG. 4 is a diagram showing the L I GBT of the fourth embodiment of the present invention.
FIG. 5 is a diagram showing LIGB of the fifth embodiment of the present invention.
FIG. 6 is a diagram showing a conventional LDMO 3, and FIG. 7 is a diagram showing a conventional LIGBT. DESCRIPTION OF SYMBOLS 1...p-type silicon substrate, 2a...n-type base region, 3...p-type isolation region, 4...p-type base region, 5...n-type base region, 6...・n-type base contact region, 7...gate oxide film, 8...
- Gate electrode, 9... Interlayer insulating film, 10... Source electrode, 11... n+ drain contact In region, 12
... Drain electrode, 13... Isolation ground electrode, 14... P-type anode region, 15... Anode electrode, 16... Hole, 20... Insulating layer, 2
DESCRIPTION OF SYMBOLS 1... P ten-shaped hole extraction region, 22... Schottky junction, 23... Hole extraction region, 25...
N-type silicon substrate, 26...field oxide film.

Claims (1)

[Claims] A base region of a first conductivity type with a relatively low impurity concentration formed on the surface of a substrate, and a base of a second conductivity type formed on a part of the surface of the base region of the first conductivity type. a first conductivity type source region formed on a part of the surface of the second conductivity type base region; and a first conductivity type source region between the first conductivity type base region and the first conductivity type source region. a gate electrode formed on the surface of the base region of the second conductivity type sandwiched therebetween via a gate insulating film; and a gate electrode formed on the surface of the base region of the first conductivity type separated from the base region of the second conductivity type. In the lateral insulated gate bipolar transistor comprising a second conductivity type anode region formed therein, at least a portion of the first conductivity type base region formation portion is provided at a predetermined depth from the surface of the base region formation portion. an insulating layer formed, a separation region formed in a peripheral portion of the first conductive type base region to reach the insulating layer, and a second conductive type base in the first conductive type base region. A lateral insulated gate bipolar transistor comprising: a minority carrier extraction region formed between the region and the anode region.