JPH02185041A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02185041A JPH02185041A JP368189A JP368189A JPH02185041A JP H02185041 A JPH02185041 A JP H02185041A JP 368189 A JP368189 A JP 368189A JP 368189 A JP368189 A JP 368189A JP H02185041 A JPH02185041 A JP H02185041A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin
- semiconductor region
- compound semiconductor
- coating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010410 layer Substances 0.000 claims abstract description 131
- 150000001875 compounds Chemical class 0.000 claims abstract description 32
- 239000011247 coating layer Substances 0.000 claims abstract description 27
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 6
- 229910052717 sulfur Inorganic materials 0.000 claims abstract description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 5
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000011593 sulfur Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- 238000007738 vacuum evaporation Methods 0.000 claims description 5
- 238000001771 vacuum deposition Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 11
- 238000007254 oxidation reaction Methods 0.000 abstract description 11
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 10
- 230000000087 stabilizing effect Effects 0.000 abstract description 6
- 239000012212 insulator Substances 0.000 abstract description 5
- 125000004434 sulfur atom Chemical group 0.000 abstract description 5
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 17
- 230000004888 barrier function Effects 0.000 description 14
- 239000000243 solution Substances 0.000 description 11
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- UYJXRRSPUVSSMN-UHFFFAOYSA-P ammonium sulfide Chemical compound [NH4+].[NH4+].[S-2] UYJXRRSPUVSSMN-UHFFFAOYSA-P 0.000 description 10
- 150000004706 metal oxides Chemical class 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 238000001816 cooling Methods 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 239000003507 refrigerant Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010494 dissociation reaction Methods 0.000 description 3
- 230000005593 dissociations Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 229910000951 Aluminide Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052979 sodium sulfide Inorganic materials 0.000 description 1
- GRVFOGOEDUUMBP-UHFFFAOYSA-N sodium sulfide (anhydrous) Chemical compound [Na+].[Na+].[S-2] GRVFOGOEDUUMBP-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産1」J1引肚分I−
本発明は、Ga(ガリウム)を一主成分とする化合物半
導体領域を有する半導体基体の表面に、S(硫黄)の単
原子層レベルの薄層を介して、被覆層が形成された半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for forming a monoatomic layer of S (sulfur) on the surface of a semiconductor substrate having a compound semiconductor region containing Ga (gallium) as a main component. The present invention relates to a method of manufacturing a semiconductor device in which a covering layer is formed through a thin layer of.
来の 術と発明が解決しようとする課題GaAs (砒
化ガリウム)の表面には特有の不安定性があり、GaA
s半導体装置の製品化が期待はどには進展していない一
因となっている。G a A sから成る化合物半導体
領域上に形成されるショットキバリア(金属−半導体整
流障壁)についても。Problems to be solved by recent techniques and inventions The surface of GaAs (gallium arsenide) has a unique instability.
This is one reason why the commercialization of semiconductor devices has not progressed as expected. Also regarding the Schottky barrier (metal-semiconductor rectifying barrier) formed on the compound semiconductor region made of GaAs.
所望のバリアハイドを有するショットキバリアを形成し
たり、逆電流の小さいショットキバリアを再現性よく形
成することが難しかった。It has been difficult to form a Schottky barrier having a desired barrier hydride or to form a Schottky barrier with a small reverse current with good reproducibility.
一方、本願発明者等は、n形GaAg−5iOzlll
(シリコン酸化膜) −AQ (アルミニウム)電極の
系から成るMIS(金属−絶縁物一半導体)構造におい
て、GaAs表面を硫化アンモニウム溶液で処理するこ
とにより、GaAs表面に単原子層レベルのS薄層を形
成すると、良好なMIS特性が得られることを見出した
。また、n形GaAs−AQ電極等から成るショットキ
バリア構造についても、GaAs表面を硫化アンモニウ
ム溶液で処理してGaAs表面にS(硫黄)薄層を形成
すると、良好なショットキバリア特性が得られることを
見出した。また、これらの研究結果を、社団法人応用物
理学会主催の第20同面体素子・材料コンファレンス(
1988年8月24日〜26日開催)等において発表し
た。On the other hand, the inventors of the present application have discovered that n-type GaAg-5iOzllll
(Silicon oxide film) -AQ In a MIS (metal-insulator-semiconductor) structure consisting of an (aluminum) electrode system, by treating the GaAs surface with an ammonium sulfide solution, a thin S layer at a monoatomic layer level is formed on the GaAs surface. It has been found that good MIS characteristics can be obtained by forming a . In addition, for Schottky barrier structures made of n-type GaAs-AQ electrodes, etc., good Schottky barrier properties can be obtained by treating the GaAs surface with an ammonium sulfide solution to form a thin S (sulfur) layer on the GaAs surface. I found it. In addition, these research results were presented at the 20th Isohedral Elements and Materials Conference (sponsored by the Japan Society of Applied Physics).
Held from August 24th to 26th, 1988), etc.
しかしながら、S薄層が単原子層または2原子層程度の
極限的な薄さであるため、S薄層の上面に金属層及び絶
縁層を形成する工程中にS薄層のSがG a A s表
面から解離してしまい、S薄層による表面安定化効果が
損なわれることがある。However, since the S thin layer is extremely thin, on the order of a monoatomic layer or two atomic layers, the S of the S thin layer is formed by Ga A during the process of forming a metal layer and an insulating layer on the top surface of the S thin layer. It may dissociate from the S surface, and the surface stabilizing effect of the S thin layer may be impaired.
そこで1本発明は、上記問題を解決し、S薄層の上面に
金属層又は絶縁層を良好に形成できる半導体装置の製造
方法を提供することを目的とする。Accordingly, one object of the present invention is to provide a method for manufacturing a semiconductor device, which solves the above problems and allows a metal layer or an insulating layer to be satisfactorily formed on the upper surface of the S thin layer.
を ゛するための
本発明による半導体装置の製造方法では、Ga(ガリウ
ム)を一主成分とする化合物半導体領域を有する半導体
基体の化合物半導体領域の表面にS(硫黄)から成る薄
層を形成した後、半導体基体を冷却した状態で薄層の上
面に被覆層を形成する。In the method for manufacturing a semiconductor device according to the present invention for the purpose of Thereafter, a coating layer is formed on the upper surface of the thin layer while the semiconductor substrate is cooled.
また、本発明による半導体装置の製造方法では金属から
成る被覆層を酸化して第1の絶縁層を形成した後に、第
1の絶縁層の上面に更に第2の絶縁層を形成する。Further, in the method for manufacturing a semiconductor device according to the present invention, after forming the first insulating layer by oxidizing the covering layer made of metal, the second insulating layer is further formed on the upper surface of the first insulating layer.
前記の被覆層はその層厚が10人に達するまでは一50
℃以下の温度に冷却した状態において真空蒸着により形
成される。また、第1の絶縁層に変換する金属から成る
被覆層の層厚は300Å以下に形成される。The above-mentioned coating layer has a thickness of 150 until the layer thickness reaches 10.
It is formed by vacuum evaporation in a cooled state to a temperature below .degree. Further, the layer thickness of the coating layer made of metal to be converted into the first insulating layer is formed to be 300 Å or less.
作−一一月一
半導体基体を冷却した状態で、被覆層を形成するので、
化合物半導体領域の表面から解離するS原子が減少する
。被覆層が金属層である場合、被覆層を非常に薄く形成
した後、酸化して金属酸化物層に変換すると、化合物半
導体領域を絶縁物で被覆した構造を形成できる。もちろ
ん、被覆層を金属層として残存させて、ショットキバリ
ア及びオーミック接触を形成する半導体構造の一部に利
用することができる。被覆層が絶縁層の場合には。Production - November 1st The coating layer is formed while the semiconductor substrate is cooled, so
S atoms dissociated from the surface of the compound semiconductor region are reduced. When the covering layer is a metal layer, if the covering layer is formed very thin and then oxidized to convert into a metal oxide layer, a structure in which the compound semiconductor region is covered with an insulator can be formed. Of course, the covering layer can remain as a metal layer and be used as part of a semiconductor structure to form a Schottky barrier and an ohmic contact. When the covering layer is an insulating layer.
被覆層による表面安定化構造及びMIS構造にそのまま
利用できる。It can be used as is for surface stabilization structures and MIS structures using coating layers.
去−JL−例一」1
本発明による半導体装置の製造方法の実施例としてショ
ットキバリアの形成方法を第1図及び第2図に基づいて
説明する。EXAMPLE 1 As an example of the method for manufacturing a semiconductor device according to the present invention, a method for forming a Schottky barrier will be described with reference to FIGS. 1 and 2.
まず、第1図(A)に示すように、GaAsから成るn
形化合物半導体領域(2)を含む半導体基体(1) 、
H,5O4(硫酸) −Hxon (過酸化水素) −
H,O(水)から成るエツチング液及び室温に保持した
濃度1規定の硫化アンモニウムの水溶液を用意する。First, as shown in FIG. 1(A), an n
a semiconductor substrate (1) comprising a shaped compound semiconductor region (2),
H,5O4 (sulfuric acid) -Hxon (hydrogen peroxide) -
An etching solution consisting of H and O (water) and an aqueous solution of ammonium sulfide at a concentration of 1N kept at room temperature are prepared.
化合物半導体領域(2)の不純物濃度は約5×1101
sa″″3である。硫化アンモニウムは化学式(N H
4)a Sで表される標準の化合物に対して約8%のS
を過剰に含み、具体的には化学式:(NH,)、Sx
(x=1.08)で表される硫化アンモニウムである。The impurity concentration of the compound semiconductor region (2) is approximately 5×1101
sa″″3. Ammonium sulfide has the chemical formula (NH
4) a About 8% S relative to the standard compound represented by S
Specifically, the chemical formula: (NH,), Sx
It is ammonium sulfide represented by (x=1.08).
なお、X≧1.02であるのが望ましい。Note that it is desirable that X≧1.02.
次に、化合物半導体領域(2)の表面をH,5O1(硫
酸) −H,O,(過酸化水素)−Hio(水)から成
る溶液で軽くエツチングして清浄化する。Next, the surface of the compound semiconductor region (2) is lightly etched and cleaned with a solution consisting of H, 5O1 (sulfuric acid)-H,O, (hydrogen peroxide)-Hio (water).
清浄化した半導体基体(1)を前記硫化アンモニウムの
溶液中に浸漬する。浸漬時間は数秒〜数時間と幅広く選
択することができる。半導体基体(1)を硫化アンモニ
ウムの溶液から取り出して、化合物半導体領域(2)の
表面にN、(窒素)ガスを吹き付け、付着している溶液
を除去する。この結果、化合物半導体領域(2)の表面
は、約10nm (100人)の厚さを有しかつSを主
成分とするアモルファス状の被膜で被覆される。続いて
、半導体基体(1)を真空中(減圧雰囲気中)に約30
分間放置すると、このアモルファス状の被膜はほとんど
消失する。得られた化合物半導体領域(2)の表面には
、第1図(B)に示すように、Ga及びAsと結合状態
にあるS薄層(3)が形成されている。オージェ電子分
光法による観測によれば、S薄層(3)は硫化アンモニ
ウムを構成するSがGaAs表面に吸着されて単原子層
又は2原子層程度の極限的な薄さで残存している。なお
、S薄層(3)を得るには、硫化アンモニウム溶液の浸
漬の後に、この溶液を純水で急激に薄めるなどの他の適
切な方法を採用してもよい。The cleaned semiconductor substrate (1) is immersed in the ammonium sulfide solution. The immersion time can be selected from a wide range of seconds to several hours. The semiconductor substrate (1) is taken out of the ammonium sulfide solution, and N, (nitrogen) gas is blown onto the surface of the compound semiconductor region (2) to remove the adhering solution. As a result, the surface of the compound semiconductor region (2) is coated with an amorphous film having a thickness of approximately 10 nm (100 nm) and containing S as a main component. Subsequently, the semiconductor substrate (1) was placed in a vacuum (in a reduced pressure atmosphere) for about 30 minutes.
When left for a minute, this amorphous film almost disappears. As shown in FIG. 1(B), a thin S layer (3) bonded to Ga and As is formed on the surface of the obtained compound semiconductor region (2). According to observation by Auger electron spectroscopy, S in the S thin layer (3), which constitutes ammonium sulfide, is adsorbed on the GaAs surface and remains in the extremely thin layer of about a monoatomic layer or a diatomic layer. Note that in order to obtain the S thin layer (3), other suitable methods may be employed, such as dipping the ammonium sulfide solution and then rapidly diluting this solution with pure water.
更に、第2図に模式的に示す超高真空タイプの真空蒸着
装置を使用して、第1図(C)に示すように、Sw層(
3)の上面にAΩから成る金属層(被覆層)(4)を設
けて、ショットキバリアを形成する0本実施例で使用す
る真空蒸着装置は、ベル形の真空容器(ペルジャー)(
5)、内部に温度調整用のヒーター(図示せず)を内蔵
する支持台(6)、支持台(6)に隣接する冷媒用の収
容器(7)、冷媒用収容器(7)に通じる導入路(8)
と排出路(9)、ボート形蒸発皿(10)。Furthermore, using an ultra-high vacuum type vacuum evaporation apparatus schematically shown in FIG. 2, a Sw layer (
3) A metal layer (coating layer) (4) made of AΩ is provided on the upper surface to form a Schottky barrier.
5), a support stand (6) with a built-in heater for temperature adjustment (not shown), a refrigerant container (7) adjacent to the support stand (6), and a refrigerant container (7) connected to the refrigerant container (7). Introductory path (8)
and a discharge channel (9), and a boat-shaped evaporation dish (10).
及び電子銃(11)を有する。支持台(6)と収容器(
7)とで冷却器(13)が構成されている。and an electron gun (11). Support stand (6) and container (
7) constitute a cooler (13).
金属層(4)を形成するときは、第1図(B)に示すS
薄層(3)を有する半導体基体(1)の一方の主面〔S
薄層(3)の形成された主面〕を蒸発皿(10)側に向
けて支持台(6)に半導体基体(1)を取付ける。ペル
ジャー(5)内の気圧はI X 10”’Torr以上
に減圧されており、金属層(4)を形成する蒸着源とし
ての/l板材(12)がボート形蒸発皿(10)内に配
置されている0本実施例では、半導体基体(1)を冷却
した状態で金属層(4)を形成するため、冷媒用の収容
器(7)に支持台(6)が取付けられている。導入路(
8)を通じて収容器(7)に液体窒素を導入すると、支
持台(6)を介して収容器(7)に接する半導体基体(
1)は−100℃以下、例えば約−150℃の低温に冷
却される。この状態で、電子銃(11)から照射される
電子ビームによりAQ板材(12)の表面を加熱すると
。When forming the metal layer (4), the S shown in FIG.
One main surface of the semiconductor substrate (1) having a thin layer (3) [S
The semiconductor substrate (1) is mounted on the support base (6) with the main surface on which the thin layer (3) is formed facing the evaporation dish (10). The pressure inside the Pelger (5) is reduced to more than I x 10'' Torr, and the /l plate material (12) serving as the evaporation source for forming the metal layer (4) is placed in the boat-shaped evaporation dish (10). In this embodiment, in order to form the metal layer (4) in a cooled state of the semiconductor substrate (1), a support stand (6) is attached to the refrigerant container (7).Introduction Road (
When liquid nitrogen is introduced into the container (7) through the support base (6), the semiconductor substrate (
1) is cooled to a low temperature of -100°C or lower, for example about -150°C. In this state, the surface of the AQ plate material (12) is heated by the electron beam irradiated from the electron gun (11).
AQ板材(12)から蒸発したAΩがS薄層(3)の上
面に被着する。なお、収容器(7)内で気化する窒素ガ
スは排出路(9)を通じて真空蒸着装置の外部に排出さ
れる。また、半導体基体(1)の温度調整は主として支
持台(6)に内蔵されたヒーター(図示せず)によって
行う。AΩ evaporated from the AQ plate material (12) adheres to the upper surface of the S thin layer (3). Note that the nitrogen gas vaporized within the container (7) is discharged to the outside of the vacuum evaporation apparatus through the discharge path (9). Further, the temperature of the semiconductor substrate (1) is mainly controlled by a heater (not shown) built into the support base (6).
以上により、S薄層(3)の上面に厚さ約2μmの金属
層(4)が形成され、金属層(4)と化合物半導体領域
(2)との間にショットキバリアが形成される。なお、
第1図(C)ではS薄層(3)が第1図(B)の状態の
ままで存在するように便宜的に描いているが、S薄層(
3)は極薄の膜であるから、第1図(C)の状態でS薄
層(3)が実際にどのような形で存在するかは明確では
ない。Through the above steps, a metal layer (4) with a thickness of approximately 2 μm is formed on the upper surface of the S thin layer (3), and a Schottky barrier is formed between the metal layer (4) and the compound semiconductor region (2). In addition,
In FIG. 1(C), the S thin layer (3) is depicted as existing as it is in the state shown in FIG. 1(B) for convenience, but the S thin layer (
3) is an extremely thin film, so it is not clear in what form the S thin layer (3) actually exists in the state shown in FIG. 1(C).
本実施例では、真空蒸着の際の半導体基体(1)の冷却
により化合物半導体領域(2)の表面に被着したS原子
の解離が減少し、S薄層(3)による化合物半導体領域
(2)の表面安定化効果が良好かつ確実に発揮される。In this example, cooling of the semiconductor substrate (1) during vacuum deposition reduces the dissociation of S atoms deposited on the surface of the compound semiconductor region (2), and the thin S layer (3) reduces the dissociation of S atoms deposited on the surface of the compound semiconductor region (2). ) The surface stabilizing effect is well and reliably exhibited.
したがって、バリアハイドφbnはAJの仕事関数を比
較的忠実に反映した値(φbn40.4aV)となり、
また、逆方向電流の小さいショットキバリアを形成でき
る。Therefore, barrier hide φbn has a value (φbn40.4aV) that relatively faithfully reflects the work function of AJ,
Furthermore, a Schottky barrier with a small reverse current can be formed.
スー」L−一一」2
次に1本発明の第2の実施例としてMIS構造の形成方
法を第3図に基づいて説明する。Next, as a second embodiment of the present invention, a method for forming an MIS structure will be described with reference to FIG.
まず、実施例1と同様にして化合物半導体領域(2)の
表面に極薄のS薄層(3)が形成された半導体基体(1
)を用意した後、第3図(A)に示すように、S薄層(
3)の上面にAIから成る金属層(被覆層)(21)を
形成する。金属層(21)は実施例1と同様に、半導体
基体(1)を−ioo℃以下、例えば約−150℃の低
温に冷却した状態でAllを真空蒸着して形成する。た
だし、実施例2では、金属層(21)の層厚は実施例1
に比べて著しく薄く、約100人となっている。First, in the same manner as in Example 1, a semiconductor substrate (1) with an extremely thin S thin layer (3) formed on the surface of a compound semiconductor region (2).
), as shown in Figure 3(A), a thin S layer (
3) A metal layer (coating layer) (21) made of AI is formed on the upper surface. Similarly to Example 1, the metal layer (21) is formed by vacuum evaporating All on the semiconductor substrate (1) while cooling it to a low temperature of -ioo°C or lower, for example, about -150°C. However, in Example 2, the layer thickness of the metal layer (21) is
There are only about 100 people, which is significantly thinner than the previous year.
次に、第3図(B)に示すように、金属層(21)が形
成された第3図(A)に示す半導体基体(1)を、空気
中で350℃程度の温度に加熱して。Next, as shown in FIG. 3(B), the semiconductor substrate (1) shown in FIG. 3(A) on which the metal layer (21) has been formed is heated to a temperature of about 350° C. in air. .
金属層(21)を熱酸化する。これにより、金属層(2
1)は第1の絶縁層として絶縁物であるAQsOsC酸
化アルミニウム)から成る金属酸化物層(22)に変わ
る。なお、熱酸化工程ではS薄層(3)の上面に金属層
(21)が密着して形成されているので、加熱によって
SR子が化合物半導体領域(2)の表面から実質的に解
離しない。The metal layer (21) is thermally oxidized. As a result, the metal layer (2
1) is changed to a metal oxide layer (22) made of an insulator (AQsOsC aluminum oxide) as the first insulating layer. In the thermal oxidation step, since the metal layer (21) is formed in close contact with the upper surface of the S thin layer (3), the SR element is not substantially dissociated from the surface of the compound semiconductor region (2) by heating.
したがって、S薄層(3)の表面安定化効果は損なわれ
ない。Therefore, the surface stabilizing effect of the S thin layer (3) is not impaired.
次に、第3図(C)に示すように、金属酸化物層(22
)の上面に周知のプラズマCVD(Chamical
Vapor Deposition)または光CVD法
によって8108膜(シリコン酸化膜)(23)を約0
゜1μmの厚さに形成する。Sin、膜(23)を形成
せずに金属酸化物層(22)のみから成る絶縁膜として
もよいが、第1の絶縁層としての金属酸化物層(22)
と第2の絶縁層としてのSin、l1l(23)の2層
から成る絶縁膜とした方が良好な絶縁膜を形成すること
ができる。プラズマCVDにおいて半導体基体(1)は
350℃程度の温度に加熱されるが、S薄層(3)の上
面には金属酸化物層(22)が形成されているので、上
記熱酸化工程と同様に問題は生じない。Next, as shown in FIG. 3(C), a metal oxide layer (22
) on the top surface of the well-known plasma CVD (Chamical
The 8108 film (silicon oxide film) (23) is deposited to approximately 0% by vapor deposition or photo-CVD method.
゜It is formed to a thickness of 1 μm. Although the insulating film may be made of only the metal oxide layer (22) without forming the film (23), the metal oxide layer (22) may be used as the first insulating layer.
A better insulating film can be formed by forming an insulating film consisting of two layers: and a second insulating layer of Sin and l1l (23). In plasma CVD, the semiconductor substrate (1) is heated to a temperature of about 350°C, but since a metal oxide layer (22) is formed on the upper surface of the S thin layer (3), the process is similar to the thermal oxidation process described above. There is no problem.
続いて、第3図(D)に示すように、SiO□膜(23
)の上面にAQから成る厚さ約2μmの金属層(24)
を周知の真空蒸着法によって形成する。金属Jlill
(24)の真空蒸着は半導体基体(1)の冷却を行わ
ない一般的な方法であるが、S薄層(3)の上面には金
属酸化物層(22)及びSio2膜(23)から成る絶
縁膜が形成されているので、上記酸化工程と同様に問題
は生じない。Subsequently, as shown in FIG. 3(D), a SiO□ film (23
) on the top surface of the metal layer (24) made of AQ and having a thickness of approximately 2 μm.
is formed by a well-known vacuum evaporation method. metal jlill
Vacuum deposition of (24) is a general method that does not involve cooling the semiconductor substrate (1), but the upper surface of the S thin layer (3) is composed of a metal oxide layer (22) and an Sio2 film (23). Since an insulating film is formed, no problem arises as in the oxidation process described above.
以上のように形成されたMIS構造においては、SUM
(3)からのS原子の解離を最小限に抑えつつS薄層
(3)の上面に絶縁膜及び金属層を形成することができ
るから、S薄層(3)による表面安定化効果が良好に保
持されており、良好なMIs特性が得られる。In the MIS structure formed as described above, SUM
Since the insulating film and metal layer can be formed on the top surface of the S thin layer (3) while minimizing the dissociation of S atoms from the S layer (3), the surface stabilization effect of the S thin layer (3) is good. It is possible to obtain good MIs characteristics.
斐−夏一握 本発明の上記実施例は種々の変更が可能である。Hi - A handful of summer Various modifications can be made to the above-described embodiments of the invention.
例えば、S薄層(3)を形成するには、実施例1及び2
のように硫化アンモニウムの溶液処理を利用する方法が
好適である。しかし、硫化ナトリウム等他の溶液処理を
利用する方法によってS薄層(3)を形成してもよい。For example, to form the S thin layer (3), Examples 1 and 2
A method using ammonium sulfide solution treatment is preferred. However, the S thin layer (3) may also be formed by a method using other solution treatments such as sodium sulfide.
また、8w1層(3)による表面安定化効果は。Also, the surface stabilizing effect of the 8w1 layer (3) is as follows.
G a A sに代表されるGaを一生成分とする■−
■族化合物半導体(GaAs、GaP (燐化ガリウム
)、GaAsP (燐化砒化ガリウム) 、 GaA
11 As(砒化アルミ化ガリウム)など〕に有効であ
るから、化合物半導体領域(2)がこれらの化合物半導
体であってもよい。- Contains Ga, represented by Ga As, as a lifelong component.
Group II compound semiconductors (GaAs, GaP (gallium phosphide), GaAsP (gallium arsenide phosphide), GaA
11 As (gallium aluminide arsenide), etc., the compound semiconductor region (2) may be made of these compound semiconductors.
更に、半導体基体(1)の冷却は、被覆層を形成する初
期の段階が特に重要である。この初期の段階とは、経験
的に被覆層が10人程度の厚さに形成されるまでの期間
である。したがって、被覆層が10人、望ましくは50
人の厚さに形成されるまで、半導体基体(1)の全体的
な温度が一50℃程度以下、望ましくは一100℃以下
の温度になるように冷却して被覆層を形成すると良い。Furthermore, cooling of the semiconductor substrate (1) is particularly important at the initial stage of forming the coating layer. This initial stage is the period until the coating layer is formed to a thickness of about 10 layers according to experience. Therefore, the coating layer is 10 people, preferably 50 people.
It is preferable to form the coating layer by cooling the semiconductor substrate (1) so that the overall temperature of the semiconductor substrate (1) is about 150° C. or less, preferably about 1100° C. or less, until the coating layer is formed to a human thickness.
これにより、S薄層から5J7i子が解離するのを防止
する効果が顕著になる。初期の段階を経過した後は、同
一の温度又はより高い温度で継続的に被覆層を形成する
ことができる。As a result, the effect of preventing the 5J7i molecules from dissociating from the S thin layer becomes significant. After the initial stage, the coating layer can be formed continuously at the same temperature or at a higher temperature.
被覆層は、必要に応じて種々の材料を選択できる0例え
ば1石英及びアルミナを蒸着源として真空蒸着したSi
n、膜またはAfi、Ga膜のような絶縁層であっても
よい、ただし、金属層は絶縁層に比べるとマイグレーシ
蕊ン(構成原子の移動)が起こり易いので、低温の表面
に比較的良好な膜質の層を形成し易い点で、被覆層が金
属層である方が製造条件を容易に設定できる。なお、絶
縁層に変換する金属層としては、酸化して絶縁物に変換
され易いことが必要であり、AQ及びTa(タンタル)
が好適である。For the coating layer, various materials can be selected as required.For example, Si is vacuum-deposited using quartz and alumina as a deposition source.
It may be an insulating layer such as n, film or Afi, Ga film. However, since metal layers are more prone to migration (movement of constituent atoms) than insulating layers, they are relatively suitable for low-temperature surfaces. Since it is easier to form a layer with a good film quality, it is easier to set the manufacturing conditions when the coating layer is a metal layer. Note that the metal layer to be converted into an insulating layer must be easily oxidized and converted into an insulator, and AQ and Ta (tantalum)
is suitable.
実施例2のように金属層(21)を酸化して金属酸化物
層(22)を作成するときは、酸化を容易にするために
金属層(21)の層厚を300人程程度下とするのが実
用的である。また、S薄層(3)を確実に被覆するため
に10Å以上とするのが実用的である。金属層(21)
の酸化方法は、熱酸化、プラズマ酸化、陽極酸化などを
適宜選択すればよい、金属層(21)が10人程度に極
薄であれば自然酸化またはこれに近い軽い熱酸化でよい
。When creating the metal oxide layer (22) by oxidizing the metal layer (21) as in Example 2, the thickness of the metal layer (21) is reduced by about 300 mm to facilitate oxidation. It is practical to do so. Further, in order to reliably cover the S thin layer (3), it is practical to set the thickness to 10 Å or more. Metal layer (21)
The oxidation method may be appropriately selected from thermal oxidation, plasma oxidation, anodic oxidation, etc. If the metal layer (21) is extremely thin, about 10 layers, natural oxidation or similar light thermal oxidation may be used.
A浬Rす1果
以上のように、本発明によれば、化合物半導体領域の表
面に形成したS薄層の上に、SUNの表面安定化効果を
実質的に損なうことなく被覆層を形成できる。したがっ
て、ショットキバリア及びオーミック接触、更には絶縁
物被覆による表面保護構造及びMIS構造をそれぞれ良
好な特性を有するように形成でき、化合物半導体を用い
た半導体装置の特性向上及び製造歩留まりの向上に寄与
する。As described above, according to the present invention, a coating layer can be formed on the S thin layer formed on the surface of a compound semiconductor region without substantially impairing the surface stabilizing effect of SUN. . Therefore, the Schottky barrier and ohmic contact, as well as the surface protection structure and MIS structure using an insulator coating, can be formed to have good characteristics, respectively, and contribute to improving the characteristics and manufacturing yield of semiconductor devices using compound semiconductors. .
第1図は本発明の一実施例による半導体装置の製造方法
を示す工程図、第2図は模式的に示す超高真空タイプの
真空蒸着装置の断面図、第3図は本発明の他の実施例に
よる半導体装置の製造方法を示す工程図である。
(1)、、半導体基体、 (2)、、化合物半導体領
域、 (3)、、S薄層、(4)、(21)0.金属
層(被覆層)、 (13)、、冷却器、 (22
)、、金属酸化物層(第1の絶縁層)(23)、、シリ
コン酸化膜(第2の絶縁層)特許出願人 サンケーン電
気株式会社
(ほか1名)
代 理 人 清水陽ゴト(はが1名)
\1 、 ′
第1図
第2因FIG. 1 is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view of an ultra-high vacuum type vacuum evaporation apparatus, and FIG. 3 is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a process diagram showing a method for manufacturing a semiconductor device according to an example. (1), Semiconductor substrate, (2), Compound semiconductor region, (3), S thin layer, (4), (21)0. Metal layer (coating layer), (13), Cooler, (22
), Metal oxide layer (first insulating layer) (23), Silicon oxide film (second insulating layer) Patent applicant Sunken Electric Co., Ltd. (and one other person) Agent Yogo Shimizu (Haga 1 person) \1、′ Figure 1 2nd cause
Claims (5)
領域を有する半導体基体の前記化合物半導体領域の表面
にS(硫黄)から成る薄層を形成した後、前記半導体基
体を冷却器に取付けることにより前記半導体基体を冷却
した状態で前記薄層の上面に被覆層を形成することを特
徴とする半導体装置の製造方法。(1) After forming a thin layer made of S (sulfur) on the surface of the compound semiconductor region of a semiconductor substrate having a compound semiconductor region containing Ga (gallium) as a main component, attaching the semiconductor substrate to a cooler. A method of manufacturing a semiconductor device, characterized in that a coating layer is formed on the upper surface of the thin layer while the semiconductor substrate is cooled.
体素子を−50℃以下に冷却した状態において真空蒸着
により前記被覆層を形成する請求項(1)に記載の半導
体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the coating layer is formed by vacuum evaporation while the semiconductor element is cooled to −50° C. or lower until the coating layer reaches a thickness of 10 Å.
領域を有する半導体基体の前記化合物半導体領域の表面
にS(硫黄)から成る薄層を形成した後、前記半導体基
体を冷却した状態で前記薄層の上面に金属から成る被覆
層を形成し、該被覆層を酸化して第1の絶縁層を形成し
た後に、該第1の絶縁層の上面に更に第2の絶縁層を形
成することを特徴とする半導体装置の製造方法。(3) After forming a thin layer of S (sulfur) on the surface of the compound semiconductor region of a semiconductor substrate having a compound semiconductor region containing Ga (gallium) as a main component, the semiconductor substrate is cooled and Forming a covering layer made of metal on the upper surface of the thin layer, oxidizing the covering layer to form a first insulating layer, and then further forming a second insulating layer on the upper surface of the first insulating layer. A method for manufacturing a semiconductor device, characterized by:
体素子を−50℃以下に冷却した状態において真空蒸着
により前記被覆層を形成する請求項(3)に記載の半導
体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 3, wherein the covering layer is formed by vacuum deposition while the semiconductor element is cooled to -50°C or lower until the thickness of the covering layer reaches 10 Å.
3)又は(4)に記載の半導体装置の製造方法。(5) The layer thickness of the coating layer is 300 Å or less (
3) or the method for manufacturing a semiconductor device according to (4).
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JP368189A JP2764595B2 (en) | 1989-01-12 | 1989-01-12 | Method for manufacturing semiconductor device |
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JP2764595B2 JP2764595B2 (en) | 1998-06-11 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03261147A (en) * | 1990-03-12 | 1991-11-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device, and method and apparatus for manufacturing semiconductor device |
-
1989
- 1989-01-12 JP JP368189A patent/JP2764595B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03261147A (en) * | 1990-03-12 | 1991-11-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device, and method and apparatus for manufacturing semiconductor device |
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