JPH02184109A - Delay circuit - Google Patents

Abstract

PURPOSE:To simply obtain a delay signal with a desired delay by forming plural delay signals whose delay time differs with respect to an input signal with a delay means and outputting selectively them via a gate circuit. CONSTITUTION:An input signal Din is fed in common to each one input of AND gates G1-G5, and inverter circuits IV are connected in cascade with outputs of the AND gates G2-G5. The AND gates G1-G5 are configurated with components of the same constitution and similarly each inverter circuit is configurated with components of the same constitution. Thus, delay signals N1-N4 are signals having sequentially larger delays like T, 2T, 3T and 4T, where T is a unit delay time being a signal propagation delay time of two inverter circuits connected in cascade. Thus, a delay signal with a desired delay is simply obtained by selecting the gate circuits G2-G5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit, and relates to a technique effective for use in a delay circuit used in, for example, a hard disk driver (HDD).

[Conventional technology]

A hard disk driver circuit requires several types of delay signals (clocks) for phase compensation during writing. In order to obtain such a delayed signal, a modularized delay line as shown in FIG. 7 is prepared. Regarding a magnetic disk driver circuit incorporating a write compensation circuit, there is, for example, Japanese Patent Application No. 63-102511.

[Problem to be solved by the invention]

In the above delay line, multiple delay outputs 01 to 0
8, select one that matches the specifications of the circuit in which it will be installed and connect it to the corresponding device.

Therefore, if the specifications change in the amount of delay mentioned above, it is necessary to reselect the delay signal and connect it to the device accordingly, or to replace the delay line itself if it does not match the desired amount of delay even after reselecting the output. be. For this reason, there are problems in that the number of parts constituting the system increases, and the amount of assembly work associated with changes in specifications and the like increases.

An object of the present invention is to provide a delay circuit in which the setting of the delay amount can be easily changed.

Another object of the invention is to provide a delay circuit suitable for semiconductor integrated circuits.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the delay means forms a plurality of delayed signals each having a different delay time with respect to the input signal, and the delayed signals are selectively outputted via the gate circuit.

[For production]

According to the above-described means, a delayed signal having a desired amount of delay can be easily obtained by switching the gate circuits.

[Embodiment 1] FIG. 1 shows a logic circuit diagram of an embodiment of a delay circuit according to the present invention. The logic gate circuit shown in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The input signal Din is commonly supplied to one input of the AND gate circuits G1 to G5.

The AND gate circuit G1 is an OR gate circuit G6 that outputs the human input signal Din as it is by constantly supplying a high level (“H”) to the other input terminal.
It is output as an output signal E through. This signal E is
If the signal propagation delay time of the AND gate circuit G1 and OR gate circuit G6 is ignored, then becomes the same signal as the input signal Din.

An inverter circuit I is connected to the output side of the AND gate circuit G2.
Two Vs are connected in tandem. This causes the delay signal N
1 is formed. On the output side of the AND gate circuit G3,
Inverter circuit [4 Vs are connected in cascade. This forms the delayed signal N2. AND gate circuit G
Six inverter circuits IV are connected in tandem to the output side of No. 4. This forms the delayed signal N3. Eight inverter circuits IV are connected in series to the output side of the AND gate circuit G5. This forms the delayed signal N4.

Each of the AND gate circuits G1 to G5 is composed of elements having the same configuration, and similarly, each inverter circuit is also composed of elements having the same configuration. Therefore, if the signal propagation delay time of two cascaded inverter circuits is a unit delay time T, each of the delayed signals N1 to N4 is a signal having a sequentially large delay amount such as T, 2T, 3T, and 4T. Ru. It is assumed that the signal propagation delay times of the AND gate circuits G1 to G5 and the OR gate circuit G7 described below are negligibly short with respect to the signal propagation delay time T of the inverter circuit. Each of the above delayed signals N1 to N4 is
It is output as an output delay signal N via the OR gate circuit G7.

On the other hand, the output delay signal N is commonly supplied to one input of the AND gate circuits G8 to Gll similar to the above. A delay circuit consisting of an inverter circuit similar to the above is provided at the output of each of the AND gate circuits G8 to Gll, and delayed signals Ll, L2, L3 and L4 are formed from each of them. These delayed signals L1, L2, L3
Similarly to the above, if the signal propagation delay time of two cascaded inverter circuits is the unit delay time T, then L4 is a signal having successively larger delay amounts such as T, 2T, 3T, and 4T with respect to the input signal N. It is said that These delayed signals L to L4 are outputted as output delayed signals via the OR gate circuit G12.

Note that, similarly to the above, for the signal propagation delay time T, the AND gate circuits G8 to Gll and the OR gate circuit G12
It is assumed that the signal propagation delay time is negligibly short.

The above AND gate circuits G2 to G5 and G8 to Gl
The remaining two input terminals of l are provided with selection signals SLA and SLB consisting of 2 bits, and inverter circuits IVI and IV2.
and the inverted signal formed by are combined and supplied as follows.

For example, an AND gate circuit G2 selects the delayed signal N1 with the shortest delay time T with respect to the input signal Din, and an AND gate circuit G8 selects the delayed signal L1 with the shortest delay time T with respect to the delayed signal N. The remaining two terminals are supplied with selection signals SLA and SLB that are inverted by inverter circuits IV1 and IV2, respectively.

AND gate circuit G3 which selects the delayed signal N2 having the second shortest delay time 2T with respect to the input signal Din, and AND gate which selects the delayed signal L2 which has the second shortest delay time 2T with respect to the delayed signal N. The remaining two terminals of the circuit G9 are supplied with a selection signal SLA and a selection signal SLB inverted by an inverter circuit IVI, respectively.

AND gate circuit G4 which selects the delayed signal N3 having the third shortest delay time 3T with respect to the input signal Din, and AND gate which selects the delayed signal L3 which has the third shortest delay time 3T with respect to the delayed signal N. The remaining two terminals of the circuit GIO are supplied with the selection signal SLA and the selection signal SLB inverted by the inverter circuit IV2, respectively.

And the longest delay time 4T with respect to the input signal Din
an AND gate circuit G5 that selects a delayed signal N4 that is assumed to be
The remaining two terminals of the AND gate circuit Gll, which selects the delayed signal L4 having the longest delay time 4T with respect to the delayed signal N, are supplied with selection signals SLA and SLB, respectively.

The four AND gate circuits G2 to C5 and C8 to Gll each perform a decoding operation of selecting the delay signals Nl to N4 and Ll to L4 by regarding the selection signals SLA and SLB as two-bit binary numbers. conduct.

FIG. 2 shows a waveform diagram for explaining an example of the operation of the delay circuit.

For example, when selection signals SLA and SLB are both low level (logic "0"), the output signals of inverter circuits IVI and IV2 become high level, and AND gate circuits G2 and C8
opens the gate (.As a result, the input signal Din is made into the delayed signal N1 delayed by the signal propagation delay time T through the AND gate circuit G2 and the two delay inverter circuits, and is output as the output signal N through the OR gate circuit G7. Further, this delayed output signal N is made into a delayed signal L1 delayed by the signal propagation delay time T through an AND gate circuit G8 and two delay inverter circuits,
It is output as an output signal through the OR gate circuit G12.

When the selection signal SLB is changed from low level to high level from this state, AND gate circuits G3 and C9 open the gates instead of AND gate circuits G2 and C8. As a result, the input signal Din is made into a delayed signal N2 delayed by the signal propagation delay time 2T through the AND gate circuit G3 and the four delay inverter circuits, and is output as the output signal N through the OR gate circuit G7. Further, this delayed output signal N passes through an AND gate circuit G9 and four delay inverter circuits for a signal propagation delay time of 2T.
The delay signal L2 is delayed by
It is output as an output signal through 12.

Next, when the selection signal SLB is changed from high level to low level and the selection signal SLA is changed from low level to high level, AND gate circuits G4 and GlO open the gates instead of AND gate circuits G3 and C9. As a result, the input signal Din is made into a delayed signal N3 delayed by the signal propagation delay time 3T through the AND gate circuit G4 and six delay inverter circuits, and is output as the output signal N through the OR gate circuit G7. Further, this delayed output signal N passes through an AND gate circuit GIO and six delay inverter circuits for a signal propagation delay time of 3.
The delayed signal L3 is delayed by T, and is outputted as an output signal through the OR gate circuit 012.

Although not shown, when the selection signals SLA and SLB are both set to high level, the AND gate circuits G4 and G
Instead of IO, AND gate circuits G5 and Gll open the gates. As a result, the input signal Din is made into a delayed signal N4 delayed by the signal propagation delay time 4T through the AND gate circuit G5 and eight delay inverter circuits, and is output as the output signal N through the OR gate circuit G7.

Further, this delayed output signal N is output from the AND gate circuit Gll.
The delayed signal L4 is delayed by the signal propagation delay time 4T through eight delay inverter circuits, and is output as an output signal through the OR gate circuit G12.

Therefore, the selection signal SLA,! : By changing the SLB settings, the delay time for the human signal Din becomes E<
The relationship N<L can be easily changed to the relationship E<N<L.

[Embodiment 2] FIG. 3 shows a circuit diagram of another embodiment of the delay circuit.

In this embodiment, a conventional delay line is used instead of the above-mentioned configuration using a delay inverter circuit. However, the difference from conventional delay circuits is that instead of outputting the delayed signals obtained from each tap of the delay line as they are through a Banfa amplifier, a logic gate circuit consisting of NAND gate circuits G21 to G28 and their output signals are used. An output selection circuit consisting of a Nant gate circuit G29 acting as an OR circuit receiving the input signal is provided.

The remaining three input terminals of the Nant gate circuits G21 to G28 are caused to perform a 1/8 decoding operation from the combination of selection signals SLO to SL2 and inverted signals formed by inverter circuits IVIO to IV12. In this configuration, the input terminal IN and output terminal OUT are fixedly connected to the device that requires the delay circuit as described above, and when the delay time specifications change, the connection is not changed but the selection is made. Since it is only necessary to change the combination of signals SLO to SL2, the delay time setting can be easily changed.

[Embodiment 3] FIG. 4 shows a schematic block diagram of an embodiment of a hard disk driver (hereinafter simply referred to as HDD) circuit in which the delay circuit DLY according to the present invention is used.

The HDD circuit is composed of a semiconductor integrated circuit, as shown by the broken line in the figure, and includes an encoder EC, a clock pulse generation circuit CPG, a clock selector SEL, and a D-type flip-flop circuit FF that forms a write phase compensation signal CWD. There is.

The delay circuit DLY is composed of a delay circuit similar to the embodiment shown in FIG.
is supplied, and three output signals E with different amounts of delay are provided.
, outputs N and L.

These output signals E, N and L are sent to the clock selector S
Manpower is provided by EL.

The write data WD output from the encoder EC is
It is supplied to the data terminal of the flip-flop circuit FF. A delay signal selected by a clock selector SEL is supplied to a clock terminal of the flip-flop circuit FF. As a result, the write data WD is outputted from the delay circuit DLY from the output Q of the flip-flop circuit FF, and the clock signal E is outputted from the output Q of the flip-flop circuit FF, each having a different amount of delay.

A phase compensation write signal CW synchronized with a clock pulse selected from N and L by a clock selector SEL.
D is output. Since the amount of delay for this phase compensation depends on the performance of the magnetic disk, it is necessary to set the amount of delay in accordance with the device. That is, the fourth
As shown in the timing diagram of the figure, the selection signal SLA,
! :5LB (omitted in the figure), the write signal CWD formed in synchronization with clock pulse E can be changed into one synchronized with clock pulse L without changing the connection of the delay circuit. Can be changed. As described above, since the setting of the delay amount of the delay circuit DLY can be changed by software using the selection signals SLA, SLB, etc., it is easy to set and adjust the delay time according to user specifications.

[Embodiment 4] FIG. 6 shows a hard disk driver (hereinafter simply referred to as HDD) in which the delay circuit DLY according to the present invention is used.
A schematic block diagram of another embodiment of the circuit is shown.

In this embodiment, a delay circuit D as in the embodiment of FIG.
When L Y is used, both the delay means and the gate means can be constructed in a semiconductor integrated circuit, so the delay circuit DLY itself is built into the semiconductor integrated circuit constituting the HDD circuit. That is, encoder EC and clock pulse generation circuit CPG.

Clock selector SEL and write phase compensation signal CW
A delay circuit DLY as shown in FIG. 1 is built into a semiconductor integrated circuit for an HDD, which is composed of a D-type flip-flop circuit FF and the like.

In this configuration, selection signals SLA and SLB for setting the amount of delay are supplied from external terminals. This allows HD
The number of external terminals of the semiconductor integrated circuit device constituting the D circuit and the number of external parts connected thereto can be reduced.

Note that the delay circuit DLY is connected to the input terminal (D
in) is supplied with the clock pulse CKO generated by the clock pulse generation circuit CPG, which is applied to the selection signal S.
3 with the amount of delay specified by LA and SLB, respectively.
The three output signals E, N and L are input to the clock selector SEL. The other configurations are the same as those of the embodiment shown in FIG. 4, so the explanation will be omitted.

Selection of the amount of delay by the logic gate circuit described above not only benefits the user using the delay circuit, but also
It also brings the following advantages to the manufacturers who manufacture it. For example, if there are large manufacturing variations within the manufacturing process of delay elements and it is difficult to control the absolute value of the delay amount, it is possible to adjust the delay amount using a logic gate circuit. The device can be adjusted before shipping and shipped as a product with uniform quality. As means for this, in addition to selecting the delay amount using the logic gate circuit described above, fine adjustment of the delay amount using an aluminum master slice, combination with a programmable logic array (PLA), etc. can be considered.

The effects obtained from the above embodiments are as follows. That is, (1) By forming a plurality of delayed signals with different delay times for the input signal using the delay means and selectively outputting them through the gate circuit, The effect is that a delayed signal having a desired amount of delay can be easily obtained.

(2) By using a logic gate such as an inverter circuit as the delay means, it is possible to obtain the effect that the delay circuit can be configured into a one-chip semiconductor integrated circuit.

(3) According to (2) above, the delay circuit itself can be incorporated in a semiconductor integrated circuit that requires a delay circuit, and the number of components and terminals can be reduced.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, in the embodiment shown in FIG. 1, delayed signals N1 and L1 are input to two inverter circuits connected in series via an AND gate circuit to form delayed signals N2 and L2. Similarly, the delayed signals N2 and L2 formed above may be input to two inverter circuits connected in series via an AND gate circuit to form the delayed signals N3 and L3. good. By adopting such a configuration, the number of inverter circuits forming the delay means can be significantly reduced.

Further, the logic gate circuit for selecting the delayed signal can be replaced with a transmission gate MO3FET.

The above delay inverter circuit and logic gate circuit are CM
It may be anything, such as an O3 (complementary MOS), a bipolar transistor, or a Bi-0M03 circuit. The settable delay time is not limited to the above embodiments, and various embodiments can be adopted as necessary.

The present invention can be widely used not only for HDD but also as a delay circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by forming a plurality of delayed signals each having a different delay time with respect to the input signal using the delay means and selectively outputting the delayed signals through the gate circuit, it is possible to easily obtain the desired signal by switching the gate circuit. It is possible to obtain a delayed signal with a delay amount of .

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing an embodiment of the delay circuit according to the present invention, FIG. 2 is a waveform diagram for explaining an example of its operation, and FIG. 3 is a logic circuit diagram showing an example of the delay circuit according to the present invention. A logic circuit diagram showing another embodiment, FIG. 4 shows an HDD in which the delay circuit according to the present invention is used.
FIG. 5 is a block diagram showing one embodiment of the circuit, FIG. 5 is a timing diagram for explaining an example of its operation, and FIG. 6 is a block diagram showing an HDD in which the delay circuit according to the present invention is used.
FIG. 7, a block diagram showing another embodiment of the circuit, is a circuit diagram showing an example of a conventional delay circuit.

Claims (1)

[Scope of Claims] 1. Delay means for receiving an input signal and forming a plurality of delayed signals each having a different delay time, and gate means for selectively outputting the plurality of delayed signals. Features a delay circuit. 2. A patent characterized in that the delay means is constituted by a plurality of inverter circuits connected in series, and is constituted in one semiconductor integrated circuit together with gate means for selectively outputting the inverter circuits. Claim 1
Delay circuit described in section. 3. The delay circuit according to claim 1 or 2, wherein the delay circuit is used in an encode/decode circuit that forms a write signal for a magnetic disk memory.