JPH02183540A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a shallow and sufficient junction between an internal base region and an external base region, and realize a bipolar semiconductor device of high performance by forming a linking region between the internal base region and the external base region. CONSTITUTION:On an internal base forming part, a borosilicate film 15 is left; a nitride film is deposited on the whole surface; a side wall 16 is formed by etching the whole surface; a polycrystalline silicon is deposited; a P<+> type polycrystalline silicon film 17 is formed; the side wall 16 is selectively etched and eliminated; boron is ion-implanted, heat treatment is performed for activation. Thus, as the result of diffusion from the BSG film 15 and a P<+> type polycrystalline silicon film 17, the following are formed; an internal base region 19, an external base region 20, and a linking region 21 between the internal base region 19 and the external base region 20. Thereby, a shallow and sufficient connection between the internal base region 19 and the external base region 20 can be realized and a bipolar semiconductor device of high performance is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a bipolar semiconductor device.

(Prior Art) An example of a conventional method of manufacturing a self-line bipolar transistor will be described with reference to FIGS. 3(a) to 3(C).

As shown in FIG. 3(a), first, a P-type silicon substrate 51
An N+ buried layer 52 is selectively formed thereon. Then, an N-type epitaxial layer 53 is grown. Next, after selectively forming element isolation regions 54, a nitride film 55 and a polycrystalline silicon film 56 are deposited, and holes for forming internal base and emitter regions are formed in the polycrystalline silicon film 56.

After doping the polycrystalline silicon film 56 with boron, oxidation is performed to form an oxide film 5 on the polycrystalline silicon film 56.
7 is formed, and the nitride film 55 and this oxide film 57 are etched to the extent of undercutting, thereby exposing the surface of the N-type epitaxial layer 53. Already - antonym: deposit crystalline silicon,
Fill in the undercut and perform etching. Then, thermal oxidation is performed to form an oxide film 57a. At this time, a p-type external base region 58 is formed in the N-type collector region 53 by diffusion from the polycrystalline silicon film 56.

Next, as shown in FIG. 3(b), boron is ion-implanted through the oxide film 57a to form five internal base regions. Thereafter, a polycrystalline silicon film (not shown) is deposited on the oxide film 57. (not shown). Using this remaining polycrystalline silicon film as a mask, the emitter window is opened. Then, polycrystalline silicon is deposited to form an emitter, arsenic ions are implanted, and patterning is performed to form an N+ type packed crystal silicon pattern 60 (see FIG. 3(c)).

Thereafter, an emitter region 61 is formed by diffusion from this polycrystalline silicon pattern 60 (see FIG. 3(c)).
.

(Problems to be Solved by the Invention) The semiconductor device obtained by the conventional manufacturing method described above has the following problems.

(1) The external base region is formed by diffusion from polycrystalline silicon, and the internal (active) base region is formed by
This is done by ion implantation through the thermal oxide film grown on the silicon surface. This ion implantation is desirably shallow in order to improve the performance of the bipolar transistor.

As a result, the connection between the external base region and the internal base region becomes insufficient, particularly in the region below the oxide film. This causes an increase in base resistance and an increase in emitter-collector punch-through current.

(2) Also, if you want to sufficiently connect the above-mentioned joint regions, one way to do this is to increase the concentration of the internal base region, but if you increase the internal base concentration, the bipolar characteristics will immediately change. For example, the current amplification factor decreases, the base width increases, and the transistor performance deteriorates. In order to achieve the same characteristics as before, it is necessary to increase the concentration of the emitter region and make it deeper, which creates even more severe conditions such as a decrease in emitter-base breakdown voltage and the occurrence of defects due to the high concentration. It becomes.

(3) Furthermore, since the internal base region is formed by ion implantation, implant damage caused by ion implantation occurs in the active base region, and the process temperature decreases as the junction becomes shallower, so defects etc. can be recovered. Without,
For example, leakage between the collector and emitter may occur.

(4) Also, since the internal base region is formed by ion implantation, it may be affected by channeling during ion implantation, resulting in the base width becoming wider than desired.
This results in variations in characteristics.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can manufacture a high-performance biparallel semiconductor device.

[Structure of the invention]

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the first invention provides a method for manufacturing a semiconductor device in which a second conductive type is formed on a portion where an internal base region is to be formed on a surface of a semiconductor substrate of a first conductivity type.
A step of forming an oxide film containing a conductivity type impurity, a step of forming a sidewall on the peripheral side of the oxide film, and a step of forming a polycrystalline film containing a high concentration of a second conductivity type impurity over the entire surface so as to cover the oxide film and the sidewall. A step of forming a silicon film, a step of removing the polycrystalline silicon film near the oxide film until the upper surface of the oxide film and sidewalls are exposed, a step of selectively removing the sidewalls, and a step of removing the sidewall traces on the surface of the semiconductor substrate. The semiconductor substrate surface under the oxide film and the semiconductor substrate surface under the polycrystalline silicon film are formed by implanting impurities of two conductivity types and diffusing the impurities from the oxide film, polycrystalline silicon film, and sidewall traces on the semiconductor substrate surface, respectively. and a step of forming an internal base region of a second conductivity type, an external base region of a second conductivity type, and a joint region between the internal base region and the external base region on the surface of the semiconductor substrate where the sidewall remains, and selectively forming an oxide film. a step of forming an insulating film on the surface and side surfaces of the polycrystalline silicon film by performing thermal oxidation, and a step of forming a polycrystalline silicon film containing impurities of a first conductivity type on the internal base region. , forming an emitter region of the first conductivity type in the internal base region by diffusing impurities of the first conductivity type from the polycrystalline silicon film.

Further, a method for manufacturing a semiconductor device according to a second invention is as follows.

a step of forming an oxide film containing an impurity of a second conductivity type on a portion of the surface of the semiconductor substrate of the first conductivity type where an internal base region is to be formed; a step of forming a sidewall on a peripheral side of the oxide film; and a step of forming an oxide film and the sidewall. a step of forming a polycrystalline silicon film containing a highly concentrated second conductivity type impurity over the entire surface so as to cover the oxide film, and a step of removing the polycrystalline silicon film near the oxide film until the top surface of the oxide film and sidewalls are exposed. , the sidewalls are selectively etched so that the height of the remaining sidewalls is approximately 1/3 of the height of the oxide film.
a step of implanting a second conductivity type impurity into the lower part of the remaining sidewall, and a step of diffusing impurities from the oxide film, polycrystalline silicon film, and the lower part of the remaining sidewall. By doing so, an internal base region, an external base region, an internal base region, and an external base region of the second conductivity type are formed on the semiconductor substrate surface under the oxide film, the semiconductor surface under the polycrystalline silicon film, and the semiconductor surface under the remaining sidewalls. a step of selectively removing the oxide film, a step of forming an insulating film on the surface and side surfaces of the polycrystalline silicon film by performing thermal oxidation, and a step of forming a joint region on the internal base region. Forming a first conductivity type emitter region in the internal base region by forming a polycrystalline silicon film containing a first conductivity type impurity and diffusing the first conductivity type impurity from the polycrystalline silicon film. It is characterized by comprising a process.

(Function) According to the method for manufacturing a semiconductor device according to the first invention configured as described above, the impurity of the second conductivity type is implanted into the side wall traces on the surface of the semiconductor substrate. Then, impurities are diffused from the oxide film, the polycrystalline silicon film, and the sidewall traces on the semiconductor substrate surface, respectively, and the internal base region and the external A base head and a joint region between the inner base region and the outer base region are respectively formed. Thereby, a high-performance bipolar semiconductor device can be manufactured.

Further, according to the method for manufacturing a semiconductor device according to the second invention configured as described above, impurities are diffused from the oxide film, the polycrystalline silicon film, and the lower part of the sidewall, respectively, and the semiconductor surface and the polycrystalline silicon film under the oxide film are diffused. An internal base region, an external base region, and a joint region between the internal base region and the external base region are formed on the semiconductor surface under the silicon film and on the semiconductor surface under the sidewall, respectively. Thereby, a high-performance bipolar semiconductor device can be manufactured.

(Example) The first example of the method for manufacturing a semiconductor device according to the first invention is described below.
This will be explained with reference to FIGS. (a) to (d).

As shown in FIG. 1(a), an N+ buried layer 12 is selectively formed on a P-type silicon substrate 11. As shown in FIG.

Then, for example, an N-type epitaxial layer 13 is grown. Note that this epitaxial layer 13 may be of P type and an N region may be formed later.

After forming the epitaxial layer 13, an element isolation region 14 is selectively formed, and BSG (
A boron concentration of 4 mol% is deposited. Then, patterning is performed to leave the BSG film 15 on the portion where the internal base is to be formed. Next, for example, a nitride film is deposited on the entire surface, and the entire surface is etched by the RrE method to form the side walls 16. After that, polycrystalline silicon was added to 4000
For example, boron is deposited at 30 KeV.

Ion implantation is performed under the conditions of 5.times.10@15 cm@-2 to form a double-sided polycrystalline silicon film 17 which functions as an external base diffusion source and base electrode extraction. Then, patterning is performed to remove the P-type polycrystalline silicon in areas other than the diffusion source and electrode lead-out areas. Next, a resist film (not shown), for example, is applied to the entire surface and etched back until the upper surface of the side 916 is exposed, leaving the P+ type polycrystalline silicon film 17 on the side surfaces of the BSG film 15 and the side wall 16. At this time, etchback is performed under conditions that make the etching rates of the P-type polycrystalline silicon film 17 and the resist film equal (first
(See figure (b)).

Next, as shown in FIG. 1(c), the side wall 16 is selectively etched away, and boron, for example, is etched at 2°KcV and 2°C.
Ion implantation is performed under conditions of approximately X 1014 cm-2. Then, a thermal process for activation is performed. At the same time, due to diffusion from the BSG film 15 and the P-type polycrystalline silicon film 17, the internal base region 19 and the external base region 20
, and the inner base region 19 and the outer base region 20
A joint area 21 is formed. Thereby, the internal base region 19 and the external base region 20 are sufficiently connected.

Next, as shown in FIG. 1(d), the BSG film 15 is selectively etched away and thermal oxidation is performed to form an insulating film 22 on the surface of the P+ polycrystalline silicon. Then, for example, CVD
A film is deposited on the entire surface and etched by RIE method,
A side wall 23 is formed on the side surface of the P+ polycrystalline silicon pattern film 17. Here, etching is performed taking care to leave a sufficient amount of the insulating film 22 formed on the surface of the P+ polycrystalline silicon film 17, but if necessary, the thickness of the oxide film on the P+ polycrystalline silicon pattern 17 or the thickness of the oxide film on the P+ polycrystalline silicon film 17 may be Care must be taken to obtain sufficient dielectric strength by adding more layers. Then, a polycrystalline silicon film 24 of, for example, 4000
For example, deposit arsenic at 40 KeV, I
Ion implantation is performed under the condition of 1016 am', and after patterning, heat treatment for emitter formation is performed to form the emitter region 25. Note that in this embodiment, heat treatment is performed after patterning, but patterning may be performed after heat treatment.

Thereafter, normal interlayer insulating film formation, contact formation, and metal wiring steps are performed to complete the present semiconductor device.

In manufacturing the semiconductor device according to the above embodiment, it should be noted that the conditions for ion implantation at the joint between one internal base region and the external base region 20 are such that
The width (thickness) of the side wall 16 must be determined by considering the junction breakdown voltage and capacitance between the base and the collector.The width (thickness) of the side wall 16 should be determined to be the minimum necessary considering the increase in capacitance between the base and the collector. However, if the width is too narrow, the withstand voltage between the emitter and the external base near the surface will deteriorate, so care must be taken.

An embodiment of the second invention will be described with reference to FIGS. 2(a) to 2(d).

As shown in FIGS. 2(a) and 2(b), a BSG film 15, a P+ type polycrystalline silicon film 17, and a side wall 16 are formed by the same steps as in the first embodiment of the present application.

Thereafter, as shown in FIG. 2(c), the sidewall 16 is selectively etched to remain, for example, up to a height of about 173 of the BSG film 15. For example, boron at 50KeV
, 2×10'cm-2 by ion implantation. After that, a thermal process for activation is performed. At the same time, due to diffusion from the BSG film 15 and the P+ type polycrystalline silicon film 17, the internal base region 19, the external base region 20, and the internal base region 19 and the external base region 20 are
A joint region 21a is formed. Thereby, the internal base region 19 and the external base region 20 are sufficiently connected.

Next, as shown in FIG. 2(d), the BSG film 15 is selectively etched away and thermally oxidized. In this embodiment, the oxide film on the surface of the silicon substrate grows slower than that on the P+ type polycrystalline silicon film 17, and due to the difference in film thickness, etching is performed to remove the oxide film on the surface of the silicon substrate. Then, a layer of polycrystalline silicon 24a of, for example, 400 nm is applied to the entire surface.
After that, for example, arsenic is deposited at 40KeV, 1
Ion implantation is performed under the conditions of x1016cIT+-2. Next, after patterning, heat treatment for emitter formation is performed to form emitter regions 25a. Note that in this embodiment, heat treatment is performed after patterning, but patterning may be performed after heat treatment. Thereafter, normal interlayer insulating film formation, contact formation, and metal wiring steps are performed to complete the semiconductor device.

A point to be noted in manufacturing the semiconductor device according to the above embodiment is that since the emitter region is determined by the sidewall 16, the sidewall width must be optimized so that the breakdown voltage is not determined between the external base region 20 and the emitter. Must be. In addition, the concentration of the joint region 21a is also determined by the emitter-base breakdown voltage.
The decision must be made taking into consideration the capacity and capacity. Also,
The P type polycrystalline silicon film 17 and the N+ type polycrystalline silicon film 24a were separated by thermal oxidation, but if necessary, for example, an additional layer may be stacked on the P+ polycrystalline silicon film 17 to obtain a sufficient dielectric strength. Care must be taken to obtain the

In the above two embodiments, etching back was performed using a resist, but it is also possible to use other methods such as bias sputtering to form the shape shown in FIG. 2(b).

In the above two embodiments, a nitride film was used as the sidewall material, but the material is not limited to this as long as it has etching selectivity with respect to the BSG film and polycrystalline silicon.

In addition, although the collector electrode extraction region was not mentioned in the above two embodiments, the collector electrode extraction region is deep N so that it connects to the N+ buried layer.
+ area is formed and extraction is performed from there.

According to the first and second embodiments described above, the following effects can be obtained. That is, sufficient connection between the external base region and the internal base region can be achieved by the ion-implanted joint region, and an increase in base resistance and an increase in punch-through current between the emitter and collector can be prevented. Furthermore, since the internal base region that determines the bipolar characteristics is formed by diffusion from the BSG film, damage during ion implantation can be avoided, and since there is no channeling, a shallow and clean junction can be formed. Therefore, it is possible to improve the leakage level and reduce the base width, thereby improving the operating speed.

Furthermore, since the internal base conditions can be determined without paying attention to the connection between the external base area and the internal base, the conditions can be set relatively freely.

〔Effect of the invention〕

As detailed above, according to the present invention, a self-aligned bipolar transistor in which the external base is formed by diffusion from a P+ polycrystalline silicon film and the emitter is formed by diffusion from an N+ polycrystalline silicon film is formed. Not only is it possible to improve the poor connection between the internal base region and the external base region, which is a problem in the process, by selectively implanting ions into the joint region, but also by solid-phase diffusion, It becomes possible to obtain a shallower junction, and thereby a high-performance bipolar semiconductor device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the steps of a first embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view showing the steps of the second example of the method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a cross-sectional view showing the steps of a conventional manufacturing method. 11... Semiconductor substrate, 12... N++ buried layer, 1
3... N-type collector region, 14... Element isolation region,
15...BSG film, 16...side wall, 17...P
type polycrystalline silicon film, 18...P-type base-P-type base coupling region upper opening, one...P-type internal base region, 20...P-type external base head mounting, 21...P Type-
P++ type base coupling region, 22... insulating film, 23...
・Side wall, 24...N++ polycrystalline silicon, 25...
N+ type emitter installed

Claims (1)

[Claims] 1. Forming an oxide film containing impurities of a second conductivity type on a portion of the surface of a semiconductor substrate of a first conductivity type where an internal base region is to be formed, and forming a sidewall on a local side of the oxide film. a step of forming;
A highly concentrated second layer is applied to the entire surface so as to cover the oxide film and sidewalls.
forming a polycrystalline silicon film containing conductivity-type impurities; removing the polycrystalline silicon film near the oxide film until the top surface of the oxide film and sidewalls are exposed; and selectively removing the sidewalls. a step of implanting a second conductivity type impurity into the sidewall traces on the surface of the semiconductor substrate; and diffusing the impurities from the oxide film, the polycrystalline silicon film, and the sidewall traces on the semiconductor substrate surface, respectively. an internal base region of a second conductivity type, an external base region of a second conductivity type, an internal base region and an external base region on the semiconductor substrate surface under the polycrystalline silicon film, the semiconductor substrate surface under the polycrystalline silicon film, and the semiconductor substrate surface of the side wall traces. a step of selectively removing the oxide film, a step of forming an insulating film on the surface and side surfaces of the polycrystalline silicon film by performing thermal oxidation, and a step of forming a joint region of the internal base region. forming a polycrystalline silicon film containing a first conductivity type impurity thereon, and diffusing the first conductivity type impurity from the polycrystalline silicon film to form a first conductivity type emitter region in the internal base region. 1. A method of manufacturing a semiconductor device, comprising: a step of forming a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity is N type and the second conductivity type impurity is P type. 3. forming an oxide film containing impurities of a second conductivity type on a portion of the surface of the semiconductor substrate of the first conductivity type where an internal base region is to be formed; and forming a sidewall on a peripheral side of the oxide film;
A highly concentrated second layer is applied to the entire surface so as to cover the oxide film and sidewalls.
a step of forming a polycrystalline silicon film containing conductivity type impurities; a step of removing the polycrystalline silicon film near the oxide film until the upper surface of the oxide film and the sidewalls are exposed; and selectively etching the sidewalls. , a step of making the height of the remaining sidewall approximately 1/3 to 1/2 of the height of the oxide film, and implanting a second conductivity type impurity into the lower part of the remaining sidewall. step, and diffusing impurities from the oxide film, the polycrystalline silicon film, and the lower part of the remaining sidewalls, thereby reducing the semiconductor substrate surface under the oxide film, the semiconductor surface under the polycrystalline silicon film, and the remaining forming an internal base region and an external base region of a second conductivity type and a joint region between the internal base region and the external base region on the semiconductor surface under the sidewall; selectively removing the oxide film; forming an insulating film on the surface and side surfaces of the polycrystalline silicon film by oxidizing; forming a polycrystalline silicon film containing impurities of a first conductivity type on the internal base region; forming an emitter region of a first conductivity type in the internal base region by diffusing impurities of a first conductivity type from a silicon film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity is N type and the second conductivity type impurity is P type.