JPH02183535A - Multilayer interconnection forming method - Google Patents

Abstract

PURPOSE:To form a multilayer interconnection of small contact resistance with a high reliability by arranging a noble metal layer on a lower wiring layer composed of a aluminum, aluminum alloy, etc. CONSTITUTION:On a lower wiring layer 2 composed of aluminum, aluminum alloy, etc., a noble metal layer 1 such as plantinum, group element or gold is arranged by a method like sputtering. The thickness of the noble metal layer 1 is desirable to be in range of 50-300Angstrom . After the lower wiring layer 2 and the noble metal layer 1 are left as a desired wiring pattern and an interlayer film 5 is formed, a contact hole 6 is formed. Hence, an oxide layer is not formed on the surface of the noble metal layer 1 exposed on the bottom surface, and insulative compound like fluoride is not deposited in the selective CVD process of high melting point metal 7, because the noble metal layer does not react chemically to source gas. Thereby a multilayer interconnection of low contact resistance can be easily formed with high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming multilayer wiring.

[Summary of the invention]

The present invention relates to a method of forming a multilayer wiring in which a contact hole is opened in an interlayer insulating film on a lower wiring of a semiconductor device and a high melting point metal is filled in the contact hole.

[Conventional technology]

BACKGROUND OF THE INVENTION As semiconductor devices become more highly integrated, multilayer wiring technology is becoming increasingly important. The aspect ratio, that is, the ratio of depth to diameter, of the contact hole for electrically connecting the lower wiring layer and the upper wiring layer is increasing to 1 or more, and it is necessary to fill the contact hole with conductive metal. A selective CVD method using a high melting point metal such as tungsten is considered to be a promising method. This is because the selective CVD method for high melting point metals such as tungsten can selectively grow high melting point metals such as tungsten only on silicon or metal surfaces in a self-aligned manner.

When this method is applied to a lower wiring layer made of aluminum, an aluminum alloy, etc., there is a problem that a natural oxide film (A1203) of aluminum is left on the lower wiring layer during the process. Furthermore, when a common source gas for a high melting point metal, for example, tungsten hexafluoride (HP), is used, WF and aluminum react to form aluminum trifluoride (AIF) on the surface of the lower wiring layer.

Alh is solid at room temperature and is insulating, so A
Along with h03, both of these factors contributed to the increase in contact resistance.

Therefore, for example, Japanese Patent Laid-Open No. 61-287149 discloses a method of providing a silicon layer on a lower wiring layer made of aluminum or the like. This conventional technology is used as a second
The explanation will be based on figures a to e.

First, as shown in FIG. 2a, a lower wiring layer 2 such as aluminum is formed on an insulating film substrate 3 on a semiconductor substrate 4, and a silicon layer 9 is formed on it to a thickness of several hundred layers. Second
As shown in the figure, silicon layer 9 and lower wiring layer 2 are left as a desired wiring pattern by photolithography and etching steps. Next, as shown in FIG. 2C, an interlayer insulating film 5 is formed, and a contact hole 6 is opened therein. At this time, the silicon layer 9 is exposed at the bottom of the contact hole 6. Subsequently, as shown in FIG. 2d, tungsten or molybdenum is selectively deposited and grown on the bottom surface of the contact hole 6 by the CVD method using MoF as a source gas and H2 as a carrier gas. At this time, the silicon layer 9 in the contact hole 6 is completely consumed due to the reaction with WF or MoF6, so that no silicon layer remains between the lower wiring layer 2 and the high melting point metal 7 in the contact hole. To,
The thickness of the silicon layer must be less than 1000 Å.

Furthermore, as shown in FIG. 2e, an upper wiring layer 8 made of aluminum, Al-5i, or the like is formed thereon.

[Problems to be Solved by the Invention] In the conventional technology described above, when the silicon layer on the lower wiring layer is completely consumed by the source gas such as WF6 or MoFb, the lower wiring layer such as aluminum is completely exposed. do. In this state, aluminum and W
F, and MoF react with h gas to form the product Al
F3 is deposited on the bottom of the contact hole. Since AlF3 is an insulator, this conventional technology results in
It has been difficult to reduce contact resistance.

Therefore, an object of the present invention is to form a contact hole in an interlayer insulating film on a lower wiring layer made of aluminum, an aluminum alloy, etc., and fill it with a high melting point metal to form a multilayer wiring. It is an object of the present invention to provide a highly reliable multilayer wiring formation method that does not require the formation of a material film and has a low contact resistance value.

[Means to solve the problem]

In order to solve the above problems, the present invention is characterized in that a noble metal layer such as a platinum group element or gold is provided on a lower wiring layer made of aluminum, aluminum alloy, etc. by a method such as sputtering. . The thickness of the noble metal layer is preferably 50 Å or more and 300 Å or less.

Thereafter, in the same manner as in the conventional method, the lower wiring layer and the noble metal layer are left as a desired wiring pattern, an interlayer insulating film is formed, and then a contact hole is opened. Next select C
A high melting point metal layer such as tungsten, molybdenum (Mo), or tantalum (Ta) is deposited and grown on the surface of the noble metal layer at the bottom of the contact hole by the VD method. By subsequently forming an upper wiring layer, it is possible to form a multilayer wiring with low contact resistance with high reliability.

[Effect]

Although noble metal layers such as platinum elements and gold are chemically inert, they can be removed by sputtering effects during the reactive ion etching (RIE) process used to pattern the underlying wiring layers.

This is because the thickness of the noble metal layer is sufficiently thin at 50 Å or more and 300 Å or less. In other words, patterning of the lower wiring layer and the noble metal layer can be done by conventional methods without any problems.

Since the noble metal layer exposed on the bottom surface due to the opening of the contact hole is stable against oxidation, no oxide layer is formed on the surface.

Furthermore, in the process of performing selective CVD of high melting point metals, the noble metal layer does not chemically react with the source gas, so that insulating compounds such as fluoride do not precipitate.

That is, the high melting point metal can be deposited and grown directly on the noble metal layer on the lower wiring layer without using an insulator.

Due to these effects, multilayer interconnections with low contact resistance values can be easily and reliably formed. In addition,
If the thickness of the noble metal layer is less than 50 layers, it is difficult to obtain a low resistance value, while if it exceeds 300 layers, it becomes difficult to remove due to the sputtering effect during wiring patterning. The thickness of the noble metal layer is 50 Å or more3
A range of 00 Å or less is preferable.

(Embodiments) Hereinafter, specific embodiments of the present invention will be described with reference to FIGS. 1a to 1e.

First, as shown in FIG. 1a, an insulating film substrate 3 such as silicon oxide (SiO□) is formed on a semiconductor substrate 4 such as silicon, and a lower wiring layer 2 made of aluminum, for example.
Then, a noble metal layer 1 made of, for example, platinum is formed to a thickness of 100 mm by DC magnetron sputtering.

Next, by a photolithography process and an RIE process, both the noble metal layer 1 and the lower wiring layer 2 are etched, leaving a wiring pattern as shown in FIG.

Next, as shown in FIG. 1C, for example, PSG (Phos
A glabellar insulating film 5 made of (pho-silicate glass) is deposited by the CVD method, followed by a photolithography process and an RIE process using a mixed gas of fluorine gas such as CHFff, argon gas, and oxygen gas to form a contact on the lower wiring pattern. Open hole 6.

Subsequently, as shown in FIG. 1d, a high melting point metal 7 is selectively deposited and grown on the noble metal layer 1 exposed at the bottom of the contact hole 6 by selective CVD of, for example, tungsten, thereby filling the inside of the contact hole 6. Selective CVD of tungsten can be performed using, for example, WF as a source gas,
IO3CCM, 5iHa as carrier gas 6S
Flow CCM and H2 at 1100O-ec, 260°C
A low pressure CVD method at 10.2 Torr was used.

Furthermore, as shown in FIG. 1e, an upper wiring layer 8 made of, for example, aluminum or an aluminum alloy is formed on the high melting point metal 7 and the interlayer insulating film 5, thereby completing the multilayer wiring.

The embodiments of the present invention have been described in detail above, but in addition to platinum (PL) used in this embodiment, the materials for the noble metal N1 include ruthenium (Ru), rhodium (Rh), palladium (Pd), Osmium (O3) and Iridium (Ir)
) or the platinum group elements of group 1 of the periodic table, such as
It is possible to use Au of Group B or an alloy of these metals, and the noble metal layer may be formed by sputtering, vacuum deposition, or the like. In short, in the RIE process for opening contact holes and the selective CVD process for refractory metals, the objects of the present invention can be achieved using inert metals that do not form an insulating layer, such as oxides or fluorides.

〔Effect of the invention〕

As explained above, according to the present invention, in a multilayer wiring formation method in which a glabellar insulating film and a contact hole are formed on a lower wiring layer made of aluminum, aluminum alloy, etc., and a high melting point compound such as tungsten is embedded in the contact hole, By providing a noble metal layer with a thickness of 50 Å or more and 300 Å or less on a lower wiring layer made of aluminum, aluminum alloy, etc., it has become possible to form multilayer wiring with low contact resistance with high reliability.

This makes it possible to overcome the drawbacks of conventional multilayer wiring technology, which has high contact resistance and poor reliability, and greatly contributes to highly integrated semiconductor processes.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a multilayer wiring structure according to an embodiment of the present invention, and FIG. 2 is a sectional view showing an example of a conventional multilayer wiring structure. 1-・-・-1--------Noble metal layer 2-------------Lower wiring layer 3--・--
=-Insulating film substrate 4...---------1---Semiconductor substrate 5--
・−・−1−−−Interlayer insulating film 6−・−−−−−−1−−−−−Contact hole 7
・・−・−・−11−〜−High melting point metal 8−・−・−
...-Upper layer wiring layer 9-----Indicates the aging of the multi-layer 1 in the row A when the silicon layer fails to explode-tgiU
Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1.

Claims (1)

[Scope of Claims] A multilayer wiring formation method in which a lower wiring layer and an interlayer insulating film are sequentially formed on a substrate, and then a contact hole is opened, and then a high melting point metal is embedded in the contact hole, the method comprising: A multilayer wiring formation method characterized by providing a noble metal layer on a wiring layer.