JPH02181554A - Packet exchange - Google Patents

Abstract

PURPOSE:To improve real time property by allowing hardware to execute the restoration processing of information sent from a terminal equipment. CONSTITUTION:A terminal interface part 10 divides a signal such as a sound transmitted from a terminal 1, user data and an image into cells with a fixed length and adds data such as destination information and sequence number information to the cells as heater information to form packet information. Then, the interface part 10 multiplexes these packeting information The multiplexed information is sent to a packet assembling processing part 30 through a packet switch circuit 20. In the processing part 30, a packet assembling part 30a constituting respective elements of hardware receives the packeting information multiplexed by the interface part 10 and rapidly restores the information to the original information format.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a packet switch, and particularly to packet assembly processing in a packet switch.

(Prior Art) Conventionally, a store-and-forward method has been adopted for exchanging data information in a packet switch. In this method, data information sent from a terminal on the originating side is temporarily stored in the memory of a packet switch, then transferred within the network (between each packet switch), and finally delivered to the other party's terminal. At this time, no communication path is set up between the terminals of one calling party and the other party for directly transmitting and receiving data.

That is, data information flowing within the network is divided into pieces of fixed length, and each piece of information is formed into a packet by adding a header containing information such as the destination and sequence number of the information. The packet switch performs switching processing on the information transmitted from the terminal in units of packets according to the headers.

Before forming the data information transmitted from the terminal into packets, the packet switch divides the data information into, for example, a fixed length, adds header information to this, and transmits it as packetized information. In order to form a packet from the packetized information, the packet switch temporarily stores the received data information in a memory, arranges it according to the sequence number, removes header information such as the destination sequence number, and returns the data to the original one. Prior art packet switches reconstruct messages sent from terminals.

Such information data reconstruction processing has been performed by software under program control.

(Problem to be Solved by the Invention) However, in such a conventional packet switch, when information data such as voice, user data, images, etc. is packetized, the received packetized information is stored in the -H memory. Therefore, it is necessary to align the order according to the sequence number, which has the disadvantage of increasing delay time.

For this reason, for example, conventional packet switching equipment can be
When applied to an integrated packet switch that integrates and exchanges signals such as user data and images, a system that satisfies real-time performance can be constructed without using an ultra-high-speed processing device and an ultra-high-speed memory inside. The problem is that it cannot be done.

It is an object of the present invention to eliminate such drawbacks of the prior art and provide a packet switch with excellent real-time performance.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention divides information sent from a terminal device into cells of a certain length, and packetizes the cells by adding destination-sequence number information to the cells. A packet switch that divides information into packets and assembles the packetized information after restoring it to the information form sent from the terminal equipment, includes at least one input buffer means for receiving the packetized information and destination and sequence number information. a latch means for latching the packetized information, and a packet assembling means for removing the header of the packetized information from the packetized information and restoring it to the information form transmitted by the terminal device, and storing this information form for each block number based on a notification from the latch means. and a first storage means for storing a block number in which the information form stored in the packet assembling means is stored, and a first storage means for storing a block number for storing packetization information when the sequence number information indicates the beginning. It has a second storage means and an output means for performing speed matching with an output side for outputting the restored information form.

(Function) According to the present invention, when packetized information divided into a certain length and header information added is received, the destination and sequence number information included in the header information are used to determine whether the packetized information sent from the terminal device is Identify information. After identifying a series of information based on the header information, the information is added up, the header information is excluded, and the information form transmitted from the terminal device is quickly restored. The restored information is then passed to software that forms packets.

(Embodiment) Next, an embodiment of a packet switch according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, a relay scheme diagram in an embodiment of the packet switch according to the present invention is shown. The packet switch 2 is, for example, an integrated packet switch capable of accommodating a plurality of terminal devices 1 with different information formats, and includes a terminal interface section 1O, a packet switch circuit 20, and a packet assembly processing section 30.

The terminal interface unit IO is an interface unit that is connected to a plurality of terminals 1 and sends signals from these terminals to the inside of the exchange. That is, the interface unit 10 divides signals such as voice, user data, and images transmitted from each terminal l into fixed-length cells, and adds destination information, sequence number information, etc. to the data as header information. to form packetized information (FIG. 3). The interface unit IO multiplexes these packetized information using a multiplexer. The multiplexed information is sent to the packet assembly processing unit 30 via the packet switch circuit 20, which is a switch that connects the terminal interface unit IO and the packet assembly processing unit 30.

FIG. 3 shows an example of packetized information. As shown in the figure, a switching header indicating sequence number information, the number of effective bytes, and destination information is added to the packetized information before the data sent from terminal l. Note that the sequence number information indicates the serial number of a series of information transmitted from the terminal 1, which is divided into packetized information that is fixed-length cell information. In addition, the header in packetization information is
Unless otherwise specified, it refers to parts other than data, such as sequence numbers, number of appeasement bytes, and switching headers.

The packet assembly processing unit 30 includes a packet assembly unit 30a, each element of which is constructed of hardware, and a packet assembly unit 30a.
a control processor 30b that receives the information restored in step a and forms a packet to be transmitted over the switching network;
0a is an assembling unit that receives multiplexed packetized information from the interface unit IO and quickly restores this information to its original information form. FIG. 1 shows a functional block diagram of the packet assembling section 30a in this embodiment.

The packet assembling unit 30a includes an input buffer circuit 31°, a header latch circuit 32. Packet assembly circuit 34, packet assembly block number storage circuit 35, initial setting data section 38
, empty block number storage circuit 37, blocked block number storage circuit 38, output buffer 7 circuit 39, control circuit 40, F
CS chainer 2 circuit 41 and multiple signal selectors 33
has. The input buffer circuit W1131 has its input side connected to the output side of the packet switch circuit 20, and one or more input buffer circuits W1131 are arranged in the assembly section 30a. The output side of the buffer circuit 31 is connected to a packet assembly circuit 34 via a header latch circuit 32, an FCS check circuit 41, and a selector 33.

The header latch circuit 32 is a circuit that latches destination and sequence number information included in the header of the received packetized information. The latch circuit 32 determines whether the received cell is the first cell based on the sequence number information, and if it is the first cell, the empty block number storage circuit 37 is
If the packet is not at the beginning, the block number storage circuit 35 for assembling the packet is activated.

The empty block number storage circuit 37 is a storage circuit that stores the block number in which the packetization information is stored when the sequence number information of the header indicates the beginning. When the block number stored here is activated, the block number is transferred to the packet assembling block number storage circuit 35 and the base reblock number storage circuit 3 via the selector 33.
8 will be notified respectively.

The blocked block number storage circuit 38 is a storage circuit that stores the block number of the information restored to the information form of one sending terminal 1. The block number restoration information stored here is transferred to the control processor 30b.

The packet assembling block number storage circuit 35 is a circuit that stores the block number of the packetized information that is being restored to the information form from the sending terminal 1, for example, multiplexed and received.

The FCS check circuit 41 is a circuit that performs an FCS check on information other than the destination, the number of effective bytes, and the header, and checks whether there are any errors in this information. When the check circuit 41 determines that there is no error in the received information, it sends the information to the storage section of the packet assembly circuit 34 via the selector 33.

The packet assembly circuit 34 is a zero assembly circuit 3 that is a circuit that removes the header and restores the information format transmitted from the terminal 1.
4 has a storage unit that stores information other than the header information that was incorrectly checked in check 119341, that is, data from terminal l. FIG. 4 shows the logical configuration inside the memory section of the assembly circuit 34 in this embodiment and the method of specifying the block number stored in this memory section.8 In this embodiment, the memory sections are the same. 0-31 as shown
It is divided into 32 blocks, and each block number is designated by 5 bits from 0 to 4. In addition, in this embodiment, the block numbers were set to 0 to 31, but the block numbers in the present invention are not particularly limited in this way, and the number of block numbers may be larger or smaller than this. Returning to FIG. 1, once the received information is restored to its original information form by assembly circuit 34, the information is sent to output buffer circuit 38.

The output buffer circuit 39 is a buffer circuit that outputs the restored information to the control processor 30b for speed matching with software.

The control circuit 40 is a synchronous circuit that supplies a clock signal, which is a reference signal for each circuit of the packet assembling unit 3Qa, that is, an operation timing. This synchronization circuit 40 allows each circuit of the packet assembling section 30a to operate regularly.

The initial setting data section 38 is a circuit that initializes the empty block number storage circuit 37 when the power is turned on or reset, for example.

Next, an example of assembling packetized information will be shown. Packetized information buffered in the input buffer circuit 31 via the packet switch circuit 20 is outputted according to timing within the packet assembling section 30a.

Then, the destination, sequence number, and number of valid bytes included in the header part are latched by the header latch circuit 32,
Information other than the header is stored in the storage section of the packet assembly circuit 34. At this time, if the sequence number of the received information indicates that it is the first, the empty block number in the storage section 34 is read from the empty block number storage circuit 37, and the empty block number is used to determine the destination, the number of effective bytes, and the information other than the header. The information is FCS checked, and output FCS data in which no error is detected is written into the storage section 34.

Also, at the same time as this operation, the empty block number storage circuit 35
The empty block number read out from the header is written into the packet assembling block number storage circuit 35 so as to correspond to the destination information latched from the header. Note that reading from the empty block number storage circuit 37 and writing to the packet assembling block number storage circuit 35 only needs to be performed when the sequence number indicates the beginning.

When the sequence number of the received packetized information indicates that it is in the middle (continuation), the corresponding block number in the packet assembling block number storage circuit 35 is read out based on the destination information, and the block number other than the header is read out based on the destination information. The information, destination, data after FCS check, and data after addition of the number of effective bytes are written into the storage section 34.

Note that the data for adding the effective number of bytes has already been stored in the storage unit 3.
Effective number of bytes of packetization information written in 4 (
The number of effective bytes of the first packet is read out from the storage circuit before addition.

Further, the data for FC'J check is processed in the same way as the number of effective bytes, and this data is used as data for continuing FCS check with information other than the header of the continuation packet. Furthermore, the received packetized information is also subjected to the same processing as the above-mentioned intermediate packetized information. When the sequence number in the packetization information indicates the last, the number of valid bytes is not added, and the value indicating the number of valid bytes received, information other than the header, destination, and data after FCS check are added to the block number during packet assembly. Memory circuit 35
The block number read from the block number is written into the storage section of the packet assembling circuit 34.

If all the information received via the packet switch circuit 20 has the same destination, this means that the information form on the sending side has been restored, so the block number of the final packetized information is stored in the basic reblock number storage circuit 38. written. At the same time, the restoration information of the block number written here is
A transfer request is made to the control processor 30b. As a result, the base reblock number is read from the base reblock number storage circuit 38, and based on this block number, the destination, the number of effective bytes, and restoration information other than the header are read from the storage section of the packet assembly circuit 34 and output to the buffer. It is buffered in circuit 38.

When the processor 30b becomes ready to receive the transfer request to the control processor 30b, the output buffer circuit 39
The restoration information buffered in the processor 30b
The data is transferred to the processor 30b under the control of the processor 30b.

In this embodiment, even if multiplexed packetized information is received, the block number is stored in the packet assembling block number storage circuit 35 in accordance with the destination information included in the header.
In this embodiment, the control processor 30b also assembles the multiplexed packetized information into the information on the sending side. Since the data can be transferred to the original information format, the original information format can be restored at high speed.

One of the features of the packet switch in this embodiment is that it can restore packetized information to the information form of the originating side according to the line speed of the incoming side, and can transfer and process information according to the ability of the control processor 30b. This is what happens.

Another feature is that the amount of received information is fixed by assigning addresses to the storage section of the packet assembly circuit 34 for the block numbers read from the free and base reblock number storage circuits 37 and 38. It lies in being able to make decisions.

Due to these features, in this embodiment, it is possible to arrange the information sent from the terminal 1 in the order according to the sequence number very quickly. In a packet switch that requires strict real-time performance in switching, processing capacity will not be insufficient even if an ultra-high-speed processing device and an ultra-high-speed memory are not used.

Although this embodiment has been described with reference to an example in which multiplexed packetized information to which the present invention is most advantageously applied is received from the terminal interface unit IO, the present invention is of course limited to multiplexed packetized information. It is also possible to apply the present invention to packetized information that is not multiplexed.

Note that in that case, the packet-assembling block number storage circuit 35 may not be particularly provided.

(Effects of the Invention) As described above, according to the present invention, the restoration process of information sent from a terminal device, which was conventionally processed by software, is performed by hardware. The software that does this can packetize information from a terminal device in the information form after restoration processing, making it possible to significantly speed up the processing compared to the conventional technology.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an embodiment of a packet assembly section in a packet switch according to the present invention, FIG. 2 is a relay system diagram showing a tallow method of a packet switch according to the present invention, and FIG. 3 is similar to FIG. FIG. 4 is a block diagram showing an example of the format of applied packetized information. FIG. 4 is an explanatory diagram of the logical configuration of the storage section of the packet assembling circuit shown in FIG. 1 and a method of specifying a block number. , 1 of 2 100. Terminal device 200. Packet switch 10, Terminal interface section 20, Packet switch circuit 30a, Packet assembly section 30b, Control processor 31, Input buff 2a circuit 32, Header latch circuit 33, Selector 34 , , Packet assembly circuit 35 , Packet assembling block number storage circuit 37 , Free block number storage circuit 38° 38° 40° 41°, Occupied block number storage circuit 6 output buffer circuit, control circuit, FCS Check circuit patent applicant: Oki Electric Industry Co., Ltd. Representative: Takao Takao Kazan

Claims (1)

[Claims] 1. Divide the information sent from the terminal device into cells of a certain length, divide the cells into packetized information by adding a header containing destination and sequence number information, and divide the information sent from the terminal device into packetized information. a packet switch that assembles the packetized information into a packet after restoring it to the information form sent from the terminal device, the switch having: at least one input means for receiving the packetized information; and latching the destination and sequence number information. a latch means, and a packet assembling means for removing the header of the packetized information from the packetized information and restoring it to the information form transmitted by the terminal device, and storing the information form for each block number based on a notification from the latch means. and a first storage means for storing a block number in which the information form stored in the packet assembling means is stored, and a block number for storing packetization information when the sequence number information indicates the beginning. A packet switching device comprising: second storage means for storing the restored information; and output means for performing speed matching with an output side for outputting the restored information form. 2. The packet switching device according to claim 1, wherein the input means, latch means, packet assembly means, first storage means, second storage means, and output means are configured by hardware. packet switch. 3. The packet switch according to claim 1, wherein the switch has a third storage means for storing the block number being restored by the packet assembling means, and the third storage means has multiplexed input data. A packet switching device that manages and stores received packetized information using the block number. 4. The packet switch according to claim 3, wherein the third storage means is constituted by hardware.