JPH02178926A - Manufacture of semiconductor substrate - Google Patents
Manufacture of semiconductor substrateInfo
- Publication number
- JPH02178926A JPH02178926A JP33149688A JP33149688A JPH02178926A JP H02178926 A JPH02178926 A JP H02178926A JP 33149688 A JP33149688 A JP 33149688A JP 33149688 A JP33149688 A JP 33149688A JP H02178926 A JPH02178926 A JP H02178926A
- Authority
- JP
- Japan
- Prior art keywords
- polishing
- oxide film
- semiconductor
- semiconductor region
- natural oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000005498 polishing Methods 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 abstract description 8
- 230000003247 decreasing effect Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 abstract 4
- 239000010409 thin film Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 26
- 229910052710 silicon Inorganic materials 0.000 description 26
- 239000010703 silicon Substances 0.000 description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 239000007788 liquid Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000010186 staining Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野１
本発明は、半導体基板の製法、特に半導体基板に絶縁層
を介して別の基板を貼り合せて後、半導体基板の裏面よ
り研磨して半導体薄層を形成するようにしたＳ ＯＩ
（ｓｉｌｉｃｏｎ ｏｎ １ｎｓｕｌａｔｏｒ）基板
の製法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a method for manufacturing a semiconductor substrate, and in particular, to bonding a semiconductor substrate to another substrate via an insulating layer, and then polishing the semiconductor substrate from the back side. SOI that forms a thin layer
(Silicon on 1 nsulator) Substrate manufacturing method.
本発明は、選択ポリッシングにより研磨して半導体薄層
を形成するようにした貼り合せによる３０丁基板の製法
において、基準位置まで研磨されると研磨圧力が低下す
るのを利用して、ここまで研磨された半導体領域部の表
面に自然酸化膜を形成し、この自然酸化膜をストッパー
として他の基準位置に達しない半導体領域部を研磨する
ことによって、基板全面に均一な半導体薄層を形成でき
るようにしたものである。The present invention utilizes the fact that the polishing pressure decreases when polished to a reference position in a manufacturing method for bonding 30 substrates in which a thin semiconductor layer is formed by polishing by selective polishing. By forming a natural oxide film on the surface of the semiconductor region that has been polished, and using this natural oxide film as a stopper to polish other semiconductor regions that do not reach the reference position, it is possible to form a uniform semiconductor thin layer over the entire surface of the substrate. This is what I did.
［従来の技術］
近時、絶縁体上に薄膜単結晶シリコン層を形成してなる
所謂ＳＯＩ基板を用いて超ＬＳＩを作成する開発が進め
られている。[Prior Art] Recently, development has been underway to create a super LSI using a so-called SOI substrate formed by forming a thin single-crystal silicon layer on an insulator.
各種のＳｏｌ基板の作製方法の中でも最も結晶性が良く
、特性面でも優れていると考えられるものに貼り合せ方
式がある。Among the various methods for producing Sol substrates, the bonding method is considered to have the best crystallinity and superior properties.
第２図は貼り合せ方式によるＳＯＩ基板の一例を示す。FIG. 2 shows an example of an SOI substrate using a bonding method.
先ず、第２図Ａに示すように鏡面シリコンウエハ（１）
の主面にフォトリソグラフィー技術を用いて複数の凸部
（２）が形成されるように所定バタンの段差を形成する
。そして、その主面上にＳ】０□等の絶縁膜（３）を形
成し、さらに段差を埋めるために全面に例えば多結晶シ
リコン層（４）を形成し、この多結晶シリコン層（４）
の表面を平１月研Ｂ４する。First, as shown in Figure 2A, a mirror silicon wafer (1) is
A predetermined level difference is formed on the main surface of the substrate using photolithography technology so that a plurality of convex portions (2) are formed. Then, an insulating film (3) such as S]0□ is formed on the main surface, and a polycrystalline silicon layer (4), for example, is formed on the entire surface to fill in the steps.
The surface of the surface was polished by January Lab B4.
次に、第２図Ｂに示すように多結晶シリコン層（４）を
介してシリコンウェハ（１）と、別の鏡面シリ′：１ン
ウエハ（５）を貼り合せた後、第２図Ｃに示すように絶
縁膜（３）を研磨ストッパーとして用いて、シリコンウ
ェハ（１）の裏面より研磨し、絶縁膜（３）で分刈され
た複数の島状シリコン薄層（６）を有したＳ Ｏｌ −
９９板（７）を得る。Next, as shown in Figure 2B, the silicon wafer (1) and another mirror-finished silicon wafer (5) are bonded together via the polycrystalline silicon layer (4), and then as shown in Figure 2C. As shown, the silicon wafer (1) is polished from the back side using the insulating film (3) as a polishing stopper, and an S having a plurality of island-like thin silicon layers (6) cut by the insulating film (3) is prepared. Ol-
Obtain 99 plates (7).
しかし乍ら、」二連した貼り合せ方式によるＳＯＩ基板
においても、次のような重大な欠点があるため、その製
造が極めて困難であった。However, even the SOI substrate using the double bonding method has the following serious drawbacks, making it extremely difficult to manufacture.
シリコンウェハ（１）の研磨にはメカニカル・ケミカル
ポリッシングで特定の化学液を用いてシリ：１ンの研磨
レーＩ〜がＳｉＯ□の研磨レー１−に比べ著しく大きく
した選択ポリッシングが用いられるが、例えば応用物理
第５６巻第１１号（１，９８７） １．４８０〜１４８
４＠（研究ノート１）にも記載されている通り、選択ポ
リッシングには繊維質のクロスを使用すると、パターン
内の島状シリコン薄層（６）にクロスか入り込み、ハタ
ーン内の島状シリコン薄層（６）の中央部が老剰に研磨
され凹状になってしまう。ごれを防くにはパターンにく
い込まない程度の硬Ｓ′盤を用いる方法がある。この様
な定盤を用いるとパクン内のシリコン薄層（６）は凹状
にならず平坦に研磨出る可能性がある。For polishing the silicon wafer (1), selective polishing is used in which a specific chemical solution is used in mechanical/chemical polishing, and the polishing radius I~ of Si:1 is significantly larger than the polishing radius I~ of SiO□. For example, Applied Physics Vol. 56 No. 11 (1,987) 1.480-148
As described in 4@ (Research Note 1), if a fibrous cloth is used for selective polishing, the cloth will penetrate into the island-like silicon thin layer (6) in the pattern, and the island-like silicon thin layer in the pattern will be damaged. The central part of the layer (6) is polished excessively and becomes concave. To prevent staining, there is a method of using a hard S' board that does not dig into the pattern. If such a surface plate is used, there is a possibility that the thin silicon layer (6) inside the crack may be polished flat without becoming concave.
しかし、ここでは次のような重大な欠点が発生ずる。研
磨前にウェハ（１）のシリコン層の厚みむらはウェハ面
内で通常、数μｍ（１〜５μｍ）程度あるのでウェハ（
１）の部分を研磨盤上で研磨して行くと、第３図Ａに示
すように１の部分（８）では選択ポリッシュが進んで部
分的にパターン内が平坦化されても、他の部分（９）は
研磨不足で未だ数μｍ研磨する必要が生じることが多い
。このため、更に追込み研磨する必要がある。−例とし
て研磨液には通常シリコンはエツチングするがＳｉＯ□
膜は工、チングしないアミン系例えばエチレンジアミン
の水溶液等のアルカリ性のものを使用する。この液で第
３図Ｂの部分（１０）まで平坦化すると、最初に平坦化
された部分（８）が溶液そのもののエンチング作用によ
り必要以」二に薄くなり、場合によっては単結晶シリコ
ン薄層（６）が無くなってしまう欠点がある。However, the following serious drawbacks occur here. Before polishing, the thickness unevenness of the silicon layer of the wafer (1) is usually about several μm (1 to 5 μm) within the wafer surface.
When the part 1) is polished on a polishing disk, as shown in FIG. (9) is often insufficiently polished and still requires polishing several μm. Therefore, additional polishing is required. -For example, silicon is usually etched in the polishing liquid, but SiO□
The membrane used is an alkaline one, such as an aqueous solution of ethylenediamine, which does not cause corrosion or oxidation. When this solution is used to planarize the area (10) in Figure 3B, the initially planarized area (8) becomes much thinner than necessary due to the etching effect of the solution itself, and in some cases, the monocrystalline silicon thin layer may become thinner. There is a drawback that (6) is lost.
この防止対策が必要であり、そのためには最初に平坦化
された部分は、その後の研磨中にエツチングが進行しな
い様な工夫がいる。It is necessary to take measures to prevent this, and in order to do so, it is necessary to take measures to prevent etching from progressing during subsequent polishing in the initially flattened portion.
本発明は、上述の点に鑑み、ウェハ全面に均一・な厚さ
の半導体薄層を形成できるようにした半導体基板即ちＳ
ｏｌ基板の製法を提供するものである。In view of the above-mentioned points, the present invention provides a semiconductor substrate, that is, an S
The present invention provides a method for manufacturing an OL substrate.
〔課題を解決するだめの手段］
本発明は、半導体基板（１）の主面に絶縁層（３）を介
して別の基板（５）を貼り合せ、半導体基板（１）を選
択ポリ・ノシングにより研磨して半導体薄層（１４）を
形成する半導体基板の製法において、基準位置まで研磨
され研磨圧力が低下した半導体領域部（８）の表面に自
然酸化膜（１２）を形成し、自然酸化膜り１２）をスト
ッパーとして他の半導体領域部（９）を研磨するように
なす。[Means for Solving the Problems] The present invention involves bonding another substrate (5) to the main surface of a semiconductor substrate (1) via an insulating layer (3), and applying selective polynosing to the semiconductor substrate (1). In the manufacturing method of a semiconductor substrate in which a thin semiconductor layer (14) is formed by polishing, a natural oxide film (12) is formed on the surface of the semiconductor region (8) which has been polished to a reference position and the polishing pressure has been reduced. The other semiconductor region portion (9) is polished using the film 12) as a stopper.
〔作用］
貼り合せ後の選択ポリッシングによる半導体基板（１）
の研磨では段差のある絶縁層（３）が研磨ストッパーと
して作用する。研磨が基準位置ａ以下即ち絶縁層（３）
の面以下になるとその半導体領域部（８）に対する研磨
圧力は低下する。この研磨圧力の低下を利用し、研磨圧
力が低下した１の半導体領域部（８）の表面に自然酸化
膜（１２）を形成して研磨を続けると、基準位置ａまで
研磨されていない他の半導体領域部（９）では研磨が進
み、研磨圧力の低い１の半導体領域部（８）では自然酸
化膜（１２）が残ったままでス１−ソバ−として作用し
てエンチングが進行せず研磨停止状態となる。これを順
次に繰返えすことにより、ウェハ全面に均一な厚さの半
導体薄層（１４）が形成される。[Function] Semiconductor substrate (1) by selective polishing after bonding
During polishing, the stepped insulating layer (3) acts as a polishing stopper. Polishing is below reference position a, that is, insulating layer (3)
When the surface of the semiconductor region (8) is lower than that, the polishing pressure on the semiconductor region (8) decreases. Utilizing this decrease in polishing pressure, if a native oxide film (12) is formed on the surface of the first semiconductor region (8) where the polishing pressure has decreased and polishing is continued, other semiconductor regions that have not been polished to the reference position a will be Polishing progresses in the semiconductor region (9), and in the semiconductor region 1 (8), where the polishing pressure is low, the natural oxide film (12) remains and acts as a sober, preventing etching from proceeding and polishing to stop. state. By sequentially repeating this process, a thin semiconductor layer (14) having a uniform thickness is formed over the entire surface of the wafer.
以下、第１図を参照して本発明によるＳｏｌ基板の製法
の一例を説明する。Hereinafter, an example of a method for manufacturing a Sol substrate according to the present invention will be explained with reference to FIG.
第１図Ａに示すように鏡面シリコンウェハ（］）の主面
にフォトリックライフイー技術を用いて複数の凸部（２
）が形成されるように所定パターンの段差を形成する。As shown in Figure 1A, a plurality of convex portions (2
) is formed in a predetermined pattern.
そして、その主面」−にＳｉＯ□等の絶縁膜（３）を形
成し、さらに段差を埋めるために全面に５ｉ０２層＋
Ｓ ＯＧ （ｓｐｉｎ ｏｎ ｇｌａｓｓ）層或は多
結晶シリコン層、本例では多結晶シリコン層（４）を形
成し、この多結晶シリコン層（４）の表面を平坦研磨す
る。Then, an insulating film (3) such as SiO□ is formed on the main surface, and a 5i02 layer +
An SOG (spin on glass) layer or a polycrystalline silicon layer, in this example a polycrystalline silicon layer (4), is formed, and the surface of this polycrystalline silicon layer (4) is polished flat.
次に、第１図Ｂに示すように多結晶シリコン層（４）を
介してシリコンウェハ（１）と、別の鏡面シリコンウェ
ハ（５）を貼り合せる。Next, as shown in FIG. 1B, the silicon wafer (1) and another mirror-finished silicon wafer (5) are bonded together via the polycrystalline silicon layer (4).
次に、研磨液としてアミン系例えばエチレンジアミンの
水溶液を使用し、硬質研Ｕｍを用いた選択ポリッシング
により、シリコンウェハ（１）の裏面より研磨する。絶
縁膜（３）はシリコンの研磨ストッパーとして作用し、
第１図Ｃば前述の第３図Ａと同様に基準位置ａ即ら絶縁
膜（３）のパターンが露出しｆ項域部（８）が平坦化さ
れるまで（即ち島状のシリコン薄層（］４）が形成され
るまで）研磨したところである。シリコン薄層（１４）
の厚さは１．０００人程度である。ウェハ内に平坦化さ
れた領域部（８）が露出されたところで、研磨液の供給
を止め、数分間（１〜５分間）水洗し、領域部（８）及
び研磨不足の他の領域部（９）のシリコン表面には数人
程度の自然酸化膜（１２）を形成する（第１回り参照）
。Next, the back surface of the silicon wafer (1) is polished by selective polishing using a hard abrasive Um using an aqueous solution of an amine such as ethylenediamine as a polishing liquid. The insulating film (3) acts as a silicon polishing stopper,
In FIG. 1C, as in the above-mentioned FIG. (] 4)) has been polished. Silicon thin layer (14)
Its thickness is about 1,000 people. When the flattened area (8) in the wafer is exposed, the supply of polishing liquid is stopped and the area is rinsed with water for several minutes (1 to 5 minutes) to remove the area (8) and other areas (8) that are insufficiently polished. 9) Form a natural oxide film (12) on the silicon surface (see the first round)
.
水洗後、再度研磨液を供給し、研磨を行う。この研磨で
ば０１磨圧力の高い領域部（９）のみ研磨が進め、研磨
盤が絶縁層（３）に当接して研磨圧ノコが低くなった領
域部（８）では自然酸化膜（１２）が残ったままで、エ
ツチングが進行しない。つまり、この領域部（８）は研
磨停止状態となる（第１１ＤＥ参照）。After washing with water, supply the polishing liquid again and perform polishing. In this polishing, polishing progresses only in the area (9) where 01 polishing force is high, and in the area (8) where the polishing disk comes into contact with the insulating layer (3) and the polishing pressure is low, a natural oxide film (12) is formed. remains and etching does not proceed. In other words, this region (8) is in a polishing stopped state (see 11th DE).
次に、領域部（１０）が平坦化され島状シリコン薄層（
１４）が表われた所で研磨液の供給を止め、水洗した後
、再度研磨液を供給する。この操作をくり返しながら研
磨するごとにより、順次、表面に薄い自然酸化膜（１２
）を残した島状のシリコン薄層（１４）が形成され、最
終的に第１図Ｆに示すようにウェハ全面にこのような島
状のシリコン薄層（１４）か形成される。しかる後、表
面の自然酸化ＩＩＺ（＋２）をフッ酸系の溶液でエツチ
ング除去して第１図Ｇに示す目的のｓｏ＋基板（１５）
を得る。Next, the region (10) is planarized and the island-shaped silicon thin layer (
When 14) appears, stop supplying the polishing liquid, wash with water, and then supply the polishing liquid again. By repeating this operation and polishing, a thin natural oxide film (12
) is formed, and finally, as shown in FIG. 1F, such an island-like silicon thin layer (14) is formed on the entire surface of the wafer. Thereafter, the naturally oxidized IIZ(+2) on the surface was removed by etching with a hydrofluoric acid solution to obtain the desired SO+ substrate (15) shown in FIG. 1G.
get.
尚、この自然酸化膜（１２）を研磨ス１〜ツバ−として
利用する伯の製法としては、研磨液の供給を停止させず
に研磨状態のまま、研磨盤」−に過酸化水素（１１，０
□）等の酸化剤を供給しながら圧力差により、研磨圧力
が低くなった領域部のみ自然酸化膜（１２）を形成して
研磨停止状態として、連続研磨を可能にする方法をとる
こともできる。In addition, as for the manufacturing method using this natural oxide film (12) as the polishing plate 1 to 3, hydrogen peroxide (11, 0
It is also possible to adopt a method that allows continuous polishing by forming a natural oxide film (12) only in the area where the polishing pressure is low due to the pressure difference while supplying an oxidizing agent such as □) to stop polishing. .
上述の製法によれば、研磨が絶縁層（３）の面が露出す
る基準位置以下になると研磨圧力が低下することを利用
して、この部分に自然酸化膜（１２）を形成し、この自
然酸化膜（１２）を研磨（即ちエツチング）スＩ・ツバ
−に使うことにより、ウェハ内のシリヨン層が全面均一
な厚さに研磨できる。従っ゛ζウェハ全面にわたって絶
縁層（３）で分離された多数の均一な厚さの島状シリコ
ン薄層（１４）を有するＳＯＩ基板り１５）を製造する
ことができる。末法は特に１．０００人程度の極めて薄
いシリコン薄層（１４）を形成することができる。また
、研磨中に酸化剤を添加する方法を採用すれば研磨装置
を停止する必要がないので、連続研磨でＳＯＴ基板を製
作できる。そして、最も結晶性の良いバルクシリコンの
８０１基板を実現することができる。According to the above-mentioned manufacturing method, by utilizing the fact that the polishing pressure decreases when the polishing becomes below the reference position where the surface of the insulating layer (3) is exposed, a natural oxide film (12) is formed on this part, and this natural oxide film (12) is formed on this part. By using the oxide film (12) as a polishing (that is, etching) bath, the silicon layer within the wafer can be polished to a uniform thickness over the entire surface. Therefore, it is possible to produce an SOI substrate 15) having a large number of island-like thin silicon layers (14) of uniform thickness separated by insulating layers (3) over the entire surface of the ζ wafer. In particular, it is possible to form extremely thin silicon layers (14) of the order of 1,000 layers. Further, if a method of adding an oxidizing agent during polishing is adopted, there is no need to stop the polishing apparatus, so that SOT substrates can be manufactured by continuous polishing. Thus, an 801 bulk silicon substrate with the best crystallinity can be realized.
本発明によれば、貼り合せ後の選択ポリッシングによる
研磨が基準位置以下になるとき、研磨圧力が低■ζする
のを利用して、この部分に自然酸化膜を形成し、この自
然酸化膜を研磨（即ちエツチング）ストッパーとして使
うようにして研磨することにより、ウェハ内の半導体薄
層が全面均一な厚さに研磨することができる。従って最
も結晶性の良いバルク半導体よりなり１０００人程度の
極めて薄い島状半導体薄層を有するＳＯＩ基板を歩留り
よく製造することができる。According to the present invention, when polishing by selective polishing after bonding is below the reference position, a natural oxide film is formed on this part by taking advantage of the fact that the polishing pressure is low. By using the wafer as a polishing (ie, etching) stopper, the thin semiconductor layer within the wafer can be polished to a uniform thickness over the entire surface. Therefore, an SOI substrate having an extremely thin island-shaped semiconductor thin layer of about 1000 layers made of a bulk semiconductor with the best crystallinity can be manufactured with a high yield.
第１図Ａ−Ｇは本発明によるＳ○■基板の製法の一例を
示す工程図、第２図Ａ−Ｃは従来のＳＯ■基板の製法例
を示す工程図、第３図Ａ及びＩ３は本発明の説明に供す
る断面Ｖ、である。
（１）（５）はシリコンウェハ、（３）はＳｉＯ□層、
（４）は多結晶シリコン層、（７）（１５）はＳＯＩ基
板、（１２）は自然酸化膜、（１４）はシリコン薄層で
ある。
代
理
人
伊
藤
貞
同
松
隈
秀
盛
口
く
ロコFigures 1A to 1G are process diagrams showing an example of the method for manufacturing an SO■ board according to the present invention, Figures 2A to C are process diagrams showing an example of the conventional method for manufacturing an SO■ board, and Figures 3A and I3 are This is a cross section V used for explaining the present invention. (1) (5) is a silicon wafer, (3) is a SiO□ layer,
(4) is a polycrystalline silicon layer, (7) and (15) are SOI substrates, (12) is a natural oxide film, and (14) is a silicon thin layer. Agent Sadado Matsukuma Hidemoriguchi Kuloco
Claims (1)
、該半導体基板を選択ポリッシングにより研磨して半導
体薄層を形成する半導体基板の製法において、 基準位置まで研磨され研磨圧力の低下した半導体領域部
の表面に自然酸化膜を形成し、 該自然酸化膜をストッパーとして他の半導体領域部を研
磨することを特徴とする半導体基板の製法。[Claims] A method for manufacturing a semiconductor substrate in which a main surface of a semiconductor substrate is bonded to another substrate via an insulating layer, and the semiconductor substrate is polished by selective polishing to form a thin semiconductor layer, comprising polishing to a reference position. 1. A method for manufacturing a semiconductor substrate, comprising: forming a natural oxide film on the surface of a semiconductor region where the polishing pressure has been lowered; and polishing other semiconductor regions using the natural oxide film as a stopper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33149688A JP2762503B2 (en) | 1988-12-29 | 1988-12-29 | Semiconductor substrate manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33149688A JP2762503B2 (en) | 1988-12-29 | 1988-12-29 | Semiconductor substrate manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02178926A true JPH02178926A (en) | 1990-07-11 |
| JP2762503B2 JP2762503B2 (en) | 1998-06-04 |
Family
ID=18244293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33149688A Expired - Fee Related JP2762503B2 (en) | 1988-12-29 | 1988-12-29 | Semiconductor substrate manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762503B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665202A (en) * | 1995-11-24 | 1997-09-09 | Motorola, Inc. | Multi-step planarization process using polishing at two different pad pressures |
-
1988
- 1988-12-29 JP JP33149688A patent/JP2762503B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665202A (en) * | 1995-11-24 | 1997-09-09 | Motorola, Inc. | Multi-step planarization process using polishing at two different pad pressures |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2762503B2 (en) | 1998-06-04 |
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