JPH02178838A - Data processor - Google Patents

Abstract

PURPOSE:To increase the system speed without increasing the amount of hardware of an information processor by queuing data in accordance with the order from a main data sequence and preferentially performing the input of the main data sequence without waiting for the processing of data of a slave data sequence. CONSTITUTION:A data processor consists of an operand prefetch unit 100, an intermediate buffer 200 which queues a fetched operand and supplies it to an executing unit, an executing unit 300, a processor 400 including other units, and a main storage 500. Plural inputs are outputted in the order of input from the main data sequence, and contents of queued data are changed by the input from the slave data sequence. Consequently, it is unnecessary for the main data sequence to wait for the change input from the slave data sequence and the main data sequence is preferentially operated when an input sequence is independently operated. Thus, the device speed is increased without increasing the amount of hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device for improving the speed of a microcomputer system without significantly increasing the hardware in the information processing device.

2. Description of the Related Art A conventional data processing device is shown in FIG. In FIG. 5, 1 is a first-in first-out memory (hereinafter referred to as FIFO) for queuing data. 2
is an input data line, 3 is an input line that requests data storage, 4 is a register that holds data, 5 is a read pointer 8 that indicates the data to be read by the FIFO control unit, and a write pointer 7 that indicates the register to be written. Output. 6 is a data line to be output. The data input from 2 is temporarily held in the register 4, and is output from 6 in the order in which it was input.

Problem to be Solved by the Invention However, with the configuration shown in FIG. 5 above, it is impossible to update the contents of data already queued in the FIFO without changing the order. Then, it is necessary to confirm that data processing is completely completed and then issue a storage request to the FIFO. For this reason, even if there are multiple input sides to the FIFO and each of them can operate independently, there is a problem in that the operation must be stopped to wait for input to the FIFO. In view of this, the present invention has a plurality of input lines, data, and a flag indicating the end of data processing,
- By making it possible to change the unprocessed data that has been inputted using the data at the update cutting edge indicated by the flag, the unprocessed input is stored in advance and the order is secured, and the data is output after the data has been changed. By doing this, the purpose is to give precedence to the input side to the buffer in the information processing device, reduce the control burden, and improve the speed of the device without increasing the hardware.

SUMMARY OF THE INVENTION The present invention provides a buffer with a plurality of inputs and flags indicating data and data processing information, and changes the data at the location indicated by the set flag without changing the queued order. This device is equipped with a control section that performs the following steps.

Effects The present invention has the above-described configuration, so that the present invention can respond to a plurality of inputs by
By outputting data in the order in which it was input from the main data series and changing the contents of the queued data based on the input from the slave data series, when the input series operate independently, the main data series becomes the slave data series. To improve the performance of an information processing device by operating a main data series in advance without having to wait for a change input from a computer.

EXAMPLES Hereinafter, the present invention will be explained in detail by way of examples with reference to the drawings.

FIG. 1 shows a data processing apparatus in a first embodiment of the present invention. 100 is an operand advance fetch unit; 200 is an intermediate buffer that queues fetched operands and supplies the operands to the execution unit; 300 is an execution unit; 400 is a processor including other units; and 500 is a main memory.

The 100 operand pre-fetch units contain 101 cache memories. Reference numeral 102 denotes an operand advance fetch unit control unit.

103 is a cache read request line, 104 is an address line for reading the cache, and 105 is a signal line for notifying the operand prefetch unit of a cache miss. Reference numeral 107 is a request line for reading from the main memory when a cache miss occurs. 201 is an intermediate buffer control unit; 202 and 203 are selection devices that select data read from the cache 106 and data read from the main memory 501; 204 and 205, respectively;
control line. 206.2゜7 queues the pre-fetched operand in the queuing register,
In the embodiment, it is composed of two sets of registers. 208.20
A flag section 9 indicates the state of the operand held in 206 and 207, and consists of a valid bit (hereinafter referred to as the V bit) and a bit indicating that reading is not possible (hereinafter referred to as the R bit). 210 and 211 are control lines for setting flags. A selection device 212 selects data from two sets of registers, and is controlled by a control line 213. 21
4.215 is a signal line through which the control section reads the flag. 2
16 is a data line that supplies operands to the execution unit;
217 is a signal line indicating validity/invalidity of data. 30
1 is a request line from which the execution unit reads data and requests the next operand. A signal line 502 indicates the end of reading from the main memory.

FIG. 2 shows the operation of the asynchronous pipeline in the embodiment.

FIGS. 2(a) and 2(b) show the operation of the pipeline from operand advance fetching to execution.

FIG. 2(a) shows when the cache is hit, and the main memory is not read, but the cache is read and executed.

FIG. 2(b) shows when a cache miss occurs, and operations are performed by reading from the cache, reading from the main memory, and executing.

Cache reading and execution are each performed in one cycle, and main memory reading is performed in two cycles.

The operation of the data processing apparatus of this embodiment configured as described above will be described below.

The operand pre-fetch uni-soto control unit of 102 is as follows:
The cache is accessed by the address 104 in response to the fetch request 103, and the cache notifies the control unit of the cache hit/miss of that address.

In the event of a hit, the operand pre-fetch unit control section notifies the data storage request and cache hit via the request line 108. The intermediate buffer control unit 201 is
When the next register to write to is 206, write data 106 to register 206 and set flag 210 to (■=
1, R=O). Further, when the next register to be read is 206, the control unit 201 selects the data 206 by the selection device 212, and since the flag 208 is valid and can be read, the signal line 217 indicates that the data is valid. Notify the execution unit.

When a miss occurs, the operand prefetch unit controller notifies the intermediate buffer controller of the cache miss through 108, and
The main memory read is activated by the address line 107 and the main memory read request line 107. When the next register to be written to is 206, the intermediate buffer control unit 201 controls the register 206.
Write 106 invalid data to the register and set flag 21.
0 to (V=1, R=1). Further, when the next register to be read is 208, the control unit 201 selects the data 206 by the selection device 212, and indicates that the data is invalid by the signal line 217 since the flag 208 is valid and cannot be read. Notify the execution unit. When the intermediate buffer control unit is notified of the completion of reading from the main memory by 502, data 501 is written to the register 206 in which the operand that activated the main memory access is stored, and the R bit 208 is reset.

The R bit is reset and 208 is (V=L R=0)
Therefore, the intermediate buffer control unit notifies the execution unit through the signal line 217 that the data is valid.

When the above cache miss occurs, when the cache read of the next operand is completed while the main memory is being read, and the operand advance fetch unit requests the intermediate buffer to store data, the intermediate buffer control unit , 207, and set the flags of 209 to (V=1, R=0). At this time also 206
Since the data of 206 is not read, the data of 206 is output from 216. Since the R bit of the flag of 208 is set, the execution unit is not read, and the main memory of 206 is read. Finished, 206
Since the readout of 207 is performed after the readout of the operands, the order of the operands is maintained.

Notification of completion of main memory access of nth operand and n+
When a cache data storage request for the first operand occurs in the same cycle, writing can be performed simultaneously in 206 and 207 by selecting with the selection devices 202 and 203.

As described above, regardless of cache hits or misses, a flag indicating that data cannot be read is stored together with a valid flag in an intermediate buffer between pipelines, and the FIFO performs not only data transfer but also synchronization management between units. This reduces the burden on the control section of the operand pre-fetch unit, which is one stage of the pipeline, and
Even when a cache miss occurs, the operand pre-fetch unit can read the next operand from the cache in advance without having to wait and stop reading the main memory, which improves performance. I can do it.

FIG. 3 shows the operation of the pipeline in an embodiment where successive operands are a cache miss, a cache hit, and a cache miss.

FIG. 3(a) shows a case where a conventional FIFO is used as an intermediate buffer, and it takes eight cycles from the start of operand fetching to the end of execution.

FIG. 3(b) shows a case where the device of the present invention is used as an intermediate buffer, and it takes seven cycles from the start of operand fetish to the end of execution.

FIG. 4 shows a second embodiment. 10 is an instruction execution unit, 11
12 is a data line from the instruction execution unit; 12 is an input line indicating a data storage request and the state of the data; 13 is an input line from the preceding processing device; 20 is a buffer; and 21 is a data output line. 30 is a multiplier, 31 is a data line from the multiplier, 32 is an input line indicating a data storage request, 33 is a data line from the divider, 40 is a divider, and 41 is an input line indicating a data storage request. be.

11 when the data processing is completed in the instruction execution unit 10.
12 notifies data, 12 notifies the end of processing, and 20 buffer stores valid data. When the data processed by the instruction execution unit 10 requires further multiplication processing, a storage request from 12 and an input from 30 notify that the data needs to be changed. Buffers at 20 set flags in the appropriate locations, making the data unreadable until 30 more valid data is available. When the instruction execution unit 10 receives a data storage request in the intermediate buffer, it can perform the next execution process in advance.

As mentioned above, regardless of whether data processing is completed or not,
By being able to continue executing the preceding main data series and performing parallel processing,
The speed of the system can be improved.

As described in detail, according to the present invention, the buffer has a plurality of input sequences, performs queuing according to the order starting from the main data sequence, and inputs the main data sequence without waiting for the processing of the data of the secondary data sequence. Since the data series can be input in advance, the performance can be improved without increasing the hardware of the information processing device, and it is extremely easy to implement on an LSI, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device in a first embodiment of the present invention, FIG. 2 is a timing chart showing pipeline operation in the embodiment of the present invention, and FIG. 3 is a conventional example and an embodiment of the present invention. FIG. 4 is a block diagram showing a data processing device according to a second embodiment of the present invention, and FIG. 5 is an explanatory diagram of a conventional example. 100... Operand advance fetch unit, 101
... cache memory, 102 ... operand advance fetch unit control section, 200 ... intermediate buffer,
201... Intermediate buffer control unit, 202... Selection device A, 203... Selection device B1206... Register A1207... Register B1208... Flag A1
209... Flag B, 212... Selection device C, 30
0... Execution unit, 400... Processor, 50
0... Main memory, 10... Instruction execution section, 20... Buffer 3°... Multiplier, 40... Divider.

Claims (1)

[Scope of Claims] An input line for inputting processing information indicating whether or not there is a need for data and data processing and, if processing is required, a processing system for inputting the processed data, and the input line a plurality of change lines for inputting input and processed data; a selection device for selecting data from the input line and the plurality of change lines; and a data storage section for holding data selected by the selection device; A register file that has multiple entries with flags that hold processing information indicating whether or not data is to be processed and the input system of data after processing, the output line from the register file, and the order of output from the register file are determined by the input line If the processing information of the flag of the next entry to be output indicates that processing is not completed, it indicates that the data in the register file cannot be read, and after processing from the change line. If data is input, the processing information in the register file is changed to the data of the first input entry among the entries whose processing has not yet been completed and the input system after processing matches, and the processing information flag is processed. 1. A data processing device, comprising: a control section that enables reading of data upon completion of the processing.