JPH02177689A - Filter control circuit - Google Patents

Abstract

PURPOSE:To ensure the optimum control of the picture quality of the input signal by controlling a filter circuit with the output signal of an adder defined as a coefficient. CONSTITUTION:When a clock signal 46 is equal to fck, a filter circuit consisting of the latch circuits 38 and 39 and an adder 40 serves as a notch filter circuit which is expressed in (1+Z<-2>) and has a fck/4 frequency. The output signal 18 of a YC separating circuit is applied to the notch filter circuit and multiplied by a coefficient L. At the same time, the signal 18 is multiplied by a coefficient (1-L) and a signal 20 is obtained with the output signals of both multipliers 41 and 42 added together via an adder 45. Thus the detection signal of a non- standard detection circuit 10 is used as a coefficient. As a result, it is possible to actuate effectively the notch filter circuit in accordance with the non-standard degree of an input signal as well as with the ON/OFF binary state. Thus the pictures of high quality are obtained with no disturbance of dots.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a high-definition television receiver using a frame memory, which determines the state of an input signal and optimizes a notch filter circuit connected to the output of a YC separation circuit. The present invention relates to a filter control circuit that controls the filter control circuit.

2. Description of the Related Art In recent years, there has been a growing trend toward higher image quality in television receivers, and high-quality televisions using frame memories are being actively developed.

The above-mentioned high-definition television receiver using a conventional frame memory will be explained below with reference to the drawings. In the figure, 1 is a first inter-frame YC separation circuit for separating luminance signals using a frame memory;
2 is a first line-to-line YC separation circuit for separating luminance signals using line memory, 3 is a motion detection circuit for detecting movement of luminance signals and color difference signals, and 4 is a frame memory for separating color difference signals. 5 is a second inter-line YC separation circuit for separating luminance signals using a line memory; 6.7 is a motion detection circuit 3 for each signal; 8 is a bandpass filter for extracting the chroma signal component of the video signal 12, and 9 is a color demodulation circuit for obtaining a color difference signal. , 1o indicates that the input video signal 12 is NTS
11 is a notch filter circuit for removing dot interference in the YC-separated luminance signal 18; 2o is the YC-separated luminance signal output; 19 is the YC-separated color difference signal output. be.

The operation of the filter control circuit configured as above will be explained.

If, the video signal 12 is applied to the interframe YC separation circuit 1 and the interline YC separation circuit 2 to obtain respective luminance signal outputs 14.15. On the other hand, for video [-12, a chroma signal is extracted by a bandpass filter 8, demodulated into a color difference signal 13 by a color demodulation circuit 9, and applied to an interframe YC separation circuit 4 and an interline YC separation circuit 5, and the chroma signal is extracted by a bandpass filter 8. Signal output signal 16.17 is obtained.

At the same time as this processing, the video signal 12 and the color difference signal 13 are applied to the motion detection circuit 3, which detects the motion of each signal, and when it is determined that the signal is stationary, as shown in FIG. In response to the signal 21, the switch 6.7 selects the output signal 14.16 of the interframe YC separation circuit 1.4 to obtain an interframe YC separated signal of high image quality free of dot interference and cross color. When it is determined that it is a moving image, the switch 6.7 selects the output signal 15.17 of the line-to-line YC separation circuits 2 and 5 according to the signal 21, and the high-quality image with less cross color is produced by line-to-line YC separation. get the signal. These signal processes, especially inter-frame YC separation, can accurately perform YC separation when the input signal is, for example, a standard NTSC signal.
High quality signals without dot interference and cross color can be obtained.

However, in the above configuration, if the input signal deviates from the standard NTSC signal, for example, the relationship between the frequency FsC of the color subcarrier signal and the frequency Fh of the horizontal synchronization signal is as follows for the NTSC signal. F = (46s/2)XFh ・・・・・・・・・
・・・・・・(1) The relationship of C is satisfied, but in the case of equipment such as home VTRs, considering the recording method, it is not necessarily true that the relationship of (1) is satisfied. No. In the case of an input signal that does not satisfy equation (1), if inter-frame YC separation processing is performed, the correlation between frames of the chroma signal is missing, so dot interference and cross-color interference will occur. Furthermore, due to recording system jitter, etc., the correlation between lines of the chroma signal may be missing, so even if line-to-line YC separation processing is performed, the luminance Dot interference will occur in the signal.

For this purpose, it is conceivable to provide a notch filter circuit shown in FIG. 4 and remove the dot interference generated in the luminance signal output 18 of the YC separation circuit.

The notch filter circuit is configured so that the video signal 12 is NTSC.
By operating the signal when the signal is not a signal (herein referred to as a non-standard signal), it is possible to eliminate the dot interference in the home VTR and the like. Therefore, a signal detection circuit shown in FIG. 4 is used to determine whether the input signal 12 is an NTSC signal.

Next, the signal detection circuit 10 will be explained. FIG. 6 shows its block diagram. In FIG. 6, 21 is a one-frame delay circuit, 22 is an adder, 23 is a band-hasfy),
24 is an absolute value circuit, 26 is a peak detection circuit, 26 is a latch circuit, 47 is a comparator, 27 is a notch filter circuit, 4
9 is a switch circuit. The operation of the signal detection circuit 10 will be explained based on FIGS. 6 and 7. The input signal 12 is shown in FIG. 6a, with the burst signal portion emphasized. The input signal 12 is delayed by a one frame delay circuit and becomes a signal 32 shown in FIG. Figure 6 shows
A case is shown in which the input signal 12 is an NTSC signal, and the burst signal of the signal 32 delayed by the one frame delay circuit is exactly 180 degrees out of phase with respect to the input signal 12. Therefore, the output signal 33 of the adder 22 is as shown in FIG.
The burst signal portion is removed as shown in FIG. The output signal of the bandpass filter 23 has no signal in the burst signal portion as shown in FIG. 6d, and the output signals 36 and 36 of the absolute value circuit 24 and the peak detection circuit 25 are also as shown in FIGS. 6e and f. become.

Therefore, when the position of the burst signal is launched in the latch circuit 26 by the burst gate pulse 31 shown in FIG. Output signal 5o
When υ is at a low level, the switch 49 shown in FIG. 5 selects the signal 18, that is, the notch filter 27 is turned off.

Next, consider a case where a non-standard signal is input.

The operation will be explained based on FIG.

The input signal 12 is delayed by a one frame delay circuit and becomes a signal 32 shown in FIG. At this time, FIG. 7 shows a case where the input signal 12 is a non-standard signal, and the burst signal of the signal 32 delayed by the one frame delay circuit is NT
Unlike the SC signal, the phase is not shifted by 180 degrees with respect to the input signal 12, but there is a shift of phase φ. Therefore, the burst signal portion of the output signal 33 of the adder 22 remains without being removed, as shown in FIG. 7C. The output signal of the bandpass filter 23 is the seventh
The burst signal portion is extracted as shown in Figure d.

The output signal of the absolute value circuit 24 is as shown in FIG. 7e, and the output signal 36 of the peak detection circuit 26 is oscillated by the amount by which the burst signal deviates during one frame, as shown in FIG. 7f. It appears as a. Therefore, uh, Sochi circuit 2
6, when the position of the burst signal is latched by the burst gate pulse 31 shown in FIG. The switch 49 shown in FIG. 6 selects the signal 52, that is, the notch filter 27 is turned on.

When the signal inputted by the signal detection circuit 10 as described above is a non-standard signal, a luminance signal free from dot interference can be obtained by operating the notch filter.

Here, a specific example of a notch filter circuit is shown in FIG. In FIG. 8, 38 and 39 are latch circuits, 4o is an adder, and 46 is a clock signal. Now, the clock signal 46
When fck, the filter circuit composed of the latch circuits 38 and 39 and the adder 40 is a notch filter circuit represented by (1+Z), and has a pole at the frequency of 9fck/4. Therefore, its characteristics are as shown in FIG.

Problems to be Solved by the Invention However, with the above configuration, the notch filter is always turned on for signals other than NTSC signals, which deteriorates the resolution, etc., regardless of the degree of non-standardization of the input signal. Furthermore, as the performance of home VTRs continues to improve year by year, there is a growing need to perform optimal high-quality signal processing on various signals.

The present invention solves the above problem and provides a filter control circuit for determining the state of a signal input to a YC separation circuit and performing optimal high-quality signal processing according to the result.

Means for Solving the Problems To achieve this object, the filter control circuit of the present invention includes a circuit for detecting inter-frame correlation of burst signals of input signals, a notch filter circuit connected to a luminance signal output, Function of the device: A filter control circuit configured to control the notch filter circuit using an interframe correlation signal of a burst signal. In order to perform image quality YC separation,
By determining the regularity of the input signal, a filter circuit for removing dot interference in the luminance signal output from the YC separation circuit is controlled.

Embodiment An embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a block diagram of a filter control circuit in one embodiment of the present invention.

In FIG. 1, 21 to 27 and 31 to 37 are the same as those shown in the description of the conventional example, and the description thereof will be omitted.

28 is a first coefficient circuit that generates a coefficient (1-L) in response to a signal 37; 29 is a second coefficient circuit that generates a coefficient in response to a signal 37; and 30 is an adder.

The operation of the filter control circuit configured as above will be explained. The method of obtaining the frame sum signal of the burst signal from the input signal 12 is the same as the conventional example up to the launch output signal 37. The feature of the present invention is the first
Using signal 37, coefficient circuits 28 and 29 as shown in the figure
The purpose is to control the effect of the notch filter in stages by driving the notch filter.

As shown in Figure 7, the signal 37 is data with an amplitude K and is processed by the coefficient circuit 29 such that 0≦L (K)≦1 L is a coefficient that satisfies the function of K, that is, when K is large, L is large;
When L is small, a coefficient is generated such that L is small. Also,
Coefficient circuit 28 generates a coefficient (1-L).

Here, an example of the filter control circuit will be explained based on FIG. 2. In Figure 2, 38.39 is a latch circuit, 40
．． 45 is an adder, 41.42 is a multiplier, 43.44 is a coefficient unit that generates coefficients (1-L) and L, respectively, 46
is the clock signal.

Now, when the clock signal 46 is fck, the latch circuit 3
The filter circuit composed of 8.39 and the adder 40 is a notch filter circuit represented by (1+Z) and has a pole at the frequency of fck/4. The output signal 18 of the YC separation circuit is applied to a notch filter circuit constituted by 38, 39, 40 in FIG. 2 and multiplied by a coefficient. - On the other hand, the signal 18 is the coefficient (1
-L), and the output signals of multipliers 41 and 42 are added by adder 46 to obtain signal 2o.

Therefore, the signal 20 is L=o as shown in FIG.
When the notch filter effect is 0FFO≦L≦1, the notch filter effect is intermediate, and when L=1, the notch filter effect is maximum.

In this way, by using the detection signal 37 of the non-standard detection circuit 10 as a coefficient, the notch filter circuit can be simply reduced to zero.
It is possible to operate effectively not only according to binary values such as N10FF but also according to the degree of non-standard input signal. This means that due to the difference in performance of the same home VTR, those with good performance can suppress the effect of the notch filter circuit and suppress the deterioration of resolution, and the effect of the notch filter circuit can be maximized for recorded images with a lot of jitter. It is possible to obtain high-quality images without dot interference.

Effects of the Invention As described above, according to the present invention, in a high-quality signal processing circuit using a frame memory, by detecting the state of an input signal, it is possible to determine the optimal notch filter circuit according to each signal. The image quality of the input signal can be optimally controlled. This invention is based on I.D.T.
V (ImprovetiDefinition T
V ) and E D T V (Extended Defi
This technology is compatible with various input signals such as TV, TV, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a filter control circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the notch filter control circuit in FIG. 1, and FIG. 3 is an embodiment of the present invention. 4 is a block diagram of a filter control circuit with a conventional notch filter circuit, FIG. 5 is a block diagram showing a specific example of a conventional filter control circuit, and FIGS. FIG. 7 is an explanatory diagram of the operation of the filter control circuit, FIG. 8 is a block diagram of a conventional notch filter circuit, and FIG. 9 is a characteristic diagram of the notch filter circuit shown in FIG. 21...1 frame delay circuit, 22...Adder, 23...Band pass filter, 24...R absolute i. 26...Peak detection circuit, 26...Latch circuit, 27...Notch filter circuit. Name of agent Patent attorney Shigetaka Awano and one other person (c) 4; 37 N ------ (i) 4i sa-90 FF Figure Figure

Claims (4)

[Claims] (1) A video signal, a delay circuit that delays the video signal for one frame period, an adder that adds the video signal and the output signal of the delay circuit, and a filter circuit that can vary the filter effect depending on input coefficients. A filter control circuit characterized in that the filter circuit is controlled using the output signal of the adder as a coefficient. (2) A latch circuit that latches only the burst signal period of the output signal of the adder is provided, and the filter circuit is controlled using the output signal of the latch circuit as a coefficient. 1. The filter control circuit according to 1. (3) Equipped with a bandpass filter that extracts the burst signal from the output signal of the adder, an absolute value circuit that takes the absolute value of the output signal of the bandpass filter, and a peak detection circuit that peak-detects the output signal of the absolute value circuit. 3. The filter control circuit according to claim 1, wherein the output signal of the peak detection circuit is applied to the latch circuit. (4) The filter control circuit according to claim 1, 2 or 3, wherein the filter circuit is a notch filter circuit.