JP2727611B2 - Filter control circuit - Google Patents

Description

The present invention relates to a high-definition television receiver using a frame memory, which determines the state of an input signal and optimizes a notch filter circuit connected to an output of a YC separation circuit. The present invention relates to a filter control circuit for controlling the above.

2. Description of the Related Art In recent years, the trend toward higher image quality of television receivers has been increasing.
High-definition televisions using frame memories are being actively developed.

Hereinafter, the above-described high-definition television receiver using a conventional frame memory will be described with reference to the drawings.
FIG. 4 is a block diagram of a conventional high image quality television receiver. In FIG. 4, reference numeral 1 denotes a first inter-frame YC separation circuit for separating a luminance signal using a frame memory.
Is a first method for separating a luminance signal using a line memory.
3 is a motion detecting circuit for detecting the motion of a luminance signal and a color difference signal, 4 is a second inter-frame YC separating circuit for separating a color difference signal using a frame memory, and 5 is a line memory. , A second line-to-line YC separation circuit for separating the luminance signal by using the YC separation between the frame and the line according to the output signal 21 of the motion detection circuit 3 for each signal. A switch for adaptively switching between the two, 8 is a band-pass filter for extracting a chroma signal component of the video signal 12, 9 is a color demodulation circuit for obtaining a color difference signal, and 10 is whether the input video signal 12 is an NTSC signal. 11 is a notch filter circuit for removing dot interference in the luminance signal 18 separated by YC, and 20 is a notch filter circuit.
YC-separated luminance signal output 19 is a YC-separated color difference signal output.

Regarding the filter control circuit configured as described above,
The operation will be described.

First, the video signal 12 is applied to the inter-frame YC separation circuit 1 and the inter-line YC separation circuit 2, and outputs the respective luminance signal outputs.
Gain 14,15. On the other hand, the chroma signal is extracted from the video signal 12 by the band-pass filter 8, demodulated into a color difference signal 13 by the color demodulation circuit 9, added to the inter-frame YC separation circuit 4 and the inter-line YC separation circuit 5, Output signals 16 and 17 are obtained.

Simultaneously with this processing, the video signal 12 and the color difference signal 13 are applied to the motion detection circuit 3 to detect the motion of each signal, and when it is determined that the signals are stationary, as shown in FIG. In response to the signal 21, the switches 6 and 7 select the output signals 14 and 16 of the inter-frame YC separation circuits 1 and 4 to obtain a high-quality signal which is YC separated between frames and free from dot disturbance and cross color. When it is determined that the moving image is a moving image, the switches 6 and 7 are output from the inter-line YC separation circuits 2 and 5 by the signal 21.
15 and 17 are selected to obtain a high-quality signal with little cross color and YC separation between lines. These signal processings, especially inter-frame YC separation, can accurately perform YC separation when the input signal state is, for example, a standard NTSC signal, and achieve high image quality without dot interference and cross color. Can be obtained.

However, in the configuration described above, the signal input is if deviates from the standard NTSC signal, for example, relationship between the frequency F _SC of the color subcarrier signal frequency Fh of the horizontal synchronizing signal is the NTSC signal , F _SC = (455/2) × Fh satisfies the relationship of (1), but in the case of a device such as a home VTR, the relational expression of expression (1) is not necessarily considered from the recording method. I'm not satisfied. In the case of an input signal that does not satisfy the expression (1), if the YC separation process between frames is performed,
Since the correlation between the frames of the chroma signal is lacking, an adverse effect of increasing dot disturbance and cross-color disturbance occurs. Further, the correlation between the lines of the chroma signal may be lost due to the jitter of the recording system or the like, so that even if the inter-line YC separation processing is performed, dot interference occurs in the luminance signal.

For this purpose, it is conceivable to provide a notch filter circuit shown in FIG. 4 to eliminate dot interference generated in the luminance signal output 18 of the YC separation circuit. By operating the notch filter circuit when the video signal 12 is a signal that is not an NTSC signal (hereinafter referred to as a non-standard signal), the dot interference in the home VTR or the like can be removed. Therefore, the signal detection circuit shown in FIG. 4 is used to determine whether the input signal 12 is an NTSC signal.

Next, the signal detection circuit 10 will be described. FIG. 5 shows a block diagram thereof. In FIG. 5, 21 is a one-frame delay circuit, 22 is an adder, 23 is a band-pass filter, 24 is an absolute value circuit, 25 is a peak detection circuit, 26 is a latch circuit, 47 is a comparator, and 27 is a notch filter circuit. , 49 are switch circuits. The operation of the signal detection circuit 10 will be described with reference to FIGS. The input signal 12 is shown in FIG. 6a, and the burst signal portion is emphasized and expressed. The input signal 12 is delayed by a one-frame delay circuit to become a signal 32 shown in FIG. 6B. FIG. 6 shows a case where the input signal 12 is an NTSC signal, and the burst signal of the signal 32 delayed by the one-frame delay circuit has exactly the phase of the input signal 12.
180 degrees off. Therefore, the burst signal portion of the output signal 33 of the adder 22 is removed as shown in FIG. 6c. As shown in FIG. 6d, the output signal of the band-pass filter 23 has no signal in the portion of the burst signal, and the output signals 35 and 36 of the absolute value circuit 24 and the peak detection circuit 25 are also shown in FIGS. 6e and f. become. Therefore, when the position of the burst signal is latched by the burst gate pulse 31 shown in FIG. 6q in the latch circuit 26, the signal becomes a signal 37, and the signal level is zero level. The signal goes low, and the switch 49 shown in FIG. 5 selects the signal 18, that is, the notch filter 27 is turned off.

Next, consider a case where a non-standard signal is input. The operation will be described with reference to FIG.

The input signal 12 is delayed by a one-frame delay circuit and FIG.
A signal 32 shown in FIG. At this time, FIG. 7 shows a case where the input signal 12 is a non-standard signal, and the burst signal of the signal 32 delayed by the one-frame delay circuit has a phase exactly 180 ° with respect to the input signal 12 like an NTSC signal. The relationship is not shifted by degrees, but is shifted by the phase φ. Therefore, the output signal 33 of the adder 22 remains without removing the burst signal portion as shown in FIG. 7c. As shown in FIG. 7D, a burst signal portion is extracted from the output signal of the band-pass filter 23. The output signal of the absolute value circuit 24 is as shown in FIG. 7e, and the output signal 36 of the peak detection circuit 25 has a burst signal of 1 as shown in FIG. 7f.
It appears as the amplitude K by the amount shifted between frames.
Therefore, when the position of the burst signal is latched by the latch circuit 26 by the burst gate pulse 31 shown in FIG. 7q, the signal level becomes K as in the signal 37, and the output signal 50 becomes high when compared with the value N in the comparator 47. The switch 49 shown in FIG. 5 selects the signal 52, that is, the notch filter 27 is turned on.

When the signal input by the signal detection circuit 10 as described above is a non-standard signal, a luminance signal free from dot interference can be obtained by operating the notch filter.

Here, a specific example of the notch filter circuit is shown in FIG.
In FIG. 8, 38 and 39 are latch circuits, 40 is an adder, 46
Is a clock signal. Now, when the clock signal 46 is fck, the filter circuit composed of the latch circuits 38 and 39 and the adder 40 is a notch filter circuit represented by (1 + Z- ² ) and has a pole at a frequency of fck / 4. Therefore, the characteristics are as shown in FIG.

However, in the above configuration, the notch filter is always turned on except for the NTSC signal regardless of the degree of non-standardity of the input signal, and the resolution and the like are deteriorated. In addition, since the performance of home VTRs has been improving year by year, it is necessary to perform optimal high-quality signal processing on various signals.

The present invention has been made in view of the above problems, and provides a filter control circuit for determining a state of a signal input to a YC separation circuit and performing optimal high-quality signal processing according to the result.

Means for Solving the Problems To achieve this object, a filter control circuit of the present invention includes a circuit for detecting an inter-frame correlation of a burst signal of an input signal, a notch filter circuit connected to a luminance signal output, The filter control circuit is configured to control the notch filter circuit using a signal of inter-frame correlation of the burst signal.

Operation With this configuration, the present invention provides an optimal high-quality YC separation for a signal connected to a television receiver.
By determining the regularity of the input signal, a filter circuit for removing dot interference in the luminance signal output from the YC separation circuit is controlled.

Embodiment An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a filter control circuit according to an embodiment of the present invention. In FIG. 1, 21
27 to 31 to 37 are the same as those described in the description of the conventional example, and the description is omitted.

28 is a first coefficient circuit for generating a coefficient (1-L) according to the signal 37, 29 is a second coefficient circuit for generating a coefficient L according to the signal 37, and 30 is an adder.

Regarding the filter control circuit configured as described above,
The operation will be described. For the method of obtaining the frame sum signal of the burst signal from the input signal 12, see the output signal of the latch.
Up to 37 is the same as the conventional example. The feature of the present invention resides in that the effect of the notch filter is controlled stepwise by driving the coefficient circuits 28 and 29 using the signal 37 as shown in FIG.

The signal 37 is data having an amplitude K as shown in FIG. 7h, and 0 ≦ L (K) ≦ 1 L is a coefficient satisfying the function of K by the coefficient circuit 29, that is, L is large when K is large, and K is large.
Is small, a coefficient is generated such that L is small. Also,
The coefficient circuit 28 generates a coefficient (1-L).

Here, an example of the filter control circuit will be described with reference to FIG. In FIG. 2, 38 and 39 are latch circuits, 40 and 45 are adders, 41 and 42 are multipliers, and 43 and 44 are coefficients (1-
L) and a coefficient unit for generating L, 46 is a clock signal.

Now, when the clock signal 46 is fck, the filter circuit composed of the latch circuits 38 and 39 and the adder 40 is a notch filter circuit represented by (1 + Z- ² ) and has a pole at a frequency of fck / 4. The output signal 18 of the YC separation circuit is 38, 39, 40 in FIG.
And is multiplied by a coefficient L. On the other hand, the signal 18 is multiplied by a coefficient (1-L),
The output signals of the multipliers 41 and 42 are added by the adder 45 to obtain the signal 20.

 Therefore, as shown in FIG. 3, the signal 20 has a notch filter effect when L = 0, a notch filter effect when 0 ≦ L ≦ 1, and a maximum notch filter effect when L = 1.

As described above, the notch filter circuit is simply turned on / off by using the detection signal 37 of the non-standard detection circuit 10 as a coefficient.
It can be effectively operated according to the non-standard degree of the input signal as well as the binary value such as FF. This means
Even for the same home-use VTR, the one with good performance due to the difference in performance can suppress the effect of the notch filter circuit and suppress the deterioration of the resolution.For recorded images with a lot of jitter, the effect of the notch filter circuit can be maximized to reduce the dot interference. Not high images can be obtained.

Effects of the Invention As described above, according to the present invention, in a high image quality signal processing circuit using a frame memory, by detecting the state of an input signal, an optimum notch filter circuit corresponding to each signal can be obtained. It is possible to control the operation and optimally control the image quality of the input signal. The present invention relates to IDTV (Im
proved Definition TV) or EDTV (Extended Definition)
This is a technology that can respond to various input signals such as TV.

[Brief description of the drawings]

FIG. 1 is a block diagram of a filter control circuit in one embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of a notch filter control circuit in FIG. 1, and FIG. 3 is an embodiment of the present invention. , FIG. 4 is a block diagram of a conventional filter control circuit having a notch filter circuit, FIG. 5 is a block diagram showing a specific example of a conventional filter control circuit, and FIGS. 7 is an explanatory diagram of the operation of the filter control circuit, FIG. 8 is a block diagram of a conventional notch filter circuit, and FIG. 9 is a characteristic diagram of the notch filter circuit shown in FIG. 21 ... one frame delay circuit, 22 ... adder, 23 ... bandpass filter, 24 ... absolute value circuit, 25 ... peak detection circuit, 26 ... latch circuit, 27 ... notch filter circuit.

Claims (2)

(57) [Claims] 1. A delay circuit for delaying a video signal by one frame period, an adder for adding the video signal and an output signal of the delay circuit, and latching only a burst signal period of the adder output signal. A latch circuit, a filter circuit that can vary the effect of the filter by an input coefficient, and a notch filter that removes dot interference of a luminance signal, wherein the filter circuit has a first coefficient according to an output signal of the latch circuit. A first coefficient generating circuit for generating L and multiplying the output signal of the notch filter by the first coefficient L and outputting the same; and a second coefficient (1-L) according to the output signal of the latch circuit. And the second signal is added to the luminance signal.
And a second coefficient generation circuit that multiplies the coefficient (1-L) by multiplying the output of the first coefficient generation circuit and the output of the second coefficient generation circuit. Filter control circuit. 2. A band pass filter for extracting a burst signal from an output signal of an adder, an absolute value circuit for obtaining an absolute value of the output signal of the band pass filter, and a peak for detecting a peak of the output signal of the absolute value circuit. The filter control circuit according to claim 1, further comprising a detection circuit, wherein an output signal of the peak detection circuit is applied to a latch circuit.