JPH02177047A - Servo device for capstan motor - Google Patents

Abstract

PURPOSE:To make the phase stable by varying a frequency division ratio of a 1/m frequency divider and a 1/n frequency divider respectively. CONSTITUTION:When a capstan motor 11 is brought into a multiple of m/n, the frequency of a speed signal FG is (m/n)f and frequency-divided into (1/n)f by a frequency divider 41. Thus, the loop keeps the frequency stably to keep the frequency of the signal FG to a constant value. In the case of m/n multiple variable speed of reproduction, the frequency f2 of a control pulse (CTL) is (m/n)f2 and the frequency f2 becomes (1/n)f2 when it is inputted to a phase comparator 52 and compared with an output f0(1/n) of a frequency divider 55 (f0 is a frequency of a voltage controlled oscillator 54). In response to the phase comparison, the oscillated output is controlled and the loop is operated so that the frequency (m/n)f2 is kept constant. Thus, the phase is made stable.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) This invention relates to a servo device for a capstan motor of a video tape recorder (hereinafter referred to as VTR).

(Prior Art) In a VTR, there are a Herad servo device for keeping the rotational speed of a rotating head constant, and a capstan servo device for a capstan motor that drives a tape that is helically scanned by the rotating head.

Some recent VTRs are designed to allow switching of the recording speed and playback speed to set the tape recording time or to obtain special effects on the reproduced picture. In order to have such a function, it is necessary to control the tape feeding speed, so the capstan servo device is designed to maintain a stable speed when changing the rotational speed of the capstan motor. Has been a husband.

FIG. 2 shows a conventional capstan servo device.

The rotation of the capstan motor 11 is detected by a frequency detector (not shown), and its speed signal (PC) is supplied to the terminal 12. Terminal 12 is (1/3) frequency divider 1
3, it is connected to a (1x) frequency divider 14 and a (1/3x) frequency divider 15. The output of each frequency divider 13, 14.15 is
Each input terminal al, b1 . c1, and this switch 16 can select any one terminal and connect it to the J, 'J wave number discriminator 17. The output terminal of the frequency discriminator 17 is connected to a low-pass filter 18 , and the output terminal of the low-pass filter 18 is connected to a synthesis circuit 19 that drives the capstan motor 11 .

A control pulse CTL is reproduced from a tape 21 driven by a capstan motor 11 via a control head 22. This control pulse CT
C is supplied to the input terminal 23. The input terminal 23 is (
1x) frequency divider 24 and (Ix) frequency divider 25. The outputs of the frequency dividers 24 and 25 are supplied to input terminals a2 and b2 of a switch 26, respectively. This switch 26 selects any one terminal and connects the phase comparator 27.
Connect to. This phase comparator 27 detects the phase difference between the output signal from the switch 26 and the reference signal (head switching pulse) from the terminal 28, and sends the phase error signal to the previous synthesizer via a low-pass filter 29. Supplied to circuit 19.

Now, assuming that the VTR's playback mode is standard mode,
Switches 16 and 26 are each (1/3) frequency divider 13
and select 24. At this time, capstan motor 1]
The speed signal (p
c) is designed to be, for example, 1.080 tl z. and frequency discriminator] 7 is 360) Iz
The capstan motor 1 is designed so that the output voltage corresponding to the human input signal is increased by i'%, and the capstan motor 1] maintains the standard speed in this state. At this time, the speed signal obtained from the (l/3 times) frequency divider 13 also becomes 3[1i011z. When there is a change in the rotational speed, the output voltage of the low-pass filter 18 changes accordingly, and the rotational speed of the capstan motor 11 is maintained constant. Further, at this time, the control pulse CTL is 301]z. Therefore, the signals input to the phase comparator 27 are also pulses at 3011z (switch 26 output) and 3011z O, and the voltage output from the low-pass filter 29 does not change.However, if the tape speed fluctuates or When the motor rotation phase changes, the phase of the control pulse CTL changes, so
An error output corresponding to this is obtained, and the rotational phase of the capstan motor 11 is controlled in order to correct the tape fluctuation or motor rotation phase.

Next, when the triple speed reproduction mode is set, the capstan motor 11 rotates at three times the standard speed, and the tape feed also becomes three times the standard speed.

Therefore, in this case, the speed signal (PC) is 3X108
0-3240H2,: 7 tons/l/Ha/L/S(
CTL) will be 3X30-90Hz. To this end, switches 16 and 26 are connected to the (173k) divider 1, respectively.
5 and (1/k) frequency divider 25 (k-3).

As a result, the output of switch 16 is 3BO, which is the same as the standard time.
IIZ is output, and switch 26 is also 3011, which is the same as standard time.
Output z.

Note that the frequency divider 14 is employed when the tape speed is reduced to ⅓ for reproduction.

Further, the above servo circuit is provided with a switch 30. This switch 30 is for providing a direct current (DC) offset to the phase control voltage within a controllable range. If the speed is to be further shifted, the illustrated point A can be turned off, the switch 30 can be turned on, and the adjustment can be performed using a DC offset. The reason why point A is turned off is that the phase control system has a narrower control range, and if this system operates, the speed cannot be shifted sufficiently.

(Problems to be Solved by the Invention) According to the conventional capstan servo device described in -, the speed signal (FC) is multiplied or divided by (1/k) times, k times (k is an integer), etc. Although it is possible to obtain phase and speed control by rotating (+w/n) times the speed (
It is not possible to divide the frequency by a count (m and n are integers), and the types of speed and phase control are limited. In order to compensate for this, it is configured to be able to apply a DC offset, but the method using the DC offset has a problem in that the control range (dynamic range) is biased.

Therefore, this invention allows variable speed playback of (+*/n) times to 1
It is an object of the present invention to provide a servo device for a capstan motor in which the phase control system effectively works and stabilizes the phase even in such a control state.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a frequency detection means for detecting the rotational frequency of a capstan motor, and frequency discrimination of the frequency of an output signal from the frequency detection means to reduce the error. a speed control signal output means for outputting a speed control signal through a bandpass filter; a reproduction means for reproducing a reference control pulse recorded on a medium driven by the capstan motor; A capstan servo device comprising a phase error signal output means for deriving a phase difference with a reference pulse via a low-pass filter, wherein an output terminal of the frequency detection means and an input terminal of the speed control signal output means are connected. and between the output terminal of the reproduction means and the input terminal of the phase error signal output means, and the frequency conversion means frequency-divides the input signal (1/■).
a frequency divider; a phase-locked loop to which the output of the frequency divider is supplied; a (1/n) frequency divider provided within the phase-locked loop and capable of controlling the synchronization frequency; The frequency divider includes a frequency divider and means for varying the frequency division ratio of the (1/n) frequency divider.

(Function) By varying the division ratios of the (1/m) frequency divider and the (1/n) frequency divider using two means, the speed signal (PG) from the frequency detection means is /n times the frequency, making the capstan motor ts/n
It is possible to double the pulse rate and also to lock the phase to the reference pulse. This makes it possible to perform variable speed driving at Il/n times the speed and to stabilize the phase control range over a relatively wide range.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In Figure 1,
The same parts as those in the conventional circuit will be described with the same reference numerals as in FIG. 2. Rotation speed signal of capstan motor 11 (
PG) is supplied to the input terminal 12, and a control pulse (CTL) reproduced from the tape rotationally driven by the capstan motor 11 is supplied to the input terminal 23. The input terminal 12 is connected to a (1/kl) frequency divider 46 and also to a (1/II) frequency divider 41. (1/kl) frequency divider 46 is frequency divider 1 shown in FIG.
3,14°15 are shown together. The output of the (1/m) frequency divider 41 is supplied to one of the phase comparators 42, and the output of the (1/n) frequency divider 45 is supplied to the other of the phase comparators 42. The output of the phase comparator 42 is supplied to a control terminal of a voltage controlled oscillator 44 via a low pass filter 43. The output of this voltage controlled oscillator 44 is (1
/n) is supplied to the frequency divider and guided to one input terminal 47B of the switch 47. The output of the frequency divider 46 is led to the other input terminal 47A of this switch 47. The output selected by the switch 47 is then input to the frequency discriminator 17.

This servo device includes a frequency divider 41, a phase comparator 42, a low-pass filter 43 . The present invention is characterized in that it is provided with a frequency conversion means using a phase locked loop constituted by a voltage controlled oscillator 44° frequency divider 45.

Similarly, in the phase control system, the input terminal 23 is (+,
/k2) frequency divider 56 and (1/s) frequency divider 51. (17 to 2) The frequency divider 51 collectively shows the frequency dividers 24 and 25 shown in FIG. (1/
a) The output of the frequency divider 51 is supplied to one of the phase comparators 52, and the output of the (1/n) frequency divider 55 is supplied to the other of the phase comparators 52. The output of the phase comparator 52 is supplied to a control terminal of a voltage controlled oscillator 54 via a low pass filter 53. The output of this voltage controlled oscillator 54 is supplied to a (1/n) frequency divider 55 and guided to one input terminal T57B of the switch 57. The other input terminal 57A of this switch 57 is connected to the frequency divider 56
The output of is derived. The output selected by the switch 57 is input to the phase comparator 'r,27.

Switch 47 selects input terminal 47A, and switch 57 selects input terminal 47A.
When the input terminal 57A is selected, the same operation as the conventional one can be obtained. In other words, the speed signal (r'G)
It is possible to obtain speed control of an integer multiple of .

Next, when the switch 47 selects the input terminal 47B and the switch 57 selects the input terminal 57B, it is possible to obtain speed control that is (a+/n) times the speed signal (PG).

That is, if the speed signal (PG) has a frequency (rl), the speed signal (PG) is divided by the frequency divider 41 (rl) by (1, /ff1).
1/ff1). On the other hand, if the output frequency of the voltage controlled oscillator 44 is (f'), the frequency divider 45 provides (r/n
) and is input to the phase comparator 42. Phase comparator 4
2 obtains an output proportional to the phase difference between (rt/m) and (r/n), and outputs it to a voltage controlled oscillator 44 via a low-pass filter 43.
Supplied to the control terminal of

Therefore, in a synchronous loop, (fl/II)-(r/n)
That is, the relationship rl=C+++/n)1' holds true.

Now, if the capstan motor 11 is made twice as fast (m/n), the speed signal (pc) becomes the frequency (m/n) f',
The frequency is divided into (1/n)f' by a frequency divider 41. On the other hand, the output of the voltage controlled oscillator 44 is (1/n)
The frequency is divided into f' and supplied to the comparator 42. Thus, the loop maintains the frequency stable and the speed signal (pc
), the oscillation frequency of the voltage controlled oscillator 44 changes to follow this variation, and operates to maintain the frequency of the speed signal (FC) constant.

Also, in principle, the phase control system can provide the same operation as the two-legged speed system.

That is, in the case of (m/n) variable speed playback, the control pulse (CTL) frequency is 1'2, (m/n) I'2
becomes.

Then, when inputting to the phase comparator 52, (1/n)1
2, which is compared with the output rO(1/n>) of the frequency divider 55 (fO is the frequency of the voltage controlled oscillator 54).According to the result of this phase comparison, the oscillation output is controlled, and the loop becomes (
IIlIn) operates so that f2 is maintained constant.

[Effects of the Invention] As explained above, the present invention enables variable speed reproduction of (m/n) times the speed of the capstan motor, and also enables the phase control system to work in a q-effect even in such a control state. Phase stabilization can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional capstan servo device. 11... Capstan motor, 17... Frequency discriminator, 18... Low pass filter, 41.51... (1/
l11) Frequency divider, 43.53... Phase comparator, 43.
53...Low pass filter, 44, 55-(1/n)
Frequency divider, 46°56... Frequency divider, 47.57... Switch. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] Frequency detection means for detecting the rotational frequency of the capstan motor, and speed control signal output means for frequency-discriminating the frequency of the output signal from the frequency detection means and deriving the error through a low-pass filter. a reproducing means for reproducing a reference control pulse recorded on a medium driven by the capstan motor; and a low-pass filter to detect the phase difference between the control pulse obtained from the reproducing means and a constant reference pulse. In the capstan servo device, the capstan servo device is provided with a phase error signal output means for deriving a phase error signal through Frequency conversion means each provided between an input terminal of the error signal output means, a (1/m) frequency divider, an output of this frequency divider, and an output of the (1/n) frequency divider. a phase comparator that performs a phase comparison, and the output of this phase comparator is supplied to a frequency control terminal via a low-pass filter, and the output is supplied to the speed control signal output means and the (1/n) frequency divider. A servo device for a capstan motor, comprising: a voltage controlled oscillator for supplying the voltage; and means for varying the frequency division ratio of the (1/m) frequency divider and the (1/n) frequency divider.