JPH02173859A - Multi-cpu system - Google Patents

Abstract

PURPOSE:To improve the interchangeability of software by outputting a stop release signal when the transfer of data is through between one of two peripheral devices and a data transfer means via an input/output means. CONSTITUTION:An input/output instruction detecting circuit 17 outputs the stop request signals 18 to an input/output means 19 and a stop circuit 21. Thus the circuit 21 outputs a stop signal 22 of a 2nd CPU 2. The CPU 2 receives the signal 22 and stops in an executing state of an input/output instruction cycle. At the same time, the means 19 inputted the signal 18 checks a peripheral device address transmission circuit 16 and a data transfer circuit 15. Then the means 19 outputs the data on the circuit 15 to the peripheral device pointed by the circuit 16 via a 1st peripheral device control circuit 5 in the case the CPU 2 performs the output operation to its peripheral devices. Thus the operation is attained with the CPU of one of two systems with no correction and without deteriorating the working reliability of software.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a computer system that processes characters and data, and more particularly to a multi-CPU system having a plurality of CPUs.

Conventional technology Currently, due to rapid advances in semiconductor technology, 32-bit central processing units (hereinafter referred to as CPUs), so-called microprocessors, have been put into practical use, and the circuit scale has reached the scale of hundreds of thousands of transistors. I'm reading.

Furthermore, with regard to software, operating systems (OS), high-level languages, and application software have become more diverse and large-scale.

As a result, it has taken a long time to develop and test software, and even if a new CPU is developed, it has become difficult to immediately provide software that takes advantage of its high performance, and semiconductor technology has We are now in a situation where it is difficult to take advantage of advances made at the level of computer systems.

Conventionally, it has been considered to use high-level languages so that computers that execute any object code can use common software to execute.

In addition, operating systems (OS) have been developed in order to standardize the software environment to be executed in computer systems no matter what kind of peripheral equipment they have.

However, as the marketability of software increases and it comes to be distributed on the market on its own, performance competition among software requires that the performance of the hardware being implemented be maximized without using high-level languages or O8, which have large overheads. Because it was designed to be used, it cannot be ported to other computer systems without extensive modifications.

On the CPU side, the progress from 8 bits to 16 bits to 32 bits has made software development easier.
Consideration is being given to maintaining compatibility at the object code level and maintaining software compatibility so that past software assets can be used.

However, it is not possible to test whether the software running on a certain system will run seamlessly on hardware using a higher-performance CPU until after the new CPU is completed. .

As CPU performance increases and processing time becomes shorter, software may not work unless appropriate consideration is taken.

For this reason, in addition to the type of CPU, software compatibility has come to be affected by the type, speed, performance, peripheral devices, and O8 type of the CPU for which the software was developed.

Due to the above situation, software has become increasingly dependent on computer systems, and even if new high-performance CPUs are developed, it has become necessary to maintain the traditional CPU and traditional system configuration, resulting in two types of software in one system. Equipped with a CPU of
The new software required an environment to run on the new CPU.

In addition, in order to run both the software developed for CPU A and the software developed for CPU B, two different CPUs A and B are used.
The need for systems equipped with this has also increased.

Due to the progress of semiconductor technology, C as a component
This is because although the cost of the PU is relatively low in the system, the software has become expensive.

Therefore, in order to maintain software compatibility, it has become necessary to have a CPU compatible with each software and a system with compatible hardware including peripheral devices.

FIG. 2 shows a block diagram of a conventional multi-CPU system.

In this figure, one CPU reads and writes instructions and data from one storage circuit (ROM, RAM) 3 connected via a system bus 12 to execute a program, and also connects one peripheral device control circuit 5 to a floppy disk. Input and output can be performed from one of the peripheral devices such as the device 7, the hard disk device 8, the printer device 9, and the keyboard device 11.

A third CPU 23 is also connected to the system bus 12 so that one CPU
Similarly to I, one of the memory circuits 3 and one of the peripheral devices can be accessed. The system bus 12 includes an address bus for specifying the address of one of the memory circuits 3 and one of the peripheral devices, a data bus for exchanging data, control signals for instructing reading and writing, and a C from the peripheral device.
It consists of an interrupt request signal that conveys an interrupt to the PU, a bus use request signal for using the system bus, a bus use permission signal, etc., and one CPU 23 and the third CPU 23 each receive the system bus 12 as necessary. Run the program using However, these two CP
Since U cannot use the system bus 12 at the same time, they will operate alternately, which may result in insufficient processing performance depending on the application. For example, when connected to a communication channel or local network, real-time processing is required to ensure that received data is not lost. However, if the system bus 12 is continuously in use, the processing CPU There are cases where this is not possible.

If parallel processing is required in this way, system bus 1
2 and a local bus 13 independent from the other CPU 2.
, the other memory circuit 4. The other peripheral device control circuit 6 is connected to create a local system 14. Normally, the local system 14 is created independent of the system bus 12, and programs are executed within the local bus 13 and input/output to peripheral devices is performed. I do.

The other CPU 2 accesses one of the storage circuits 3 and one of the peripheral device control circuits 5 on the system bus 12, and conversely, one CPU or the third CPU 23 accesses the local system 14. in case of,
System bus 12 by bus interface circuit 24
While checking the usage status of the local bus 13, the user obtains the right to use the local bus 13, and connects the buses so that access can be made from each bus. By adopting such a configuration, various CPUs can independently execute programs.

Problems to be Solved by the Invention In the conventional multi-CPU system as explained above, one CPU uses addresses, etc. to enable high-speed access to memory circuits and peripheral devices distributed within the system. Many are configured in the form of a data bus. This is because the memory access time of the CPU greatly affects the program processing time. For this reason, for example, 1nte1's MULTIBUSTI and Texas
The NuBus from sInstruments was developed as a high-performance bus for 32-bit systems, but the connector has a large number of signal lines, 96, and has a large physical drawback.

For this reason, they cannot be easily attached to or removed from the device, and moreover, they are expensive.

Also, CPUs with different bus widths (e.g. 8 bits and 1 bits)
When a system is configured with a 6-bit CPU or a 32-bit CPU, the following problems arise.

LSIs that control communication interfaces for peripheral devices such as floppy disks, hard disks, printers, and R5-232Cs often interface with the CPU in byte units (8 bits). Therefore, when connected to a system bus with a 16-bit data bus, the data bus is divided into the upper 8 bits (MSB) and the lower 8 bits (LSB), so the I10 address seen from the CPU is an even address. In order to execute software assigned to consecutive I10 addresses as is in an 8-bit system, it is necessary to use hardware that converts the 110 addresses, or the lower 8 bits of the data bus, or the upper 8 bits of the data bus. A multiplexer for switching 8 bits is required.

For this reason, in a CPU system with different bus widths, the address setting of the I10 devices of both CPUs is restricted, and hardware such as a multiplexer for bus switching is required.

For this reason, with advances in CPUs, even if CPUs with higher performance and compatibility at the conventional object code level are put into practical use, the bus width will be reduced to 8 bits, 16 bits, or
In cases where the software is different, such as 32 bits, even if you try to standardize the hardware and achieve conventional software compatibility, the engineering /
○Additional hardware is required for device addressing, which has the disadvantage of being expensive.

That is, current multiprocessor systems have the disadvantage that it is difficult to obtain a system that is small, inexpensive, easy to handle, easy to attach and remove devices, and has high software compatibility.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-CPU system that is inexpensive, easy to handle, and highly compatible with software regardless of the type of CPU.

Means for Solving the Problems The multi-CPU system of the present invention solves the above problems, and includes a CPU that executes instructions and processes data;
A multi-CPU system consisting of at least two sets, one set consisting of a memory circuit that stores instructions and data, and a peripheral device consisting of an external storage device or a plurality of input/output devices, and the other set. In, the CP of the other set
detects an input or output command to a peripheral device of the other set of CPUs, and issues a stop request if the peripheral device corresponding to this input or output command cannot access the other set of peripheral devices. an input/output command detection means that generates a signal; a stop means that generates a stop signal in response to the stop request signal outputted from the input/output command detection means and stops the CPU of the other set; C
peripheral device address transmitting means connected to the PU and outputting address data of a peripheral device to which the CPU of the other set requests access; and peripheral device address transmitting means activated by the stop request signal and specified by the peripheral device address transmitting means. input/output means for selecting a device from the one set of peripheral devices and executing an input or output command to the selected one set of peripheral devices in accordance with an input or output command of the CPU of the other set; and the input/output means is connected to the other set of CPUs, and the input or output command to the other set of CPUs detected by the input/output command detection means is transmitted from the input/output means as an input command. When notified, the data input from the one peripheral device is transferred to the CPU of the other set, and when notified as an output command from the input/output means, the data is output from the CPU of the other set. and a data transfer means for transferring the data transferred to the one set of peripheral devices, and the input/output means includes a stop means when the data transfer between the one peripheral device and the data transfer means is completed. It was configured to output a stop release signal to the

Further, in the multi-CPU system of the present invention, data to be output by an output command of the other set of CPUs detected by the input/output command detection means is output to a plurality of peripheral devices of one set of peripheral devices. In this case, the input/output means can be configured to convert into a plurality of output data and output it to a plurality of corresponding peripheral devices.

Further, in the multi-CPU system of the present invention, data to be inputted by an input command of the other set of CPUs detected by the input/output command detection means is input from a plurality of peripheral devices of one set of peripheral devices. , the input/output means receives data input from each of the plurality of corresponding peripheral devices,
It is also possible to configure the system to convert data into a format required by the other set of CPUs.

In addition, in the multi-CPU system of the present invention, when the data output by the other set of CPUs is divided into the - set of peripheral devices and the other set of peripheral devices, It is also possible to select only the data to be output and convert it into the data format of one set of peripheral devices.

Further, in the multi-CPU system of the present invention, when data inputted by the other set of CPUs is divided into data input from the one set of peripheral devices and from the other set of peripheral devices, the other set of peripheral devices It is also possible to convert data input from the other set of CPUs into a data format required by the other set of CPUs, and to output only data input from the other set of peripheral devices to the other set of CPUs.

That is, the multi-CPU system according to the present invention connects memory circuits such as RAM and ROM necessary for each system's CPU to each CPU's bus, and
The configuration is such that the memory circuit of the PU is not accessed to the memory circuits of other CPUs.

When a CPU on the other system side needs to perform input/output to a peripheral device on one system side, it is possible to determine whether the instructions of the CPU on the other system side are input/output instructions. The execution of this instruction is detected by a monitoring input/output instruction detection circuit, and the other CPU is paused, and the input/output means provided on the other system side performs input/output for the peripheral device on the one system side. After performing the output, the other CPU is released from hibernation.

As a result, the multi-CPU system of the present invention is characterized in that the data that passes through the connection between the systems is only the data that is exchanged with the peripheral device in an input/output cycle.

Effects According to the above configuration, when the other CPU executes an input/output instruction, it behaves as if all peripheral devices exist on the bus of the CPU on the other system side. Even if a peripheral device is not directly connected to the bus, programs can be executed in the same way as in a system that has a peripheral device on the other CPU side.

In addition, by not allowing memory cycles that require a high-speed response to pass through the connection between two systems, and by interfacing only with input/output signals (input/output cycles) that are slower than memory cycles, it is possible to There is no need for peripheral devices or peripheral device control circuits on the side, and it is also possible to reduce the number of signal lines required for connections between systems, while hardly reducing the processing power of each CPU. Therefore, software compatibility can be improved, and the interface section can be physically smaller and cheaper.

In a conventional multi-CPU system, the entire system operates in synchronization using the system bus 12, so if the operating clock of each CPU does not satisfy the synchronization relationship at a certain integer multiple, the synchronization will fail. This also solves the problem that the operating clock of each CPU was sometimes subject to design restrictions due to the increase in bus access time.

Furthermore, according to the present invention, since the coupling part between the systems only needs to interface with the address, data, and status of the other CPU as a mere input/output port, it is not affected by the operating clocks of the two systems, so that a certain software can be implemented easily. Since the operating clock of the CPU on the other system side can be kept independent of the clock of the CPU on the other system side, there is an advantage that the operating environment of the software can be maintained regardless of speeding up due to advances in hardware.

In addition, regarding hardware differences in the I10 address and bus width of peripheral devices on one system side, the input/output means is interposed between the two CPUs and converts data, so that the input/output of the peripheral devices can be adjusted. data format, speed,
Differences in protocols, etc. can be absorbed.

In addition, even if the other system has a special hardware configuration that has multiple peripheral devices at one I10 address and performs input/output to each device at the same time, the input/output means converts the data format and input/output. This eliminates the need for peripheral devices on one system side to have the same configuration and can be made into standard hardware, making it possible to simplify the circuitry.

If the other CPU does not need to be used together with one CPU, the other system's (
By combining the PU, ROM or RAM containing software, input/output means, and bus interface circuit on one card, it can be installed in one system's equipment when necessary, and can be used as if it were one piece of software. It can be operated by the side device.

In this way, according to the present invention, the hardware environment in which the other system and its software were developed can be realized as is by simply adding an input/output means, so one can be implemented without modification without compromising the operational reliability of the software. It can be operated by the system's CPU.

Embodiment FIG. 1 is a block diagram showing the configuration of a multi-CPU system according to an embodiment of the present invention.

In the figure, 1 is one CPU (hereinafter referred to as the first CPU), 2 is the other CPU (hereinafter referred to as the second CPU)
, 3 is one memory circuit (ROM, RAM) (hereinafter referred to as the first C memory circuit), and 4 is the other memory circuit (ROM, RAM).
RAM) (hereinafter referred to as the second memory circuit), 5 is one peripheral device control circuit (hereinafter referred to as the first peripheral device control circuit), and 6 is the other peripheral device control circuit (hereinafter referred to as the second peripheral device control circuit). (referred to as a circuit), 7 is a floppy disk device,
8 is a hard disk device, 9 is a printer device, 10 is a communication interface, 11 is a keyboard device, 12 is a system bus, 13 is a local bus, 14 is a local system, 15 is a data transfer circuit 16 is a peripheral device address transmission circuit, 17 is a An input/output command detection circuit, 18 a stop request signal, 19 an input/output means, 20 a stop release signal, 21 a stop circuit, and 22 a stop signal.

The first CPUI is connected to the first storage circuit 3 and the first peripheral device control circuit 5 by the system bus 12,
In addition to executing programs, input/output can be performed to the first peripheral devices, that is, the floppy disk device 7, the hard disk device 8, the printer device 9, and the communication interface 10.

On the other hand, the second CPU 2 is connected to the second memory circuit 4 and the second
It is connected to the peripheral device control circuit 6 by a local bus 13 and can execute and process instructions stored in the second memory circuit 4 and input data from the keyboard device 11 .

This second CPU is connected to a floppy disk device 7, a hard disk device 8, a printer device 9, and a communication interface 1, which are peripheral devices that do not exist in the local system 14.
When an input/output instruction is executed to perform input/output to 0, the operation is as follows.

First, the input/output command detection circuit 17 outputs a stop request signal 18 to the input/output means 19 and the stop circuit 21. As a result, the stop circuit 21 outputs a stop signal 22 to the second CPU 2. Upon receiving this, the second CPU 2 stops while executing the input/output instruction cycle.

The input/output means 19 which received the stop request signal 18 at the same time,
The peripheral device address transmission circuit 16 and the data transfer circuit 15 are checked, and when the second CPU 2 performs output to the peripheral device, the data of the data transfer circuit 15 is transmitted to the peripheral device indicated by the peripheral device address transmission circuit 16. is outputted through the first peripheral device control circuit 5.

Further, when the second CPU 2 receives input from a peripheral device, the input/output means 19 similarly controls the first peripheral device control circuit 5.
The input data is set in the data transfer circuit 15 through the data transfer circuit 15.

The input/output means 19 that has completed the input or output work in this manner outputs a stop release signal 20 to the stop circuit 21. Upon receiving this, the stop circuit 21 releases the stop signal 22 and releases the second CPU 2 from the stopped state. In this way, if it is an output command cycle, the second CPU 2 ends the command cycle, and if it is an input command cycle, it reads the data from the data transfer circuit 15 through the local bus 13 and ends the input command cycle. Therefore, even if the input/output device does not exist on the local system 14 side, data input/output can be executed from the first peripheral device control circuit side.

In addition, in the case of a special hardware configuration in which the second CPU 2 has multiple peripheral devices at one address for input/output and input/output to each device is performed at the same time, or The first I10 address
When the input/output means is divided into two peripheral devices: a second peripheral device on the local system 14 side and a second peripheral device on the local system 14 side, the
○By converting the address to the required data format and converting the protocol, the local system 1
By absorbing the details of the hardware of the fourth peripheral device and the hardware of the first peripheral device, the second C
Programs can be executed from the PU 2 as if all peripheral devices were on the local bus 14.

Further, since many peripheral devices involve mechanical operations, it often takes two orders of magnitude or more time compared to the operation of electronic memory circuits, so the input/output means 19 is
The processing time required to perform operations such as 0 address conversion and protocol conversion is also not a problem. And input/output means 19
To realize this, it can be implemented by hardware using logic circuits, depending on the operating time of peripheral devices and the overhead allowed by the software executed by the second CPU 2, or by the first CPU using software means, or by using both. The choice between the two methods should be made from the standpoint of performance and cost.

In addition, the number of signal lines at the coupling portion between the system 12, the data transfer circuit 15, the peripheral device address transmission circuit 16, and the input/output means 19 can be freely selected from the above-mentioned performance and cost viewpoints.

Effects of the Invention The purpose of the present invention is to input and output data by using peripheral devices and their interface circuits as much as possible on the host system without modifying the software running on the local system. Therefore, when the local system CPU executes an input/output instruction,
It is necessary to determine whether the peripheral device "exists" or not on the local system side.

Furthermore, if it does not exist, it is necessary to determine whether the peripheral device is an input or an output depending on what kind of peripheral device it is.

Also, when inputting and outputting data from a peripheral device on the host system, there is additional time to convert and transfer the data, so it takes more time than if the peripheral device is on the local system. , it is assumed that the CPU of the local system is temporarily stopped.

Next, if it is an output, the data to be output is read from the data transfer circuit (here, just a port). If data needs to be converted from there, the data format is converted.

For this reason, determining whether the local system has a peripheral device requested by the local system's CPU is as follows:
The input/output instruction detection circuit performs this. This is to determine which peripheral device to input/output to on the host system side when it is necessary to use a peripheral device on the host system side that is not on the local system side. , the input/output means has that function, reads the peripheral device address transmission circuit (here considered as just a port), checks what peripheral device the local system wants to input or output, and then if it is an output. The data to be output is read from the data transfer circuit (also just a port). Then, if data conversion is necessary, the data format is converted.

The data is then output to the target peripheral device. In the case of input, data is input from the target peripheral device.

Next, if format conversion is necessary, perform that conversion. Then, the data is written to the data transfer circuit.

Finally, when the work is completed, stop the CPU on the local system side.

From the perspective of the local system CPU, in the case of an output cycle, the cycle ends, and in the case of an input cycle, data is read from the data transfer means, and the input data is read into the local CPU. (However, from the local CPU's point of view, the data transfer circuit is not a special process, but outputs data to the data bus in the input cycle, and operates as a simple input cycle.) From the above, input/output The means may be a program running on the CPU of the host system, or may be constructed entirely of logic circuits.

In addition, if the operating speed of the host system is sufficiently faster than that of the local system, the input/output command detection means can also be detected by the host system's CPU using software, and the conversion time and data transfer time can be ignored. If it runs fast enough, the local system's CP
There is no need to stop U.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a multi-CPU system according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional multi-CPU system, and FIG. 3 is a block diagram showing the configuration of a local system according to an embodiment of the present invention. It is a perspective view showing a mounting state. 1: First (one) CPU, 2: Second (other) CPU, 3: First (one) memory circuit, 4: Second (other) memory circuit, 5: Second (other) memory circuit. 1 (one) peripheral device control circuit, 6...2nd (
7.. Floppy disk device, 8.. Hard disk device, 9.. Printer device, 1o.. Communication interface, 11.. Keyboard device, 12.. System bus, 13.. Local bus. , 14・
- Local system, 15... Data transfer circuit, 16... Peripheral device address transfer circuit, 17... Input/output command detection circuit, 18... Stop request signal, 19... Input/output means, 20...
Stop release signal, 21...stop circuit, 22, stop signal, 2
3...Third CPU, 24...Bus interface circuit, 25...Bus connection terminal, 26...Upper case, 27...Capacitor.

Claims (6)

[Claims] (1) One set includes a CPU that executes instructions and processes data, a memory circuit that stores instructions and data, and a peripheral device that includes an external storage device or multiple input/output devices, and the other. in a multi-CPU system consisting of at least two sets, one set of CPUs connected to the other set of CPUs;
input/output command detection means for detecting an input or output command to a peripheral device of U and generating a stop request signal when the peripheral device corresponding to the input or output command cannot access the other set of peripheral devices; , a stop means for generating a stop signal in response to the stop request signal outputted from the input/output command detection means and stopping the CPU of the other set; and a stop means connected to the CPU of the other set, C.P.
peripheral device address transmission means for outputting address data of a peripheral device that U requests access to; input/output means for executing input or output commands to the selected one set of peripheral devices in accordance with the input or output commands of the other set of CPUs; When an input or output command to the CPU of the other set connected to the CPU of the other set and detected by the input/output command detection means is notified as an input command by the input/output means,
When data input from the one peripheral device is transferred to the other set of CPUs and notified as an output command by the input/output means, the data output from the other set of CPUs is transferred to the other set of CPUs. and data transfer means for transferring data to a set of peripheral devices, and the input/output means sends a stop release signal to the stop means when data transfer between the one peripheral device and the data transfer means is completed. A multi-CPU system characterized by output. (2) When data to be output by an output command of the other set of CPUs detected by the input/output command detection means is output to a plurality of peripheral devices of one set of peripheral devices, the input/output 2. The multi-CPU system according to claim 1, wherein the means converts the data into a plurality of output data and outputs the data to each of the plurality of corresponding peripheral devices. (3) When data to be input by an input command of the other set of CPUs detected by the input/output command detection means is input from a plurality of peripheral devices of one set of peripheral devices, the input/output means Claim (1) characterized in that the data input from each of the plurality of corresponding peripheral devices is converted into a format required by the other set of CPUs and provided.
The multi-CPU system described in . (4) When the data output by the other set of CPUs is divided into the one set of peripheral devices and the other set of peripheral devices, selecting only the data to be output to the one set of peripheral devices, A multi-CPU system characterized by comprising input/output means according to claims (1) and (2) for converting data into a data format of one set of peripheral devices. (5) When data input by the other set of CPUs is divided into data input from the one set of peripheral devices and from the other set of peripheral devices, the data input from the other set of peripheral devices is Claims (1) and (2) above, wherein the data format is converted into a data format required by the other set of CPUs, and only the data input from the other set of peripheral devices is output to the other CPU. A multi-CPU system comprising the input/output means described in . (6) In a multi-CPU system formed by at least one pair of systems and the other, memory circuits such as RAM and ROM required for the CPU of each system are connected to the bus of each CPU, and the memory of each CPU is connected to the bus of each CPU. When the circuit is configured so that the memory circuits of other CPUs are not accessed, and the CPU on the other system side needs to perform input/output to the peripheral device on the one system side,
The execution of this instruction is detected by an input/output instruction detection circuit provided on the other system side, which monitors whether the instruction of the CPU is an input/output instruction. After the input/output means provided on the system side performs input/output to the peripheral device on one system side, the CPU of the other side is released from the hibernation state, thereby passing through the connection between the systems. A multi-CPU system characterized in that data is limited to data exchanged with the above-mentioned peripheral devices in input/output cycles.