JPH02172294A - Solder bonding method for electronic parts - Google Patents
Solder bonding method for electronic partsInfo
- Publication number
- JPH02172294A JPH02172294A JP32649888A JP32649888A JPH02172294A JP H02172294 A JPH02172294 A JP H02172294A JP 32649888 A JP32649888 A JP 32649888A JP 32649888 A JP32649888 A JP 32649888A JP H02172294 A JPH02172294 A JP H02172294A
- Authority
- JP
- Japan
- Prior art keywords
- cream solder
- solder
- land
- printed
- dispersed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 7
- 239000006071 cream Substances 0.000 claims abstract description 39
- 238000005476 soldering Methods 0.000 claims abstract description 15
- 238000005304 joining Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 241000272168 Laridae Species 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子部品の本体部より導出する複数の端子リ
ードを表面実装によりプリント配線板に形成されたラン
ドにはんだ付けするはんだ付け接合方法に係わるもので
ある。[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a soldering joining method in which a plurality of terminal leads led out from the main body of an electronic component are soldered to lands formed on a printed wiring board by surface mounting. This is related to.
従来、本体部の端面から等間隔に導出された複数の接v
tS子を有する電子部品例えば集積回路等のフラットパ
ッケージ形電子部品1を、プリント配線板2に表面実装
し、リフローはんだ付けにより接合する場合、端子リー
ド6の巾と各端子リード間のピッチに合わせ、プリント
配線板上にランド3を形成し、ランド3に対応する開口
8を有する印刷用マスク7によりクリームはんだ4をラ
ンド3に印刷し、リフローはんだ付けにより接合する方
法がとられている。Conventionally, a plurality of tangents v derived at equal intervals from the end face of the main body
When a flat package type electronic component 1 such as an integrated circuit is surface mounted on a printed wiring board 2 and joined by reflow soldering, the width of the terminal lead 6 and the pitch between each terminal lead are adjusted. A method is used in which lands 3 are formed on a printed wiring board, cream solder 4 is printed on the lands 3 using a printing mask 7 having openings 8 corresponding to the lands 3, and the lands 3 are joined by reflow soldering.
この場合、ランド3の巾は、端子リード6の巾より充分
大きく取り、同ランド3の巾よりやや小さい開口8を有
するはんだ印刷用マスク7により、クリームはんだ4を
印刷するのが通例で、リフローはんだ付けにより溶融さ
れたクリームはんだ4は1、表面張力によりランド3と
端子リード6の間を伝わり均一にはんだ付けされ、過剰
なりリームはんだ4はランド3に拡がりフィレットを形
成して、はんだ付け信幀性が保証されていた。In this case, the width of the land 3 is made sufficiently larger than the width of the terminal lead 6, and the cream solder 4 is usually printed using a solder printing mask 7 having an opening 8 slightly smaller than the width of the land 3. The cream solder 4 melted during soldering 1 is transmitted between the land 3 and the terminal lead 6 due to surface tension and is soldered uniformly. affordability was guaranteed.
近来、集積回路の高集積化が進むにつれて多端子化し、
端子リード中とリード間のピッチが挟まり、クラオード
タイプの電子部品で端子数が100ビンで、端子中が0
.5n+m、端子リード間ピッチが0、65mo+のち
のまで実用化されている。In recent years, as integrated circuits have become more highly integrated, the number of terminals has increased,
The pitch in the terminal lead and the pitch between the leads are pinched, and the number of terminals in a Claude type electronic component is 100 pins, and the pitch in the terminal is 0.
.. 5n+m, the pitch between terminal leads was 0, and it was put into practical use until later, when it was 65mo+.
この場合、ランド3の巾は端子リード6の巾と同程度の
寸法に設定され、第4図および第5図に示すように、隣
接する端子リード間隔が挟まり、溶融されたクリームは
んだ4が押し出され、隣接する端子リード6またはラン
ド3に接触して短絡を生じる事例が多く発生し、この検
査と修正のための作業が生産の障害となっている。In this case, the width of the land 3 is set to be approximately the same as the width of the terminal lead 6, and as shown in FIGS. 4 and 5, the space between adjacent terminal leads is pinched and the molten cream solder 4 is pushed out Therefore, there are many cases where short circuits occur due to contact with adjacent terminal leads 6 or lands 3, and the inspection and correction work becomes an obstacle to production.
本発明は、上記従来の技術の問題点に鑑みなされたもの
で、隣接するランド3間のクリームはんだの洩出による
短絡を解消することができるはんだ接合方法を提供する
ことを目的としている。The present invention has been made in view of the problems of the prior art described above, and it is an object of the present invention to provide a soldering method capable of eliminating short circuits caused by leakage of cream solder between adjacent lands 3.
〔課題を解決するための手段〕
上記目的を達成するために、本発明ではランド3上の接
合面に対応してクリームはんだを分散して印刷し、上記
分散したクリームはんだ印刷面をリフローはんだ付けに
より相互に連結するように配置した。[Means for solving the problem] In order to achieve the above object, in the present invention, cream solder is distributed and printed corresponding to the bonding surface on the land 3, and the distributed cream solder printed surface is reflow soldered. They are arranged so that they are interconnected.
上記構成によれば、ランド3の端子リード6の接合面に
クリームはんだ4を分散して載置し、リフローはんだ付
けを行うことによりクリームはんだ4が流出し、表面張
力によって端子リード6とランド3の間に均一に拡がっ
て連結しはんだ接合を行う。According to the above configuration, the cream solder 4 is dispersed and placed on the joint surface of the terminal lead 6 of the land 3, and by performing reflow soldering, the cream solder 4 flows out and the terminal lead 6 and the land 3 are bonded to each other due to surface tension. The solder joints are made by spreading uniformly between them and connecting them.
以下、本発明の一実施例について添付図面を参照して詳
細に説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.
第1図は、クラオードタイプのフラットパッケージ形の
電子部品1をプリント配線板2に搭載する状況を示して
いる。FIG. 1 shows a situation in which a Claude type flat package electronic component 1 is mounted on a printed wiring board 2. As shown in FIG.
電子部品lは、本体部より複数の端子リード6を導出し
、同端子リード6をガルウィング状に折曲げ、同端子リ
ード6の接合面が面一になるように形成している。In the electronic component 1, a plurality of terminal leads 6 are led out from the main body, and the terminal leads 6 are bent into a gull wing shape so that the bonding surfaces of the terminal leads 6 are flush with each other.
プリント配線板2には、上記複数の端子リード6の接合
面lOに合わせて、複数のランド3を形成し、ランド3
のはんだ接合部を除く外周にはんだレジスト9を印刷し
、同時にクリームはんだ4の印刷用マスク7を位置決め
するガイドマークまたはガイドビン孔(図示せず)を配
設している。A plurality of lands 3 are formed on the printed wiring board 2 in accordance with the bonding surface lO of the plurality of terminal leads 6.
A solder resist 9 is printed on the outer periphery except for the solder joints, and at the same time guide marks or guide bin holes (not shown) for positioning the printing mask 7 of the cream solder 4 are provided.
印刷用マスク7は、上記端子リード6の接合面10に合
わせ、同接合面10に円形または楕円形の開口8を形成
し、プリント配線板2のガイドマークまたはガイドビン
孔により開口8をランド3上およびその近傍に位置合わ
せしている。The printing mask 7 has a circular or elliptical opening 8 formed in the joint surface 10 to match the joint surface 10 of the terminal lead 6, and the opening 8 is connected to the land 3 by a guide mark or a guide bottle hole of the printed wiring board 2. Aligned on and near the top.
印刷用マスク7の上から、クリームはんだ4をスキージ
により開口8を通してランド3上に載置する。Cream solder 4 is placed on land 3 from above printing mask 7 through opening 8 using a squeegee.
印刷用マスク7を取り除き、印刷されたクリームはんだ
4上に、フラットパッケージ形電子部品lを位置合わせ
して搭載し、リフローはんだ付けによりはんだ接合を行
う。The printing mask 7 is removed, the flat package type electronic component 1 is aligned and mounted on the printed cream solder 4, and solder joint is performed by reflow soldering.
この時、分散したクリームはんだ印刷面は、溶融したク
リームはんだ4により相互に連結され、接合面10に均
一に拡がり、安定したはんだ接合を形成する。At this time, the dispersed cream solder printed surfaces are interconnected by the melted cream solder 4 and uniformly spread over the joint surface 10 to form a stable solder joint.
第2図は、本発明の詳細を示す一部省略平面図で、印刷
用マスク6に形成された開口8の配置パターンおよびラ
ンド3上に印刷されたクリームはんだ4の印刷パターン
を示している。FIG. 2 is a partially omitted plan view showing details of the present invention, showing the arrangement pattern of openings 8 formed in the printing mask 6 and the printing pattern of the cream solder 4 printed on the lands 3.
第2図(a)は、プリント配線板2にクリームはんだ4
を印刷した状態で、クリームはんだ4は二個所に分散し
て印刷され、ランド3のはんだ接合部を除く外周をはん
だレジスト9で覆っている。Figure 2 (a) shows cream solder 4 on printed wiring board 2.
In the printed state, the cream solder 4 is distributed and printed in two places, and the outer periphery of the land 3 except for the solder joint part is covered with a solder resist 9.
第2図(b)は、端子リード6をはんだ接合した状態で
、クリームはんだ4は溶融して表面張力により流動し、
余白部5を埋めて上記端子リード6とランド3の間を均
一に接合する。FIG. 2(b) shows a state where the terminal lead 6 is soldered and the cream solder 4 melts and flows due to surface tension.
The margin portion 5 is filled and the terminal lead 6 and the land 3 are uniformly bonded.
第3図は、本発明の他の実施例で、ランド3に対応する
印刷用マスク6の所定の位置に、クリームはんだ4を一
定量通過させる内径の開口8を、適正なりリームはんだ
4の量に合わせて複数個分散して形成し、クリームはん
だ4をランド3のはんだ接合部に均一に形成している。FIG. 3 shows another embodiment of the present invention, in which an opening 8 having an inner diameter through which a certain amount of cream solder 4 passes is formed in a predetermined position of a printing mask 6 corresponding to a land 3, so that an appropriate amount of cream solder 4 can be applied. A plurality of cream solders 4 are uniformly formed on the solder joints of the lands 3.
本発明によれば、端子リード5の中およびランド3の巾
に合わせて、クリームはんだ印刷面に上記開口8を、位
置および数を適切に選んで配置することにより、巾の広
いランド3の場合にも均一なりリームはんだ量を搭載す
ることができる。According to the present invention, when the land 3 has a wide width, the openings 8 are appropriately selected and arranged in the cream solder printed surface in the terminal lead 5 and in accordance with the width of the land 3. It is also possible to load a uniform amount of ream solder.
本発明は、上記のように構成されているので、リフロー
はんだ付けに際し、溶融したクリームはんだ4がクリー
ムはんだ印刷面からランド3上に拡がり、均一なはんだ
層を形成し、従来例のように局部的に溶融したクリーム
はんだ4が洩出し、隣接するランド3または端子リード
6と短絡する事故を防ぐことができた。Since the present invention is configured as described above, during reflow soldering, the molten cream solder 4 spreads from the cream solder printed surface onto the lands 3 to form a uniform solder layer, and is localized unlike the conventional example. It was possible to prevent an accident in which the melted cream solder 4 leaked out and caused a short circuit with the adjacent land 3 or terminal lead 6.
またクリームはんだの印刷の際、印刷用マスク7に円形
または楕円形の開口8を形成することにより、クリーム
はんだの印刷の際、クリームはんだの通過が容易になり
、印刷用マスク7に付着して生じた印刷かすれやずれを
防ぐことができ、また印刷用マスク7の洗浄等の作業が
容易になり、作業性の改善を図ることができた。Furthermore, by forming circular or oval openings 8 in the printing mask 7 when printing cream solder, it becomes easier for the cream solder to pass through and prevent it from adhering to the printing mask 7. It was possible to prevent the printing from fading and shifting, and it was also possible to perform operations such as cleaning the printing mask 7 easily, thereby improving workability.
第1図は、フラットパッケージ形電子部品のプリント配
線板への搭載を説明する一部省略斜視は第2図は印刷用
マスク6の開口8の配置とランド3上に形成されたクリ
ームはんだ4の印刷パターンをしめす部分平面図、第3
図は本発明の他の実施例を示す一部省略斜視図、第4図
および第5図は従来例を示す部分平面図およびA−A断
面図である。
図中、lは電子部品、2はプリント配線板、3はランド
、4はクリームはんだ、5は同余白部、6は端子リード
、7は印刷用マスク、8は開口、9ははんだレジスト、
10は接合面である。
特許出願人 株式会社富士通ゼネラル第2図
第4図
第、5図FIG. 1 shows the mounting of a flat package type electronic component on a printed wiring board, and FIG. Partial plan view showing the printed pattern, 3rd
The figure is a partially omitted perspective view showing another embodiment of the present invention, and FIGS. 4 and 5 are a partial plan view and a sectional view taken along the line A-A of the conventional example. In the figure, l is an electronic component, 2 is a printed wiring board, 3 is a land, 4 is cream solder, 5 is the same margin, 6 is a terminal lead, 7 is a printing mask, 8 is an opening, 9 is a solder resist,
10 is a joint surface. Patent applicant: Fujitsu General Ltd. Figure 2 Figure 4, Figure 5
Claims (1)
応してプリント配線板上に形成された複数のランドにク
リームはんだを印刷し、リフローはんだ付けにより接合
するはんだ付け接合方法において、上記ランド上の接合
面に対応してクリームはんだを分散して印刷し、上記分
散したクリームはんだ印刷面をリフローはんだ付けによ
り相互に連結するように配置した電子部品のはんだ付け
接合方法。In a soldering method in which cream solder is printed on a plurality of lands formed on a printed wiring board corresponding to a plurality of terminal leads leading out from the main body of an electronic component, and the solder is bonded by reflow soldering, A method for soldering and joining electronic components, in which cream solder is distributed and printed in correspondence with the joining surfaces, and the distributed cream solder printed surfaces are arranged so as to be interconnected by reflow soldering.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32649888A JPH02172294A (en) | 1988-12-24 | 1988-12-24 | Solder bonding method for electronic parts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32649888A JPH02172294A (en) | 1988-12-24 | 1988-12-24 | Solder bonding method for electronic parts |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02172294A true JPH02172294A (en) | 1990-07-03 |
Family
ID=18188498
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32649888A Pending JPH02172294A (en) | 1988-12-24 | 1988-12-24 | Solder bonding method for electronic parts |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02172294A (en) |
-
1988
- 1988-12-24 JP JP32649888A patent/JPH02172294A/en active Pending
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