JPH02172293A - Solder bonding method for electronic parts - Google Patents
Solder bonding method for electronic partsInfo
- Publication number
- JPH02172293A JPH02172293A JP63326497A JP32649788A JPH02172293A JP H02172293 A JPH02172293 A JP H02172293A JP 63326497 A JP63326497 A JP 63326497A JP 32649788 A JP32649788 A JP 32649788A JP H02172293 A JPH02172293 A JP H02172293A
- Authority
- JP
- Japan
- Prior art keywords
- cream solder
- solder
- land
- printed
- margin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3465—Application of solder
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子部品の本体部より導出する複数の端子リ
ードを表面実装によりプリント配線板に形成されたラン
ドにはんだ付けするはんだ付け接合方法に係わるもので
ある。[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a soldering joining method in which a plurality of terminal leads led out from the main body of an electronic component are soldered to lands formed on a printed wiring board by surface mounting. It is related to.
従来、本体部の端面から等間隔に導出された複数の接続
端子を有する電子部品例えば集積回路等のフラットパッ
ケージ形電子部品1を、プリント配線板2に表面実装し
、リフローはんだ付けにより接合する場合、端子リード
6の巾と各端子リード間のピッチに合わせ、プリント配
線板上にランド3を形成し、ランド3に対応する開口8
を存する印刷用マスク7によりクリームはんだ4をラン
ド3に印刷し、リフローはんだ付けにより接合する方法
がとられている。Conventionally, a flat package type electronic component 1 such as an integrated circuit, which has a plurality of connection terminals led out from an end surface of a main body at equal intervals, is surface mounted on a printed wiring board 2 and joined by reflow soldering. , a land 3 is formed on the printed wiring board according to the width of the terminal lead 6 and the pitch between each terminal lead, and an opening 8 corresponding to the land 3 is formed.
A method is used in which the cream solder 4 is printed on the land 3 using a printing mask 7 having a 100% density, and the solder is bonded by reflow soldering.
この場合、ランド3の巾は、端子リード6の巾より充分
大きく取り、同ランド3の巾よりやや小さい開口8を有
するはんだ印刷用マスク7により、クリームはんだ4を
印刷するのが通例で、リフロ−はんだ付けにより溶融さ
れたクリームはんだ4は、表面張力によりランド3と端
子リード6の間を伝わり均一にはんだ付けされ、過剰な
りリームはんだ4はランド3に拡がりフィレットを形成
して、はんだ付け信頼性が保証されていた。In this case, the width of the land 3 is made sufficiently larger than the width of the terminal lead 6, and the cream solder 4 is usually printed using a solder printing mask 7 having an opening 8 slightly smaller than the width of the land 3. - The cream solder 4 melted during soldering is transmitted between the land 3 and the terminal lead 6 due to surface tension, and is soldered uniformly, and the excess ream solder 4 spreads over the land 3 and forms a fillet, resulting in reliable soldering. sex was guaranteed.
近来、集積回路の高集積化が進むにつれて多端子化し、
端子リード巾とリード間のピッチが挟まり、クラオード
タイプの電子部品で端子数が100ビンで、端子中が0
.5mm、端子リード間ピッチが0.65mmのものま
で実用化されている。In recent years, as integrated circuits have become more highly integrated, the number of terminals has increased,
The terminal lead width and the pitch between the leads are pinched, and the number of terminals is 100 in a Claude type electronic component, and the terminal inside is 0.
.. 5 mm, and those with a pitch between terminal leads of 0.65 mm have been put into practical use.
この場合、ランド3の巾は、端子リード6の巾と同程度
の寸法に設定され、第5図および第6図に示すように、
隣接する端子リード間隔が挟まり、溶融されたクリーム
はんだ4が押し出され、隣接する端子リード6またはラ
ンド3に接触して短絡を生じる事例が多く発生し、この
検査と修正のための作業が生産の障害となっている。In this case, the width of the land 3 is set to be approximately the same as the width of the terminal lead 6, and as shown in FIGS. 5 and 6,
There are many cases where the gap between adjacent terminal leads gets pinched, and the molten cream solder 4 is pushed out and comes into contact with the adjacent terminal lead 6 or land 3, causing a short circuit. It has become an obstacle.
〔発明が解決しようとする課題]
本発明は、上記従来の技術の問題点に鑑みなされたもの
で、隣接する導体パターシ面3間のクリームはんだの洩
出による短絡を解消することができるはんだ接合方法を
提供することを目的としている。[Problems to be Solved by the Invention] The present invention has been made in view of the problems of the conventional technology described above, and provides a solder joint that can eliminate short circuits caused by leakage of cream solder between adjacent conductor pattern surfaces 3. The purpose is to provide a method.
上記目的を達成するために、本発明ではランド3を複数
に区画してこの区画の一部にクリームはんだを印刷しな
い余白部を形成し、上記クリームはんだ印刷面3aの面
積と余白部の面積の比によりクリームはんだの量を変え
てはんだ付け接合するようにした。In order to achieve the above object, in the present invention, the land 3 is divided into a plurality of sections, and a margin portion in which cream solder is not printed is formed in a part of the division, and the area of the cream solder printing surface 3a is equal to the area of the margin section. The amount of cream solder was changed depending on the ratio and the solder joints were made.
上記構成によれば、ランド3の一部を区画して端子リー
ドの接合面にクリームはんだ4の余白部5を形成し、ク
リームはんだ4を複数面に分割して印刷し、リフローは
んだ付けにより、クリームはんだ4が余白部5を含めて
ランド3と端子リードの接合面に均一に分散し、クリー
ムはんだ4の洩出を防ぎ、隣接する端子リード6または
ランド3間での短絡を防止することができる。According to the above configuration, a part of the land 3 is divided to form a margin 5 of the cream solder 4 on the joint surface of the terminal lead, the cream solder 4 is divided into a plurality of surfaces and printed, and by reflow soldering, The cream solder 4 is evenly distributed on the bonding surface between the land 3 and the terminal lead including the margin 5, thereby preventing leakage of the cream solder 4 and preventing short circuits between adjacent terminal leads 6 or lands 3. can.
以下、本発明の一実施例について添付図面を参照して詳
細に説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.
第1図は、クラオードタイプのフラットパッケージ形の
電子部品1をプリント配線vi、2に搭載する状況を示
している。FIG. 1 shows a situation in which a Claude type flat package electronic component 1 is mounted on printed wiring lines vi and 2. As shown in FIG.
電子部品lは、本体部より複数の端子リード6を導出し
、同端子リード6をガルウィング状に折曲げ、開端子リ
ーと6の接合面を面一になるように形成している。In the electronic component 1, a plurality of terminal leads 6 are led out from the main body, and the terminal leads 6 are bent into a gull wing shape, so that the joint surfaces of the open terminal leads and 6 are flush with each other.
プリント配線板2には、上記複数の端子リード6の接合
面に合わせて、複数のランド3を形成し、同時にクリー
ムはんだ4の印刷用マスク7を位置決めするガイドマー
クまたはガイドビン孔(図示せず)を配設している。A plurality of lands 3 are formed on the printed wiring board 2 in accordance with the bonding surfaces of the plurality of terminal leads 6, and at the same time guide marks or guide bin holes (not shown) are formed for positioning the printing mask 7 of the cream solder 4. ) are installed.
印刷用マスク7は、上記端子リーと6の接合面に合わせ
、複数の区画された開口8を形成し、プリント配線Fi
2のガイドマークまたはガイドビンにより開口8を導体
パターン面3上に位置合わせしている。The printing mask 7 has a plurality of partitioned openings 8 formed in alignment with the bonding surface of the terminal wire 6 and the printed wiring Fi.
The opening 8 is aligned on the conductor pattern surface 3 using guide marks or guide bins.
印刷用マスク7の上から、クリームはんだ4をスキージ
により複数の区画された開口8を通してランド3上にク
リームはんだ印刷面3aと余白部5により区分された状
態に印刷する。From above the printing mask 7, the cream solder 4 is printed with a squeegee through a plurality of divided openings 8 onto the land 3 in a state divided by the cream solder printing surface 3a and the margin part 5.
クリームはんだ4の印刷は、使用時の室温により粘度が
左右され、印刷時にたれまたはすけを生じるため温度調
整された室内で行い、且つ充分な攪拌を行って使用する
。The viscosity of the cream solder 4 depends on the room temperature at the time of use, and sagging or sagging occurs during printing. Therefore, the cream solder 4 should be printed in a temperature-controlled room and thoroughly stirred.
印刷用マスク7を取り除き、印刷されたクリームはんだ
4上に、フラットパンケージ形電子部品1を位置合わせ
して搭載し、リフローはんだ付けによりはんだ接合を行
う。The printing mask 7 is removed, the flat pan cage type electronic component 1 is aligned and mounted on the printed cream solder 4, and solder joint is performed by reflow soldering.
第2図、第3図および第4図は、本発明の詳細を示す部
分平面図(a)と部分側面断面図(b)である。2, 3 and 4 are a partial plan view (a) and a partial side sectional view (b) showing details of the invention.
第2図(a)に示すようにランド3のはんだ接合部およ
びランド3の間を除く外周には、はんだレジスト9を印
刷しである。As shown in FIG. 2(a), a solder resist 9 is printed on the outer periphery of the lands 3 except for the solder joints and between the lands 3.
第2図は、プリント配線板2のガイドマークに合わせて
、クリームはんだ4の印刷用マスク7を位置決めした状
態を示し、印刷用マスク7に形成された二つの開口8.
8の間の間隙が形成されている。FIG. 2 shows a state in which the printing mask 7 of the cream solder 4 is positioned in accordance with the guide marks on the printed wiring board 2, and the two openings 8 formed in the printing mask 7.
A gap of 8 is formed.
第3図は、印刷用マスク7によりクリームはんだ4をラ
ンド3上に印刷した状態を示し、クリームはんだ印刷面
3aの中央部に余白部5が形成されている。FIG. 3 shows a state in which cream solder 4 is printed on land 3 using printing mask 7, and a margin 5 is formed in the center of cream solder printing surface 3a.
第4図は、端子リード6をはんだ接合した状態で、クリ
ームはんだ4は溶融して表面張力により流動し、余白部
5を埋めて上記端子リード6とランド3の間を均一に接
合する。FIG. 4 shows a state in which the terminal leads 6 are soldered together, and the cream solder 4 melts and flows due to surface tension, filling the margin 5 and uniformly joining the terminal leads 6 and the lands 3.
上記ランド3のクリームはんだ印刷面3aの面積と余白
部5の面積の比を変えることにより、クリームはんだ4
の量を変え、リフローはんだ付けにより、クリームはん
だ4が隣接した端子リード6または導体パターン面3に
向は洩出さない適切なりリームはんだ4の量および印刷
条件を選択することができる。By changing the ratio of the area of the cream solder printed surface 3a of the land 3 to the area of the margin part 5, the cream solder 4
By changing the amount of reflow soldering, it is possible to select an appropriate amount of ream solder 4 and printing conditions so that cream solder 4 does not leak toward adjacent terminal leads 6 or conductor pattern surfaces 3.
第2図においては、余白部5を中央部に設けた例を示し
ているが、複数の余白部を設け、その両側または片側に
クリームはんだ印刷面3aを形成することにより、クリ
ームはんだ4を平均的に分散して配置し、リフローはん
だ付けによりクリームはんだ4が流出し、余白部5を埋
めて上記端子リード6とランド3の間を均一に接合する
。Although FIG. 2 shows an example in which the margin 5 is provided in the center, by providing a plurality of margins and forming the cream solder printed surface 3a on both sides or one side, the cream solder 4 can be averaged. The cream solder 4 flows out by reflow soldering, fills the margin 5, and uniformly joins the terminal lead 6 and the land 3.
本発明は、上記のように構成されているので、リフロー
はんだ付けにより、溶融したクリームはんだ4がクリー
ムはんだ印刷面3aからランド3上に、均一なはんだ層
を形成し、従来例のように溶融したクリームはんだ4が
洩出し、隣接するランド3または端子リード6と短絡す
る事故を防ぐことができた。Since the present invention is configured as described above, by reflow soldering, the molten cream solder 4 forms a uniform solder layer from the cream solder printing surface 3a on the land 3, and unlike the conventional example, the molten cream solder 4 forms a uniform solder layer on the land 3. It was possible to prevent an accident in which the cream solder 4 leaked out and caused a short circuit with the adjacent land 3 or terminal lead 6.
また電子部品を搭載する場合に、ランド3と端子リード
6のずれを、露出したクリームはんだ4の余白部5をガ
イドにすることにより、手作業または自動装着において
も容易に位置決めすることができた。Furthermore, when mounting electronic components, by using the exposed margin 5 of the cream solder 4 as a guide to correct the misalignment between the land 3 and the terminal lead 6, the positioning can be easily performed either manually or automatically. .
第1図は、フラットパッケージ形電子部品のプリント配
線板への搭載を説明する一部省略斜視l第2図はランド
に印刷用マスクを位置合わせしている状態の一部省略部
分断面図および平面図、第3図はクリームはんだの印刷
状態の一部省略部分断面図および平面図、第4図ははん
だ結合状態をしめず一部省略部分断面図および平面図、
第5図および第6図は従来例を示す部分平面図およびA
−A断面図である。
図中、1は電子部品、2はプリント配線板、3はランド
、4はクリームはんだ、5は余白部、6は端子リード、
7は印刷用マスク、8は開口、9ははんだレジストであ
る。
特許出願人 株式会社富士通ゼネラル第5図
第、6図Figure 1 is a partially omitted perspective view illustrating the mounting of a flat package type electronic component on a printed wiring board. Figure 2 is a partially omitted partially sectional view and plan view showing the printing mask aligned with the land. Figure 3 is a partially omitted partial sectional view and plan view of the printed state of cream solder, and Fig. 4 is a partially omitted partial sectional view and plan view of the solder bonded state.
5 and 6 are partial plan views showing the conventional example and A
-A sectional view. In the figure, 1 is an electronic component, 2 is a printed wiring board, 3 is a land, 4 is cream solder, 5 is a margin, 6 is a terminal lead,
7 is a printing mask, 8 is an opening, and 9 is a solder resist. Patent applicant: Fujitsu General Ltd. Figures 5 and 6
Claims (2)
に対応してプリント配線板上に形成された複数のランド
にクリームはんだを印刷し、リフローはんだ付けにより
接合するはんだ付け接合方法において、上記ランドを複
数に区画してこの区画の一部にクリームはんだを印刷し
ない余白部を形成し、上記クリームはんだ印刷面の面積
と余白部の面積の比によりクリームはんだの量を変えて
はんだ付け接合するようにした電子部品のはんだ付け接
合方法。(1) In a soldering method in which cream solder is printed on a plurality of lands formed on a printed wiring board corresponding to a plurality of terminal leads led out from the main body of an electronic component, and the solder is bonded by reflow soldering, the above-mentioned Divide the land into multiple sections, form a margin where cream solder is not printed in a part of the section, and solder and join by changing the amount of cream solder depending on the ratio of the area of the cream solder printed surface to the area of the margin. A method of soldering and joining electronic components.
面を形成し、リフローはんだ付けにより余白部にクリー
ムはんだが浸透するように該余白部を形成したことを特
徴とする請求項(1)記載の電子部品のはんだ付け接合
方法。(2) Claim (1) characterized in that cream solder printed surfaces are formed opposite both sides of the margin, and the margin is formed such that the cream solder penetrates into the margin by reflow soldering. Method of soldering the electronic components described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63326497A JPH02172293A (en) | 1988-12-24 | 1988-12-24 | Solder bonding method for electronic parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63326497A JPH02172293A (en) | 1988-12-24 | 1988-12-24 | Solder bonding method for electronic parts |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02172293A true JPH02172293A (en) | 1990-07-03 |
Family
ID=18188487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63326497A Pending JPH02172293A (en) | 1988-12-24 | 1988-12-24 | Solder bonding method for electronic parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02172293A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5400953A (en) * | 1992-09-12 | 1995-03-28 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Method of printing a bonding agent |
-
1988
- 1988-12-24 JP JP63326497A patent/JPH02172293A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5400953A (en) * | 1992-09-12 | 1995-03-28 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Method of printing a bonding agent |
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