JPH02170747A - Wide band digital data exchange - Google Patents

Abstract

PURPOSE:To reduce a cell rejection rate by deciding the connected condition of its own switch based on a destination address and an idle or blocked state identifying bit stored in the header of a cell by means of each 2X2 unit switch. CONSTITUTION:An idle or blocked state identifying bit I to indicate whether effective information is stored in an information field D of the cell or not is provided to a heater H of the cell, and each 2X2 unit switch 18 the connected condition of its own switch 18 based on a destination address AD and the identifying bit I stored in the header H of the cell. Consequently, when the cells having the effective information collide with each other, the cell with a high priority is outputted to a prescribed output terminal according to the stored destination address AD, the cell with a low priority is rewritten in a condition in which the identifying bit I stored in the header H does not have the effective information, and it is sent to the terminal at a side different from the prescribed output terminal. Thus, the rejection rate of the cell is lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital switching device, and particularly to an ATM (Asymptomatic Switching System).
The present invention relates to improving the cell discard rate in a broadband digital switching device using chronous transfer mode.

[Conventional technology]

Conventional ATM switch technology of this type is described in, for example, "Nikkei Electronics J, January 11, 1988 issue (No. 4)".
38), pages 128-137.

The ATV switch described in this document uses a Banyan network in which 2×2 unit switches are regularly arranged as a switch element network for exchanging and connecting digital information. The connection state of each of these unit switches is changed according to the destination address stored in each cell, and the cells input to each input channel of the Banyan network are output to a predetermined output channel. Also,
If cells input to the two input terminals of each unit switch collide because they have the same destination address, one of the cells will be output preferentially to a predetermined output terminal of the unit switch according to the stored address. , the other cell is output to an output terminal different from the original output terminal according to the destination address, and reaches an output terminal of the Banyan network different from the destination address.

[Problem to be solved by the invention]

In this way, in the switch element network in the conventional ATM switching equipment described above, when cells collide, the cell whose transmission path is not prioritized (hereinafter, the prioritized cell is the winning cell, and the non-prioritized cell is is called the losing cell)
is no longer output to a predetermined output terminal according to the destination address stored in the cell. In other words, a cell that loses once becomes a completely invalid cell within the Banyan network, but each unit switch determines its own connection state by looking at only one bit of the destination address. Therefore, there is a possibility that a cell that has lost twice collides with a valid cell that has been winning until then in the next stage unit switch, and wins against the valid cell.

As a result, invalid cells within the Banyan network interfere with the transmission path of valid cells, resulting in an increased cell discard rate in the ATM switching equipment.

[Means to solve the problem]

The present invention has been made to solve such problems, and includes providing an empty identification bit in the cell header to indicate whether or not valid information is stored in the information field of the cell.
Each 2×2 unit switch is configured to determine its own connection state based on the destination address and idle identification bits stored in the header of the cell.

[Effect]

When cells with valid information collide with each other, the cell with higher priority is outputted to a predetermined output terminal according to the stored destination address, and the cell with lower priority is outputted according to the empty identification bit stored in its header. is rewritten to have no valid information and is sent to a terminal on a different side from the predetermined output terminal.

〔Example〕

Next, the present invention will be described in detail below with reference to the drawings.

FIG. 5 is a diagram showing the format of a cell used as one unit packet for information transmission in an embodiment of the present invention.

In the figure, a cell is broadly divided into a fixed-length header H and a fixed-length information field D. Header H consists of 2 bytes, including 1 empty/busy identification bit!
, a 3-bit address AD representing the destination to which the cell is to be transmitted, and a spare part SB in which control data for error detection, etc. are written, and an empty/busy identification bit I is placed at the beginning according to the time order of transmission. The following are arranged in the order mentioned above. Further, the information field D is composed of 98 bytes, and stores digital information to be transmitted expressed in binary numbers. If valid information is stored in this information field D, the empty block identification bit ■ of the header H is set to "1", and the information field D
If no valid information is stored in the block identification bit, the block identification bit is set to "0".

FIG. 4 is a block diagram showing an 8×8 exchange switch, which is a switch network of a digital exchange device to which an embodiment of the present invention is applied.

In the same figure, an 8×8 exchange switch 17 having 8 (23) input channels 1 to 8 and 8 output channels 9 to 16 has three 2×2 unit switches 18 as one unit.
It consists of a Banyan network with 4 columns and 4 rows, and a total of 12 2×
A two unit switch 18 is used. In addition, the switching pulse generation circuit 19 receives the cell synchronization signal C and generates switching pulses P1 to P3 to the blocks 20 of the 2×2 unit switches 18 configured for each column.
~22, output at different timings. The switching pulses P1 to P3 are signals synchronized with the timing at which the head of the cell passes through each 2×2 unit switch 18. Therefore, the transmission path of cell data input to each input channel 1 to 8 is switched for each block 20 to 22 in synchronization with the timing at which switching pulses P1 to P3 are input, and 16.

FIG. 2 shows a 2×2 unit switch 1 which is one unit constituting the above-mentioned 8×8 exchange switch 17 according to an embodiment of the present invention.
FIG. 8 is a block diagram showing a schematic internal configuration of the computer.

In the figure, input terminals 18a and 18b are connected to shift registers 23 and 24, and each of these shift registers 23 and 23
．． A clock pulse CLK is input to 24. Cells A and B input to input terminals 18a and 18b are synchronized with this tarlock CLK, and are transferred one bit at a time to shift register 2.
Included in 3.24.

Further, the controller 25 controls each 2×2
This determines the connection state of the unit switch 18 itself. In other words, the controller 25 controls the shift register 23.
Input bit signals A and A to a predetermined flip-flop circuit among the plurality of flip-flop circuits constituting 24.
By taking in and nB,B at the time n when the switching pulse P is input as described later, the cells A, B
The empty/busy identification bit (2), which is the first bit of the destination address AD, and the nth 1 bit of the destination address AD are taken in. Then, the connection state of the switch element 26nn is controlled based on the information of these bits A, B and pits A, B. Note that this subscript n is 2×2
The unit switch 18 is located in the nth column of the 8×8 exchange switch 17 (
n-1 to n-3).

FIG. 1 is a circuit diagram showing details of the internal configuration of the 2×2 unit switch shown in FIG. 2. FIG.

In the figure, each shift register 23, 24 is constituted by four D flip-flops 27-30, 31-34, and AND circuits 51, 56. Furthermore, bit Ao corresponding to the leading bit of input cells A and B is input from the data input terminals of D flip-flops 30 and 34 in the final stage (the rightmost stage in the drawing).

Bo is input to the controller 25, and bits A and B are input to the controller n n 25 from the data input terminal of the n-th stage (the n-th stage counting sequentially from the left side of the D flip-flop located at the final stage in the figure). is input. For example, when the 2X2 unit switch 18 is located in the first stage block 20, the data input terminals D of the D flip-flops 29 and 33 are used; (in the illustrated case), and when located in the third stage block 22, data from the data input terminals of the D flip-flops 27 and 31 is connected so that data is input to the controller 25. . Further, each of these D flip-flops 27 to 34 outputs the signal inputted to the data input terminal to the data output terminal Q in synchronization with the clock signal CLK.

The controller 25 has a NOT circuit 39.40
, AND circuits 35 to 38, NAND circuits 53 and 55, an OR circuit 41, and D flip-flops 42, 43, and 52.54.

Each of these logic circuits is connected in accordance with the logic formula shown in Table 1 below. That is, based on the bits A, B, A, and B signals input to the controller 25, the control signal S for controlling the connection state of the 0 0 n n switch cable 26 is N.
OT circuit 39, AND circuit 36, 37 and OR circuit 4
1, and the reset signals RA and RB that reset the empty/occupied identification bit I of the cell that was not prioritized when cells collided are NOT circuits 39.40
A logical operation is performed by AND circuits 35 and 38.

In the same table, "." represents a logical product, "+" represents a logical sum, and "-" represents an inverted signal.

Table 1 The logically operated control signal S is sent to the D flip-flop 42.
43, the switching pulse P is output in synchronization with the timing at which the switching pulse P is input. This is because the aforementioned switching pulse P is input to the clock terminal CLK of the D flip-flop 42. This switching pulse P is applied to the data input terminals of D flip-flops 30.34 constituting the shift register 23.24, and is applied to bits A and B corresponding to the leading bits of the cell.

In other words, it is set to rise at the timing when each blockage identification bit I reaches. Also, bits A and B at this timing are n of each cell.
n Corresponds to the nth bit from the beginning of the destination address AD.

The timing relationship between the switching pulse P and the clock signal CLK is shown in FIG. In other words, the switching pulse P shown in FIG. 5(b) rises after a certain period of time has elapsed from the rise of the clock CLKI of the clock signal CLK shown in FIG. It is designed to fall down after a period of time has elapsed. Therefore, the D flip-flop 43 shown in FIG. 1 to which the clock signal CLK is input outputs a new control signal S according to the cell information input this time at the rising timing of the clock signal CLK2, and the switch element 26.

In addition, the logically operated reset signals RA and RB are AND
Output from circuits 35 and 38 to D flip-flop 52
．． 54 and output to the NANDAND circuit 53 in synchronization with the input timing of the switching pulse P.

The NAND circuit 53 further performs a NAND operation on the switching pulse P, inverts the signal, and inputs it to the AND circuits 51 and 56 in the shift registers 23 and 24.

AND circuits 51.56 perform a logical product of the output signal of the NAND AND circuit 53 and the output signal of the D flip-flop 29.33, and output the logical product result to each data input terminal of the D flip-flop 30.34. Ru. Therefore, the empty/occupied identification bit I of the cell that lost in the collision is the reset signal RA.

RB becomes "1", then it is inverted and becomes "0", and then A
It is reset by being input to the ND circuits 51 and 56.

The switch element 26 is a NOT circuit 44, NOR
It is composed of circuits 45 to 48 and NOR circuits 49 and 50, and their connection states are switched as shown in Table 2 below based on the control signal S output from the controller 25.

Table 2 shows that when the control signal S is "0", the input terminal 1
Cell data A and B input from 8a and 18b and output from shift registers 23 and 24 are respectively output from output terminal 1.
8d, 18c, each input terminal 18a, 18b and each output terminal 18d.

The connection line connecting 18c intersects with cell data A.

The traveling directions of B will intersect. In addition, the control signal S
When is "1", cell data A and B are output to the output terminals 18c and 18d, respectively, and the connection lines connecting the input and output terminals are parallel to the cell data A.

The direction of travel of B is straight.

This connection state is achieved by the following operation of the switch element 26. That is, when the control signal S is "0", the inverted signal S of the control signal S output from the NOT circuit 44 becomes "1", and one input of the NOR circuit 45.48 is always at a high level. Therefore, the NOR circuit 45.
The output of 48 is always at a low level regardless of these other inputs.

Also, since the control signal S is "0", the NOR circuit 46.4
One input of NOR circuit 46.7 is always at a low level.
The output of 47 is determined according to these other inputs. That is, the output of the NOR circuit 47 becomes an inverted signal of the data input to the input terminal 18a, and the output of the NOR circuit 46 becomes an inverted signal of the data input to the input terminal 18b.

Furthermore, the output of the NOR circuit 47 is input to the NOR circuit 50, and the input data from the input terminal 18a is again inverted and returned to the original signal, which is output to the output terminal 18d. Further, the output of the NOR circuit 46 is further input to the NOR circuit 49, where it is inverted again and returned to the original signal, and the output terminal 1
It is output to 8c.

As a result, when the control signal S is "0", the traveling directions of the input cells A and B intersect.

Furthermore, when the switch switching signal S is "1", one input of the NOR circuits 46.47 is always at a high level, which is the opposite of the above case, so the output of these NOR circuits 46.47 is always at a low level. become. Also, NOR circuit 45.4
One input of NOR circuit 8 is always at a low level, and the output of these NOR circuits 45 and 48 is determined according to these other inputs. That is, the output of the NOR circuit 45 becomes an inverted signal of the data input to the input terminal 18a, and the output of the NOR circuit 48 becomes an inverted signal of the data input to the input terminal 18b. Furthermore, the output of the NOR circuit 45 is
The input data from the input terminal 18a is again inverted and returned to the original signal, and is output to the output terminal 18c. Further, the output of the NOR circuit 48 is input to the NOR circuit 50, which inverts it again and returns it to the original signal, and outputs it to the output terminal 1.
It is output to 8d.

As a result, when the control signal S is "1", the inputted cells A and B move straight ahead.

In such a configuration, cells input to each input channel 1 to 8 of the 8X8 exchange switch 17 are taken in from the empty identification bit ■ of the header H located at the beginning of each cell. When taken in, the cell synchronization signal C is input to the switching pulse generation circuit 19. The switching pulse generation circuit 19 has a header H of 8X
During the period from being taken into the first stage block 20 of the 8 exchange switch 17 until being output from the final stage block 22,
Each of the switching pulses P1 to P3 is output at a timing when each block 20 to 22 needs to be switched.

At the timing when the switching pulses P1 to P3 are output, the vacancy identification bit 1 and the corresponding bit of the destination address AD are input to the controller 25 of each 2×2 unit switch 18.

The controller 25 executes a predetermined logical operation according to the above-mentioned Table 1 based on each of the input bit information, and outputs a control signal S, which is the result of the operation, to the switch element 26. The switch element 26 inputs this control signal S, and determines the connection state of the switch itself as follows according to Table 2 mentioned above.

That is, at least one of the two cells input to the 2×2 unit switch 18 has an empty/busy identification bit I of “0”.
In the case of , bit A at the timing when switching pulse P is output. Or B. At least one of them becomes "0".

Therefore, as understood from the logical operation formula in Table 1, the control signal S is
) is not “0” bit A of the destination address AD of the cell
or B, and n
n The connection state of the switch element 26 is determined when the empty/occupied identification bit l is "0".
” is determined to be output preferentially.

In this case, A or B as mentioned above. Since either one of the reset signals RA and RB always becomes "0", as can be understood from the logical expression in Table 1, both the reset signals RA and RB become "0". For this reason,
The output signal to the AND circuit 51.56 in the shift register 23.24 becomes "1", and the D flip-flop 30.3
The input data of No. 4 corresponds to the data output from the D flip-flops 29 and 33. This is because when either one of the blockage identification bits I is "0", a control signal S is generated so that the destination address of the cell information that is "0" is ignored, and a cell collision occurs. This is because it does not occur.

Also, the empty/occupied identification bit I of the two input cells are both “1”.
”, and bits A and B of the destination address AD
are different from each other, i.e. if valid information is stored in the n2 input cells and the corresponding bits of their respective destinations are different, the control signal S can be understood from Table 1 in the same way as in the above case. The combination of bits A and H determines n n so that the connection state of the switch element 26 is determined.

Also in this case, the reset signals RA and R
Both signals of B become "0". This is bit A
, B values are different from each other due to different destinations.
n, of these bits A and B, always n
n One side becomes rOJ, bits A, ,B shown in Table 1
and the logic n of bits A and B
n
This is because n implantation always becomes "0".

On the other hand, if both of the two input cells have valid information with the value of the empty identification bit I being "1" and the corresponding bits Ao and B of the destination address AD are the same, then the input cell collide.

■ For this reason, the process is as follows: a winning cell is output to the output terminal according to the destination address stored in that cell, and a losing cell has its empty identification bit I set to "0".
The connection state of the switch element 26 is determined so that the destination address is reset and output to an output terminal different from the destination address.

In other words, if each of bits A and B is "1", n In this case, A in the equation for signal S in Table 1.

A becomes “0” and B −B becomes “1” n
On, therefore, the control signal S becomes "1". Therefore, the connection state of the switch element 26 is determined in the direction in which the cell data travels straight, as shown in Table 2. At this time, since each bit in the calculation formula for the reset signal RA shown in Table 1 is all "1", the logical operation result for the reset signal RA is "1".
”, and the AND circuit 5 in the shift register 23
When it is input as 1, it becomes "0" and the input data of the D flip-flop 30 is forced to become "0". Therefore,
The empty/occupied identification bit I of the cell A inputted from the input terminal 18a is forcibly rewritten to "0", marked as a cell having no valid information, and outputted to the output terminal 18c. Furthermore, since A −B in the calculation formula for the reset signal RB shown in Table 1 becomes n n “0”, the reset signal RB becomes “0”, and when input to the AND circuit 56 in the shift register 24 , it becomes "1" and the input data of the D flip-flop 34 becomes "1". Therefore, in the cell B input to the input terminal 18b, the empty/busy identification bit l is maintained at "1", and the cell B is regarded as valid information and is output preferentially to the output terminal 18d.

Also, if each bit A and B is “0”, n
n is A in the equation for signal S in Table 1.

A becomes “1” and B −B becomes “0” n
Since it is on, the control signal S also becomes "1". Therefore, the connection state of the switch element 26 is determined in the direction in which the cell data travels straight, as in the above case.

In addition, the reset signal R obtained from the logical operation formula in Table 1
A becomes "O", the reset signal RB becomes "1", and the vacancy identification bit I of cell A input to the input terminal 18a becomes "1".
'' is maintained as valid information, and the empty/occupied identification bit I of cell B inputted to the input terminal 18b is forcibly reset to rOJ and marked as invalid information.

According to this embodiment, each 2×2 unit switch 1
Even if cells with valid information and the same destination address are input to cell 8 at the same time and the cells collide, the empty identification bit I is set to ``0'' to indicate that the losing cell does not have valid information. ' can be rewritten as '. Therefore, even if a losing cell is sent out in a direction different from the predetermined route at the timing when the switching pulse P is input, the next unit switch will treat it as a cell that does not have valid information, so it will not be able to transmit valid information. The losing rate of the cell holding the cell will be reduced, and at the same time, the possibility of false information being transmitted will be eliminated.

In the above embodiment, the case where the present invention is applied to an 8×8 exchange switch 17 has been explained, but the present invention is not limited to this. For example, it may be applied to a 16×16 switch, etc., and the present invention can be applied to a 16×16 switch. It has a similar effect.

〔Effect of the invention〕

As explained above, the present invention provides an empty/busy identification bit in the cell header indicating whether or not valid information is stored in the information field of the cell, and each 2×2 unit switch stores information in the cell header. By configuring the switch to determine its own connection status based on the destination address and blockage identification bit, in the event of a collision between cells with valid information, the cell with higher priority is memorized. Cells with low priority are output to a predetermined output terminal according to the destination address, and the empty/busy identification bit stored in the header of the cell is rewritten to a state where it does not contain valid information, and the cell is output to a terminal on a different side from the predetermined output terminal. sent to.

Therefore, in the present invention, when a cell collision occurs, even if the losing cell is transmitted to an output channel different from the destination address stored in that cell, it is identified as a cell that does not have valid information and processed. This has the effect of reducing the loss rate of cells with valid information, and at the same time solving the conventional problem of erroneous information being transmitted to the output channel.

Therefore, the effective discard rate of cells is reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the details of the internal configuration of a 2×2 unit switch according to an embodiment of the present invention, and FIG.
Circuit diagram showing the outline of the internal configuration of the X2 unit switch, Part 3
Figures (a) and (b) are timing charts of the clock signal CLK and switching pulse P used in this embodiment, and Figure 4 shows an 8x8 exchange switch in which the 2x2 unit switch is one unit of the configuration. The block diagram, FIG. 5, is a diagram illustrating the cell format used in this embodiment. 18...2X2 unit switch, 18a, b...input terminal, 18c, d...output terminal, 23.24...shift register, 25...controller, 26...switch element. Block diagram showing an outline of a one-man chain
Salt 1) Tatsuya Rocco CLK
・Timing chart of switching pulse P Figure 3

Claims (1)

[Claims] 2x for switching connections between 1 and 2 input terminals and 2 output terminals
N× configured by combining multiple 2-unit switches
A broadband digital exchange that is equipped with N switching switches and switches the transmission path of cells storing digital information by switching connections between N input channels and N output channels, thereby establishing broadband switching connections. In the device, an empty/busy identification bit is provided in the header of the cell to indicate whether valid digital information is stored in the information field of the cell, and each 2×2 unit switch is configured to read the destination address and the information stored in the header of the cell. A broadband digital switching device characterized in that the connection state of the switch itself is determined based on the blockage identification bit. 2. Each 2 x 2 unit switch selects one of the two unit switches when the destination addresses of the cells input to the two input terminals are the same and both empty/occupied identification bits indicate a state in which valid digital information is stored. Outputs the cell input to the input terminal according to the destination address stored in this cell, and writes the empty identification bit of the cell input to the other input terminal to a state indicating that no valid digital information is stored. 2. The broadband digital switching device according to claim 1, wherein