JPH0216828A - Time division multiplex device - Google Patents

Abstract

PURPOSE:To attain octet multiplexing and bit multiplexing only by means of changing the content of a memory by setting to which signal among received signals multiframe phase control is executed, multiplexing and separating data signals and control signals in respective terminals based on information which has been set. CONSTITUTION:In a time division multiplexing device, the content of the memory is read at the bit speed of a line and by the time period of a multiframe. At the same time, the data signals and the control signals are fetched from the terminals through a terminal interface part. Next, a multiframe synchronous pattern is inserted into a synchronous pattern insertion means according to the content of the memory and a polarity conversion means transmits a signal adjusted to the polarity of an opposite device to the line. A phase synchronous means detects the pattern, edits the signal by logical buses and transmits the data signals and the control signals through the terminal interfaces. Thus, a clock generation part 5, plural terminal interface parts 6, the buses 7-9, a multiplexing conversion part 4 and a line interface part 3 are provided in the device 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention uses a line such as a high-speed digital line to time-division multiplex the signals output from each terminal when multiple terminals transmit and receive data. This invention relates to a time division multiplexing device for sending data onto high-speed digital lines.

[Conventional technology]

A time division multiplexer (hereinafter referred to as TDM) divides one frame in time, and allocates each time slot or each bit of the divided frame to transmit data signals and control signals from each terminal. In addition to performing separation, time slots 1 to 1 are replaced for each destination according to line setting information. Such TDM can be broadly divided into TDM based on an octet multiplexing method in which octets (8 bits) are multiplexed as a basic unit, and bit multiplexing in which allocation is multiplexed in bit units in a frame structure of optimal length. There is TDM based on the method.

FIG. 9 shows, for example, rFUJITsU, 36.6J (09,
1,985), pages 545-55] - is a block diagram showing an example of the configuration of a conventional octet multiplexing TDM 200. In the figure, 100 a to 100
h is the terminal, 210a, 210b are 50 b/s −
4,8K b/s low speed terminals 100a to 100
The data signal and control signal from
s, or 64 K b/s bearer signal 110
The first multiplexing is to convert the signal into a 64 Kb/s zero-order group multiplexed signal 111. 64K
The first bit F of each octet of the O-order group multiplexed signal 11 of b/s is usually a multiframe synchronization pattern (AIIOloolo
oooololol, 110) is inserted. "rA" in this multi-frame synchronization pattern is a path alarm bit, which is set to "OI+" when the multi-frame synchronization of the corresponding logical path is lost, and is set to "1" when synchronization is established, and is sent to the partner station. Also, the 8th bit S of each octet is the terminal], O
Control signals Oa to 100f are inserted. 220 are the zero-order group multiplexed signals 111 and 64 . Kb/s
This is a second multiplexing unit that multiplexes a high-speed signal of Xn into a frame (hereinafter referred to as a frame) 112 of a primary group multiplexed signal of 1.544-Mb/s. 300 is a high-speed digital line.

Next, the operation will be explained. In FIG. 9, the first multiplexing section 210a, 210b connects the terminals 100a to 100
A terminal speed signal of f less than 300 b/s or 2.4 Kb/s will result in a bearer speed of 3.2 Kb/s;
b/s and 4.8Kb/s terminal speed signal is 6.4K
b/s bearer rate, 9.6 Kb/s terminal speed signal to 12.8 Kb/s bearer rate, 48 Kb/s
The terminal speed signal is converted to a 64, K b/S bearer speed.

FIG. 10 is a diagram showing an example of a frame structure multiplexed by the octet multiplexing TDM 200. In the figure, 15
0 is a frame synchronization bit that synchronizes the frame 112, and 120 is a frame synchronization bit when the bearer speed is 3.2Kb, for example.
This is an example when the data signals and control signals of terminals 10Oa to 100f are multiplexed, and in this case, the signals of 20 terminals], 00a, ...... are combined into one TS (time slot 1). ~) (64 KHz) and is multiplexed and transmitted. 12], the bearer speed is 6.4K
This is an example of multiplexing the signals of terminals 100a, . . ., which become b/S.
The signal of 00a is multiplexed using one T S ], 13 and transmitted.

122 is when terminal signals with a bearer speed of 12.8 Kb/s are multiplexed, and in this case, one T S
i13, signals from up to five terminals 100a, . . . are multiplexed and transmitted. 123 bearer speed is 6
4- K b / s terminal 100 g +100
This is an example when signals of h are multiplexed, and in this case, one T S 113 can transmit only a signal of one terminal] 00g.

When the octet multiplexing TDM 200 on the receiving side receives the frame 112 shown in FIG. The first multiplexing unit 2]-0 detects the beginning of one multiframe consisting of 20 subframes using the leading multiframe synchronization bit F, and separates the signals from this for each terminal 100a, . . . .

Multiplexing example with bearer speed of 6.4-Kb/s in Figure 10]
For example, when receiving TS1]3 of 21, the signals of frame numbers (frame Nα) 1- and 1] are transmitted to CH2 of FIG.
Terminal 1 corresponding to 1. To OOa, the signals of frames Nn 2 and 12 are sent to the terminal 100 corresponding to CH22 in FIG.
Separate into b and so on.

The signals separated above are further multi-frame synchronized.
Separate into F, information bit I-D S is held until the next status bit S is received as an output control signal to the terminal 100a, . In the above example, ITS is used as one subframe.

Next, FIG. 11 is a block diagram showing a configuration example of a bit multiplexing TDM 400. In the figure, 410 is 64. K
From low speed below b/s to 64K b/s
This is a third multiplexing unit that encodes data signals and control signals from each of n high-speed terminal devices 100a to 100h by one-point or multi-point sampling and directly multiplexes them.

FIG. 2 is an example of a frame structure that is multiplexed by the bit multiplexing TDM 400 of FIG. 11 and transmitted over the high-speed digital line 300. 1st time slot 1~TS
The first bit of I is the multiframe synchronization bit F into which the multiframe synchronization pattern described above is inserted.
The remaining 191 pins 1- are terminal devices 1008-1. OO
It is used to transmit h data signals and control signals.

Next, the operation will be explained. In FIG. 12, two TSs (1
1゜2 K using 11a) and (11l b)
An example is shown in which data signals for one b/s terminal, 20 2.4 Kb/s terminals, and 12 4.8 Kb/s terminals are multiplexed with one control signal for each terminal.

CH, +--CH20 is 2.4Kb/s terminal, CH2
1, -CH32 is a 4.8Kb/s terminal, CH33 is 1
．． 2 Kb/s terminal signals are allocated, and the portions surrounded by white circles of each channel are allocated to control signals, and the portions without circles are allocated to data signals.

During transmission, the third multiplexer 410 in the bit multiplexing TDM 400 multiplexes the signals from the corresponding terminals according to the bit allocation of the frame 112 shown in FIG. A multi-frame synchronization bit F is added to 1 bit, and a frame synchronization bit i~]-50 is inserted at the beginning of frame]12, and the high-speed digital line 3
Send to 00.

Bit multiplexing TDM4 on the receiving side. In OO, when the frame 112 shown in FIG. 12 is received, the third multiplexer 410
The first TS (1,
1,1,a) Multi-frame synchronization pin 1~
F is used to perform multi-frame synchronization and identify each received frame Nα. According to this frame Nn, signals within the frame 112 are separated for each terminal 100a to 100h. In the multiplexing example shown in FIG. 12, the first TS (1,
11a), and if the frame Nn at that time is 1, the second bit of the first TS (111a) is sent to the terminal 100a corresponding to CHI in FIG. 12, and the third bit is the same < CH3. The fourth bit is the same (CI-16) to the terminal 100b corresponding to the terminal 100b, and the fourth bit is the same (CI-16. Since the CHIs 1 to 1 are circled, they are output as control signals to the terminal 100a, and are held until the next time the control signal from the terminal 100a is received.They are separated as signals to the terminals 100b and 100c. The second bit, the third bit 1~
are not circled, so the terminals 100b and 100 are respectively
c as a data signal.

[Problem to be solved by the invention]

Conventional TDMs are configured as shown below, so bit multiplexing TDMs and octet multiplexing TDMs cannot communicate with each other, and TDMs of the same multiplexing method cannot communicate with each other.
Even so, if the devices are manufactured by different manufacturers, the polarity of the signals handled inside the device may be reversed or the multi-frame synchronization method may be different, resulting in problems such as inability to communicate with each other.

This invention was made to solve the above-mentioned problems, and by simply changing various information in the memory, the TDM multiplexing method, multi-frame synchronization method, and the multi-frame synchronization method of the communicating party can be changed. The purpose is to obtain a flexible TDM that can be adjusted to signal polarity, etc.

[Means to solve the problem]

The TDM according to the present invention has a memory whose first address is accessed again in a multi-frame time period by a memory reading means that reads the memory at a line bit rate and in a multi-frame time period, and this memory has a logical path. Logical path number information for identification, logical path head instruction information indicating the head of this logical path, multiframe synchronization instruction information indicating whether information in the logical path is multiframe multiplexed, and type of multiframe synchronization pattern. synchronization pattern type information indicating the polarity relationship between the TDM internal signal and the line, squelch instruction information indicating the polarity of the squelch applied to the received signal received from the line, and which terminal interface section sends the signal to the internal path. Terminal interface address information indicating whether to output or receive a signal from the internal bus, and input/output signal identification information indicating whether the signal input/output to the internal bus by the terminal interface section is a data signal or a control signal are multiframe or frame information. The number of bits is stored corresponding to the multiframe or each bit of the frame. Furthermore, a synchronization pattern output means stores several types of multiframe synchronization patterns and outputs a specific multiframe synchronization pattern indicated by the synchronization pattern type information in the memory, and a phase cycle switching means for switching whether or not to perform multi-frame phase synchronization on the received signal; and logical path number information and logical path head instruction information in the memory, and a specific multi-frame synchronization pattern output by the synchronization pattern output means. phase synchronization means for performing multi-frame synchronization control on signals received from a line using a synchronization pattern inserting means for inserting bits of a multi-frame synchronization pattern into a predetermined position of a frame to be transmitted; It has a polarity conversion means for adjusting the internal signal of the TDM to the polarity of the other device according to the information, and a squelch means for squelching the received signal from the line in accordance with the bits according to the squelch instruction information in the memory.

[Effect]

The TDM in this invention reads the contents of the memory at the bit rate of the line and in a multi-frame time period,
At the same time, data signals and control signals are taken in from the terminal via the terminal interface section, a multi-frame synchronization pattern is inserted by the synchronization pattern insertion means according to the contents of the memory, and a signal matched to the polarity of the other device is sent to the line by the polarity conversion means. transmitting and receiving a received signal from the line, the polarity of the received signal is converted as necessary by the polarity conversion means according to the contents of the memory, the multi-frame synchronization pattern is detected by the phase synchronization means and the signal is edited for each logical path, Send data and control signals to the terminal via the terminal interface.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing an example of the overall configuration of the TDM1- of the present invention, where 2 is a common control unit that monitors and controls the entire TDMI, and 3 is an electrical and logical interface with the high-speed digital line 300 and frame synchronization control. 4 is a multiplex conversion unit that inputs and outputs signals to and from the line via the line interface unit 3 according to various multiplexing methods, and multiplexes and demultiplexes data signals and control signals handled by the terminal 100; 5; 6 is a clock generation unit that generates an internal clock synchronized with the clock of the high-speed digital line 300, 6 is a terminal interface unit that controls the interface with the terminal 100 such as a telephone or personal computer, and 7 is a clock generated by the clock generation unit 5. A clock bus 8 transmits the clock extracted from the signal from the high-speed digital line 300 by the line interface unit 3;
1, a 544 Mb/s control-side transmission data bus for transmitting data signals and control signals taken in from 0 to the multiplex converter 4; 9 a terminal interface unit 6 from the multiplex converter 4;
Transfer data received from the line to 1, 544. Mb
/s terminal side receiving data bus, 10 is 1 for transferring transmission data from the multiplexing conversion unit 4 to the line interface unit 3;
54.4. M, b/S line-side transmission data bus; 11 is a 1, 54-4 Mb/s line-side reception data bus that transfers the received signal from the line interface section 3 to the multiplexing conversion section 4; 12 is which terminal interface section; 6 is an address bus that transfers information indicating which terminal interface unit 6 receives received data from the terminal-side receiving data bus 9-]- or outputs transmission data to the terminal-side transmitting data bus 8'-2; 13 is a frame; Check the synchronization status at line interface section 3.
This is a signal line for notifying the multiplexing conversion unit 4 from the multiplexing conversion unit 4.

FIG. 2 is a diagram showing an example of the configuration of the multiplexing converter 4, in which 20 is a terminal side reception data bus interface, 21 is a terminal side transmission data bus interface, 22 is a line side reception data bus interface, and 23 is line side transmission data. 24 is a squelch selector that selects and controls whether to squelch the received signal depending on the state of multi-frame synchronization or frame synchronization; 25 is a multi-frame alignment memory; 27 and 28 are excl. Shibu OR goo 1 ~ (hereinafter referred to as EXOR), 29 is the first memory, 30 is the second memory, 31 is the third memory
Memory 32 is a multi-frame synchronization bit generation circuit that generates pins 1 to 1 of multi-frame synchronization patterns such as CCITT Recommendations x and 50.

33 is a synchronization pit selector that selects the output signal of the EXOR 28 and the output signal of the multi-frame synchronization bit generation circuit 32; 34 is a multi-frame synchronized received signal, its related signals, and frame synchronization based on the output information of the second memory 30; A frame selector 35 that selects a received signal and its related signals that only receive signals, counts the frame length and multi-frame length, and includes a first memory 29 and a second memory 30.
, a frame/multi-frame counter that generates the address of the third memory 31, 36 a delay circuit that adjusts the delay between when the received signal etc. passes through the multi-frame alignment memory 25 and when it does not, and 37 the second memory 3
Multi-frame synchronization is detected for each logical path from the received signal using the control information output from 0, and read/write address generation and reading of the multi-frame alignment memory 25 is performed to align the multi-frame phase of the received signal according to each multi-frame synchronization. 38 is a fourth memory holding a plurality of different multiframe synchronization patterns; 39 is a first memory 29, a second memory 30, and a third memory 31; A common control I/F unit 40 is an ◯R gate which performs interface control with the common control unit 2 for changing the contents, etc.

FIG. 3 shows a first memory 29, a second memory 30 . FIG. 6 is a diagram illustrating an example of borrowing a third memory 31 and a fourth memory 38. In the figure, 5o is a terminal interface address (terminal I/F address) indicating the terminal interface section 6 that accesses the terminal side transmission data bus 8 and the terminal side reception data bus 9, and 51 is the terminal side transmission data bus 8 and the terminal side reception data bus 8. This is input/output signal type information that specifies whether the signal input/output by the terminal interface unit 6 to/from the data bus 9 is a data signal or a control signal.In this example, when the content of the input/output signal type information 5 is '1'', it is a data signal. Instruct input/output of LL
2 Instructs input/output of control signals when I+.

In this embodiment, the terminal I/F address 50 and input/output signal type information 51 are 193 bits x 20 frames - 3860
P1 to P1 are written into the first memory 29 by the common control section 2 via the common control section I/F section 39. Note that in the following description, information will be omitted so that the logical path number information is referred to as the logical path number.

52 is a logical path number, 53 is a logical path start instruction indicating that it is the first bit of the logical path, 54 is a multiframe synchronization instruction indicating whether multiframe synchronization control is necessary, and 55 is a multiframe used in the logical path. This is a synchronization button type indicating the type of synchronization pattern, and this information is written in each area of the second memory 30 for each bit for the frame length. 56 indicates the polarity of data signals and control signals on the internal path of TDMI-, and the signal polarity indicating the polarity conversion at the time of input/output to the high-speed digital line 300; 57 indicates the logic in which a failure such as loss of multiframe synchronization has occurred; This is a squelch instruction that indicates the polarity of a signal when performing a squelch on a received signal on a path, and this information is stored in each area of the third memory 31 for a length of 20 frames for each bit. As mentioned above, the fourth memory 38 is a memory that stores the multi-frame synchronization pattern used in this TDMI, and is accessed using the synchronization pattern type 55 as an address. O/1 alternation pattern 5 body information is stored in the frame synchronization pattern address 58.1. In this embodiment, the memories that store each information are the first memory 29, the second memory 30, and the third memory 31, and the memory reading means is the clock generator 5, the clock path 7, and the frame/multiframe counter 35. The synchronization pattern output means is the fourth memory 38 and the multi-frame synchronization bit generation circuit 32, the phase synchronization switching means is the frame selector 34, and the phase synchronization means is the multi-frame control circuit 37 and the multi-frame alignment memory 25. The insertion means is the synchronous bit selector 33, and the polarity conversion means is the EXOR27.

At 28, the squelch means are each constituted by a squelch selector 24.

Using the conventional octet multiplexed and bit multiplexed frames shown in FIGS. 10 and 12 as examples, the operation corresponding to the TDMI double-capacity multiplexing method of the present invention will be described below. First, the operation for octet multiplexing will be explained.

Figure 4 shows that the bearer speed is 3.2Kb in Figure 10.
An example of multiplexing 20 terminals 100 with a bearer speed of 120 and a terminal 1 with a bearer speed of 6.4 Kb/s. Example 121 of 1-0 trapezoidal overlapping of O O is TS of frame 112 ], (
], 1. 1a) and the contents of the first memory 29 and the second memory 30 when multiplexing is performed using TS2 (lilb). In the figure, address 0 of the first memory 29 corresponds to the 0th bit, that is, the first bit] 50 of the frame 112 of frame Nα1, and 3859 (3
667+192) address is frame 1 of frame Nα20
]-2, that is, the last bit, and address 0 of the first memory 29 corresponds to the frame synchronization bit 1. Since 50 is the insertion/extraction position, a dummy value O is stored in the input/output signal type 51 area and the terminal I/F address 50 area. The dummy value 0 is similarly stored at address 1 since this is the position where the multi-frame synchronization pattern P1-F is inserted/extracted. 2
The area of the terminal I/F address 50 at number 8 from the address indicates the address of the terminal interface section 6 that accesses the terminal side transmission data bus 8 and the terminal side reception data bus 9, in this case, the first terminal], OO. CI-T 1 is 11!
1 to indicate that the input/output signals to the terminal-side transmission data bus 8 and the terminal-side reception data bus 9 are data signals. However, in the input/output signal type 5] area at address 8, 2 is written to instruct input/output of a control signal. Frame NO2O TSi (111a)
36 from address 3667+1 of the first memory 29 corresponding to
At address 67+8, according to the multiplexing example 120 in FIG.
Similarly to addresses 1 to 8 of the first memory 29 described above,
The dummy value O is set to address 3667+1, and CH20 indicating the 20th terminal 100 is set to 3667 in the terminal block/F address 50 area from addresses 3667+2 to 3667+8.
Values 1 and 2 are written in the input/output signal type 51 areas from address +2 to address 3667+7 and address 3667+8, respectively. Next, from address 193 n + 9 of the first memory 29 corresponding to TS2 (lilb) to 193 n +]
-6 address (n=o~19) has multiplexing example 12 in Figure 0.
According to 1, set the dummy value O to address 193n+9, 193
Terminal I from address n+1.0 to address 193n+16
The /F address 50 area contains C I (21-CH30 as 1), which is the address of the terminal interface unit 6 that accesses the terminal side transmission data bus 8 and the terminal side reception data bus 9
From address 93n+10 to address 193n+15 and 19
Values 1 and 2 are set in the input/output signal type 51 area at address 3 n + 16, respectively. CH21-CH30 is 21
The terminal interface section 6 corresponding to the 100th to 30th terminals is shown.

Next, in each address of the second memory 30 where information regarding multi-frame synchronization control is stored, this address corresponds to bit 0 to bit 192 of frame 112, and address 0 is the frame synchronization bit 150 position. In order to correspond to the CH
Since the terminal interface unit 6 of the I-CH 20 inputs and outputs signals at a bearer speed of 2:3 and 3.2'Kb/S, set the path number in the logical path number 52 area of all the above addresses. . ] In the logical path head indication 53 area from number 1 to number 8, the value 1 is set at address 1 to indicate that this is the head of this path, and the value 0 is set at the other addresses. In the multi-frame synchronization instruction 54 area, the value 1 is entered in addresses 1 to 8 to indicate that multi-frame synchronization is required. Further, the value 0 is entered in the synchronization pattern type 55 area, indicating the address of the fourth memory 38 where the multi-frame synchronization pattern x, 50 is stored. The value in the same ftA pattern type 55 has meaning only when the value of the multiframe synchronization instruction 54 is 1. Addresses 9 to 166 of the second memory 30 correspond to TS2 (111b) and are allocated to transmit the signal of the terminal 100 with a bearer speed of 6.4 Kb/s, and similarly to the above, each address within these addresses corresponds to TS2 (111b). The following values are set in the area. Logical path number 52
and the value 1 as the multi-frame synchronization indication 54.
The synchronization pattern type 55 is set to the value O, and the logical path head instruction 53 is set to the value 1 only at address 9, and the value O is set to the other addresses. FIG. 5 is a diagram showing a setting example of the third memory 31,
The address of the third memory 31, like the address of the first memory 29, corresponds to each bit of the multiframe. In this example, the signal of TSl, (illa), that is, the terminal I/F address 50 shown in FIG. Terminal side receiving data bus 9
Only the control signal is inverted with respect to the above signal polarity, and further CH2
The data signals and control signals input and output by the terminal interface unit 6 of CH1 to CH30 are set so that only the pig signal is inverted. Further, when the multi-frame synchronization of each logical path is lost or when there is a notification of frame synchronization loss from the line interface unit 3, a squelch instruction 57 for a signal received from the high-speed digital line 300 is sent from the CHI to the terminal interface unit 6 of the CH2O. The data signals and control signals to be input/output are transmitted on the terminal side reception bus 9 so that the data signal becomes logic "1" and the control signal becomes logic "O", and the terminal interface section 6 of CH21 to CH30.
The data and control signals are all logical It l II,
It is set so that

Next, the operation of each part of the TDMI shown in FIGS. 2 and 1-2 will be explained based on the setting information of the first memory 29, second memory 30, and third memory 31 shown in FIGS.

The contents of the first memory 29 are sequentially output to the address bus 12 using the value indicated by the frame/multi-frame counter 35 as address information. At this time, in synchronization with the output of the first memory 29, the output of the squelch selector 24, that is, the signal received from the high-speed digital line 300, is outputted to the terminal side reception data bus 9 via the terminal side reception data bus interface 20.

The terminal interface section 6 monitors the terminal j/F address 50 information on the address bus 12'', and the contents are as follows.
When the address matches the own terminal interface unit address, the reception data flowing on the terminal side reception data bus 9-1- at that time is taken in, and the data to be transmitted that was received from the terminal 100 is transferred to the terminal side transmission data bus 8'2. Output a signal or control signal within a certain period of time. Whether the signal output to the terminal-side transmission data bus 8 and the signal taken in from the terminal-side reception data bus 9 are data signals or control signals is determined by the input/output signal type 51 on the address bus 12 at that time. That is, when the input/output signal type 51 is 1, it is a data signal, and at this time, it is a control signal. Furthermore, when the terminal I/F address 50 on the address bus 12 is O, no terminal interface section 6 accesses the terminal side transmission data bus 8 and the terminal side reception pig bus 9, so the signal on the terminal side reception pig bus 9 is At that time, the multiplex converter 4 takes in the fixed value of the terminal side transmission pig bus 8, for example, logic 111 II when no terminal interface unit 6 accesses it.

The transmission and reception operations will be explained in more detail below. First, to explain the transmission operation, under the control of the frame/multiframe counter 35, the contents of address 0 are output from the first memory 29 to the address bus 12, and a logic II 11U signal is transmitted from the terminal side transmission data bus 8 to the terminal side. The signal is fetched via the data bus interface 21 and outputted to the synchronous bit selector 33 as it is because the signal polarity 56 of the third memory 31 is taken in by the EXOR 28. In this case, as shown in FIG. 5, the content of the signal polarity 56 is O. The synchronization pit selector 33 is designed to select the output of the multi-frame periodic pit 1 to generation circuit 32 when the contents of the logical path head instruction 53 and the multi-frame synchronization instruction 54 in the second memory 30 are both ]. , At this point, the output of EXOR 28 is selected, and the line side transmission data bus interface 23,
The data is sent to the line interface unit 3 via the line-side transmission data bus 1o. Next, when the contents of address 1 of the first memory 29 are output to the address bus 12, the synchronous pit selector 33
The operation up to this point is the same as above, but at this time the second memory 3
Logical path head instruction 53 at address 1 of 0 and multiframe 11
Since the contents of the synchronization instructions 54 are both "work", the synchronization pit selector 33 selects the output of the multi-frame synchronization bit generation circuit 32 and outputs it to the line interface section 3. At this time, the multi-frame synchronization bit generation circuit 32 uses the logical path number 52 of the second memory 30, the synchronization pattern type 55, the clock from the clock path 7, and the logical path number from the multi-frame control circuit 37, that is, the logical path number 1. Outputs path alarm bit A according to the multiframe synchronization state.

When the contents of addresses 2 to 8 of the first memory 27 are sequentially output to the address bus 12, a 6-bit data signal and a 1-bit control signal are output from the terminal interface section 6 of the CHI to the terminal side transmission data bus 8. , are taken in via the terminal-side transmission data bus interface 21 of the multiplexing converter 4. The captured 7-bit 1- signal is EXORed according to the signal polarity 56 at addresses 2 to 8 of the third memory 31.
28, the polarity is reversed, and according to the logical path head instruction 53 and multi-frame synchronization instruction 54 from addresses 2 to 8 of the second memory 30, the signal passes through the selector 33 to synchronization pin 1, and is further transferred to the line side transmission data bus interface 23. and is sent to the line interface unit 3 via the line-side transmission data bus 10.

Next, from address 193n+9 of the first memory 29, 193n
+ When the contents of address 16 (n-0 to 19) are sequentially output to address bus 12, address bus 1 is output in the same manner as above.
Terminal I/F address 50 and input/output signal type 5 on 2]-
Accordingly, a 6-bit data signal and a control signal bit are outputted from the terminal interface section 6 of the CI-I 30 from the CH 21 to the terminal side transmission data bus 8'2 and taken into the multiplex conversion section 4. In the multiplex conversion unit 4, the above-mentioned signal taken in from the terminal-side transmission data bus 8 is processed as follows in the same manner as described above, according to the information stored in the second memory 30, third memory 31, and fourth memory 38. .

When address 193 n + 9 of the first memory 29 is accessed, the signal taken in from the terminal-side transmission data bus 8 is connected to the logical path head instruction 53 at address 9 of the second memory 30 that is being accessed at this point. The information of the frame synchronization instruction 54 is discarded by the synchronization bit selector 33, and instead the output of the multi-frame synchronization bit generation circuit 32 is sent to the line interface section 3 via the line side transmission data bus interface 23 and the line side transmission data bus 10. It will be done.

P1 of the multi-frame synchronization pattern output at this time
According to the information of the synchronization pattern type 55 at address 9 of the second memory 30, the CCITT recommendation Also, when outputting the path alarm pin 1-A (inserted in the O-th frame) in this multi-frame synchronization pattern, the multi-frame control circuit According to the multi-frame synchronization state of the logical path (in this case, logical path 2) sent from 37, the pins 1 to 1 of logical LL OII or II 11+ are output.

Next, 1 from address 193 n + 10 of the first memory 29
When address 93n + 16 is being accessed, the data signals and control signals output by each terminal 100 that are taken in from the terminal-side transmission data bus 8 are transferred to address 193n + 10 of the third memory 31 that is being accessed at this point. 1 from address
Data signal 6 according to signal polarity 56 at address 93n+16
The polarity of all the bits is inverted by the EXOR 28, and the control signal bits maintain the same polarity as they were taken in. Similarly, the logical path head instruction 53 from addresses 10 to 16 of the second memory 30 being accessed at this point and the multiframe Synchronization instruction 5
4, the signal passes through the synchronization pit selector 33 and is sent to the line interface section 3 via the line-side transmission data bus interface 23 and the line-side transmission data bus 10.

The signal sent from the multiplex conversion unit 4 to the line interface unit 3 as described above is added with frame synchronization pins 1 to 150 at the beginning of each frame 112 in the line interface unit 3, and the frame shown in FIG. ], 12 and a multi-frame 111 configuration on the high-speed digital line 300.

The details of the receiving operation will be explained below.

The signals received via the high-speed digital line 300 and multiplexed as shown in FIG. The signal is sent to the multiplex converter 4 via the line-side receiving data bus 11 in synchronization with the frame pulse, multi-frame pulse, and clock inside the device supplied by the clock path 7. The multiplexing conversion unit 4 takes in the received signal sent from the line interface unit 3 via the line-side reception data bus interface 22, and then stores the received signal in the first memory 29 and the second memory 29.
The following processing is performed according to the information stored in the memory 30, the third memory 31, and the fourth memory 38, and the received signal is transferred to the terminal interface section 6 of the corresponding channel number via the terminal side reception data bus 9.

The received signal is output to the terminal side reception data bus 9 via the multi-frame alignment memory 25, frame selector 34, EXOR 27, squelch selector 24, terminal side reception data bus interface 20, and the delay circuit 36 and frame selector 34. , EXOR 27, squelch selector 24, and terminal side reception data bus interface 2°, it may be output to the terminal side reception data bus 9. The received signal passing through the former route is a signal that requires multi-frame synchronization and phasing, and the received signal passing through the latter route has a bearer speed of 64 Kb/s.
A signal having the above characteristics does not require multi-frame synchronization phase alignment.

Further, the received signal inputted from the line interface section 3 to the multiplex conversion section 4 is inputted to the multiframe control circuit 37 in order to perform control such as multiframe synchronization pattern detection of each logical path.

Next, as shown in FIG. 6, each multiplexed frame 11-
The case where each bit of 2 is input will be explained.

The O-th bit of the 1st frame to the 20th frame shown in FIG.
2, the signal is input to the delay circuit 36, the multi-frame alignment memory 25, and the multi-frame control circuit 37 in the multiplex conversion unit 4, respectively. Also,
At the same time, the frame synchronization state signal sent from the line interface section 3 is sent to the delay circuit 36, and this synchronization state signal and the multiframe synchronization state signal of the corresponding logical path output from the multiframe control circuit 37 are sent to the OR gate 40.
The signal is input to the multi-frame alignment unit 1 via the multi-frame alignment unit 25. The multi-frame control circuit 37 that received the received signal P1- controls the second memory 30 that is being accessed at this time.
Since the value of the logical path head instruction 53 at address 0 is O, this bit is ignored. The received signal H1- inputted to the delay circuit 36 is matched in phase with the output timing from the multi-frame alignment memory 25 by the delay circuit 36, and then inputted to the frame selector 34.

The frame selector 34 selectively outputs the output signal from the multi-frame alignment memory 25 and the output signal from the delay circuit 36 according to the contents of the multi-frame synchronization instruction 54 in the second memory 30. In this case, since the content of the multi-frame synchronization instruction 54 at address 0 of the second memory 30 shown in FIG. 4 is 0, the output signal from the delay circuit 36 is selected.

Next, the received signal among the output signals from the frame selector 34 is input to the EXOR 27, and at this point 193n+0 (n=o to 19) is read out from the third memory 31.
According to the value of the signal polarity 56 of the address (in the example shown in FIG. 5, it is O), the signal is input to the squelch selector 24 with the signal polarity as it was input to the EX○R 27. squelch selector 2
4, the signal indicating another synchronization state output from the frame selector 34 selects the output of the EXOR 27 when the synchronization state is normal, and selects the squelch of the third memory 31 when the synchronization state is abnormal. The instruction 57 is selected and output to the terminal side reception data bus 9 via the terminal side reception data bus interface 20. On the other hand, the input to the multi-frame alignment memory 25 is the multi-frame control circuit 3 of this multi-frame alignment memory 25.
Area indicated by 7, that is, 193n+O (n=o~19)
It is stored at the address and read out at the time specified by the multi-frame control circuit 37. ” When the signal No. 2 is output to the terminal-side receiving data bus 9, on the Atres bus ]-2,
Since the contents of address 0 of the first memory 29 are being output,
In the end, this received bit, ie, the frame synchronization bit 150, is not taken in by any terminal interface section 6 and is discarded.

Next, when the first bit of the 1st frame to the 20th frame shown in FIG. , the received signal is output from address 193n+1 of the third memory 29 to the multi-frame alignment memory 25 and the frame selector 3 while maintaining the polarity of the input signal.
4. EXOR27, squelch selector 24. It is output to the terminal side reception data bus 9 via the terminal side reception data bus interface 20, and is not taken in by any terminal interface section 6 and is discarded like the 0th bit above. At the same time, the received signal is input to the multiframe control circuit 37. The multi-frame control circuit 37 outputs the output information of address 1 of the second memory 30, the output information of the fourth memory 38 (in this case, the multi-room synchronization pattern of X, 50 is output), and the output of the frame/multi-frame counter 35. and the clock from the clock bus 7, this received signal is used to perform multi-frame synchronization control of the logical bus 1, and the multi-frame synchronization state of each logical path is output to the multi-frame synchronization bit generation circuit 32 and the frame selector 34.
Furthermore, frame Na 1 to 20 and intra-frame bit number O
~] Multi-frame alignment memory 2 consisting of 92
5 address generation and read/write control for this multi-frame alignment memory 25.

Next, the second frame of the first frame to the 20th frame shown in FIG.
When the eighth bit is input, the third memory 31
193n+2 which is the access address at that time to 19
Output at address 3 n + 8, address 2 ~ of second memory 30
Output at address 8, 1.93 n + 2 of first memory 29
The multi-frame control circuit 37 outputs addresses 193n+2 to 1.9 from the address 193n+8.
The data is sequentially written into the multiframe alignment memory 25 at address 3 n +88 along with the OR of the multiframe synchronization state and the frame synchronization state of the logical path 1- at that time.

On the other hand, the contents of the memory 25 before being written to the multi-frame alignment unit 1 at the above address are read out to the terminal-side reception data bus 9 at this point, and the received signal selected by the frame selector 34 and read out is The other synchronization state information is input as a selection control signal to the squelch selector 24. If the read synchronization status information indicates normal synchronization, the signal whose polarity has been converted by EXOR27 is (
In this case, the signals corresponding to the 2nd bit to the 7th bit 1- of the 1st frame to the 20th frame shown in FIG. 6 have the same polarity and correspond to the 8th bit of the 1st frame to the 20th frame The polarity of the signal bit is inverted), and is output to the terminal side reception data bus 9 via the squelch selector 24 and the terminal side reception data bus interface 20.

If the read synchronization state information indicates an abnormality, the squelch selector 24 selects the address 1.93 n +2 of the third memory 31 that is being accessed at this point.
The contents of the squelch instruction 57 at address 93n+8 are sequentially output to the terminal side reception data bus 9 via the terminal side reception data bus interface 20. Then, in synchronization with these output signals, address 193 n +2 of the first memory 29 ~
By outputting the contents of address 193n+8 to the address bus 12, the second to eighth bits of each frame are taken into the terminal interface section 6 of CI-I1 to CH2O, respectively, and the second to seventh bits of the inner cylinder The bit is transferred as a received data signal according to the speed of the terminal 100, and the eighth bit is output as a control signal.

Next, the 9th frame of the 1st frame to the 20th frame shown in FIG.
When Pitsu 1 ~ is input, the first frame ~ second frame described above is input.
In the 0th frame, similarly to when the O-th bit is input, this signal bit is used in the multiframe control circuit 37 for multiframe synchronization control of the logic path 2. Furthermore, when the 10th bit to 16th bit of the 1st frame to the 20th frame shown in FIG. Processed in the same way, addresses 10 to 10 of the second memory 30
Contents of address 16 and 193 n + 1 of third memory 31
．． , the contents of address 0-193n+16 and the contents of address 193n+]-0-193n+16 of the first memory 29
According to the contents of the address, at the same time the multiframe control circuit 37 writes to the multiframe alignment memory 25 at addresses 193n+10 to 193n+16,
If the data stored at the address before this write is read and the frame synchronization and multi-frame synchronization of the logical path 2 are normal via the frame selector 24 and EXOR 27, the The signal polarity of the 10th to 15th bits is inverted, and the 16th bit is
If the multi-frame synchronization of the logical path is lost, the 10th to 16th bits of the frame are all logical.]
, is changed to I+, is output to the terminal side reception data bus 9 via the squelch selector 24 and the terminal side reception data bus interface 20, and is taken into the terminal interface section 6 of CH21 to CH30, of which the first 6 The bit is output as a received data signal to the terminal O○, and the last bit is output as a control signal.

By performing the above two processes on other input/output signals, multiplexing using the octet multiplexing method is performed.

Furthermore, in the above explanation, the first frame of logical path 1 and the first frame of logical path 2 were explained as being the same frame, but it goes without saying that they may be different, and the operation regarding this is also the same as the operation described above. Therefore, the explanation will be omitted.

Next, the operation corresponding to the bit multiplexing method will be explained.

FIG. 7 shows 20 terminals 100 with a terminal speed of 2.4 Kb/S shown in FIG. ．． 8Kb/S terminal 1. OO' - 2 terminals and terminal speed], 1 terminal 100 of 2 Kb/S and TS of frame 112 (1)ll
It shows the contents of the first memory 29 and the second memory 30 when multiplexing into la and TS (2) lllb.

Addresses 193n+○ and ]93n+1 of the first memory 29 correspond to the positions of the frame synchronization bit 150 and the bit of the multi-frame synchronization pattern, respectively, so the input/output signal type 5] and the terminal I/F address 50 are For other areas where the dummy value is 0, the terminal I/F address is 5.
CHl as 0.

CH3, CI-16, etc. are also input/output signal type 5]
- as 2, 1, 1.・etc. are set to correspond to each bit of the multiframe that is multiplexed. 2nd memory 3
Since address 0 of 0 corresponds to the position of frame synchronization bit 150, the dummy value O is placed in the logical path number 52 area of addresses 1 to 16 with the same logical path number or - unlike the case of octet multiplexing described above. The logical path head indication 53 area with 1 at address 1 has the value 1 to indicate the head, and 2 to 1.
The logical path head indicator 53 at address 6 has the value O, and 1 to
The multiframe 11 synchronization instruction 54 at address 16 has a value of 1 indicating that it is necessary to synchronize the multiframe 11.
Finally, the synchronization pattern type 55 at addresses 1 to 16 is set to a value 0 indicating the address where the multi-frame synchronization pattern X, 50 of the fourth memory 38 is stored.

Although not shown in the figure, the third memory 31 contains signal polarity 56 for each signal and frame synchronization loss or corresponding logical path information, similar to the implied example of FIG. A squelch instruction 57 is set when multi-frame synchronization loss occurs.

First, the TDM4 transmission operation using the bit multiplexing method will be explained.

First memory 29 and second memory 3 set as above
0, the third memory 3J, and the fourth memory 38, each circuit of the multiplex converter 4 performs the same transmission operation as the one corresponding to the octet multiplexing method, and the data signals and control signals output from each terminal 100 are as shown in FIG. As shown in the figure, a frame synchronization bit 150 is inserted at the beginning of each frame, and C is inserted into the first bit of each frame, that is, the first bit of TS(1)lla.
A multi-frame synchronization pattern bit in accordance with CITT Recommendation 3 pip 1-~
The 8th bit is set to CI (3, CH6, CH9, CH) in order.
l5. Bits of the data signal of each terminal]OO outputted from the terminal interface unit 6 of CH18 are inserted, multiplexed, and sent out to the high-speed digital line 300.

Next, the TDM4 reception operation using the bit multiplexing method will be explained.

When the line interface unit 3 receives a received signal having the frame structure shown in FIG. After the frame synchronization phase of the received signal P1~ is adjusted by the frame synchronization bit]50, it is sent to the multiplex converter 4 via the line-side receive data bus]1.

Each circuit of the multiplex converter 4 also performs the first to second operations according to the contents set in the first memory 29, second memory 30, etc. shown in FIG.
Time slot h 11-1 a of 20th frame 112
When the first bit of 112 is received, the multi-frame control circuit 37 detects the multi-frame synchronization pattern of logical path 1, and detects the first frame (first frame) 112 for the logical path.
According to this multiframe control circuit 37, the received signal bits are OR status information of the current frame out-of-sync state and the multi-frame out-of-sync state of the logical path. At the same time, the data is written to or read from the multiframe alignment memory 25 designated by the multiframe control.

The received signal bits read out from the multi-frame alignment memory 25 and the received signal bits 1 to 1 that have passed through the delay circuit 36 are sent to the second memory 3 by the frame selector 34.
Either one is selected according to the multiframe synchronization instruction 54 of 0, and the frame asynchronization state information read from the multiframe alignment memory 25 and the frame asynchronization information that has passed through the delay circuit 36 are The second frame selector 34
Either one is selected according to the multiframe synchronization instruction 54 in the memory 30.

The received signal P1- of the selected output of the frame selector 34 is inverted in polarity by the EXOR 27 if necessary according to the signal polarity 56 of the third memory 3 at this time, and further inputted to the squelch selector 2/4, and the squelch selector 24 is At this time, the content of the squelch instruction 57 area of the third memory 31 is used as the other input, and either one is selected according to the out-of-synchronization information that is the selection output of the frame selector 34, and the output is sent via the terminal side reception data bus interface 20. The signal is then output to the terminal-side reception data bus 9, and this signal is taken into the corresponding terminal interface section 6 and sent to the terminal 100 as a reception data signal according to the contents of the first memory 29 that are output to the address bus 12 at this time. or transmitted or output as a control signal.

By performing the operations described in "--, it is possible to perform the multiplexing shown in FIG. 8 and the separation of the multiplexed frames shown in FIG. 8.

Hereinafter, we have explained the corresponding operation of the 2-octet multiplexing method and the bit multiplexing method, but it goes without saying that the multiplexing method can also be supported as if both methods are mixed. Furthermore, in the above explanation, the case where the multiframe synchronization pattern of CCITT Recommendation It goes without saying that the present invention is also applicable to cases where paths are used in a mixed manner.

Further, in the above embodiments, the case where the function for performing multiplexing conversion is provided in a separate module has been described, but the same applies to the case where this function is incorporated in a line interface unit or the like. Further, in the embodiment, the information for controlling multiplexing etc. is stored separately in a plurality of memories, but the same operation can be performed even if the information is stored in one memory.

〔Effect of the invention〕

As described above, according to the present invention, multiplexing/separation order information of signals such as transmitting/receiving pig signals and control signals of each terminal is stored in a memory that is accessed at the bit rate of the line and in a multiframe time period. Set information on the insertion/extraction position of synchronization pattern bits and information on which position of multiframe synchronization pattern bits are used to perform multiframe phase control of which signal in the signal received from the line, and Based on the information, data signals and control signals of each terminal are multiplexed and separated, so you can flexibly perform various types of multiplexing such as octet multiplexing, bit multiplexing, or mixed multiplexing of both by simply changing the contents of the memory mentioned above. This has the advantage that multiplexing methods can be adopted. Further, according to the present invention, various multi-frame synchronization patterns can be freely selected and utilized for each logical path based on the information similarly set in the memory, and
Since the signal polarity of the input/output signal of each terminal can be freely converted when inputting/outputting to the line or when synchronization such as frame synchronization occurs, the various multiplexing described above can be done flexibly. The division multiplexing device has the advantage that it can be easily interconnected with various time division multiplexing devices manufactured by various manufacturers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a time division multiplexing device according to an embodiment of the present invention, FIG. FIG. 4 is a layout diagram showing an example of the configuration of the first memory to fourth memory. FIG. FIG. 6 is a frame configuration diagram showing an example of a frame configuration when multiplexed according to the settings of the first memory and second memory shown in FIG. 4, FIG. 7 is a layout diagram showing an example of the setting contents of the first memory and second memory when corresponding to the pill multiplexing method of the present invention, and FIG. A frame configuration diagram showing an example of a frame configuration when multiplexed according to the memory settings, FIG. 9 is a block diagram showing an example of the configuration of a time division multiplexing device using a conventional octet multiplexing method, and FIG. 10 is an off-tera multiplexing system. Figure 1 is a block diagram showing an example of the configuration of a time division multiplexer using a conventional bit multiplexing system, and Figure 12 is a block diagram showing an example of a frame configuration in a conventional bit multiplexing system. FIG. 2 is a frame configuration diagram showing an example of a frame configuration in a multiplexing method. 1 is a time division multiplexer (TDM), 3 is a line interface section, 4 is a multiplex conversion section, 5 is a clock generation section (memory reading means), 6 is a terminal interface section, 7 is a clock path (to memory reading 11) means), 2/I is a squelch selector (squelch means), 25 is a multi-frame alignment]-memory (phase synchronization r, stage), 27 and 28 are EXO
R (polarity conversion means), 29 is the first memory, 30 is the second
31 is a third memory, 32 is a multi-frame synchronization bit generation circuit (synchronization pattern output means), 33 is a synchronization bit selector (synchronization pattern insertion means), and 34 is a frame 5
Room selector (phase synchronization switching means), 35 is a frame/
37 is a multi-frame control circuit (phase synchronization means), 38 is a fourth memory (synchronization pattern output means), 50 is a terminal I/F address, 51 is an input/output signal type, and 52 is a multi-frame counter (memory reading means); Logical path number, 5
3 is a logical path head instruction, 54 is a multi-frame synchronization instruction, 55 is a synchronization pattern type, 56 is a signal polarity, 57 is a squelch instruction, 1. OO is the terminal, 112 is the frame, 1
50 is frame synchronization pin 1~. 300 is a high-speed digital line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation Agent Patent attorney 1) Hiroshi Sawa (2 others) Figure 11

Claims (1)

[Claims] It has a terminal interface unit that inputs and outputs signals to and from the terminal, and takes in the signals received by this terminal interface unit, time-division multiplexes them, and sends them to a line such as a high-speed digital line, and time-division multiplexes the signals received from the line. In a time division multiplexing device that separates multiplexed signals and outputs the separated signals to the terminal via the terminal interface section, logical path number information that identifies a logical path configured as a set of multiple bits in a frame. , logical path head instruction information indicating the head of the logical path, multiframe synchronization instruction information indicating whether information in the logical path is multiframe multiplexed, and type of multiframe synchronization pattern used for the logical path. synchronization pattern type information to indicate, signal polarity information to indicate whether polarity conversion of the signal is required when inputting/outputting an internal signal handled internally to the line, and a squelch instruction to indicate the polarity of the squelch to be applied to the received signal received from the line. information,
Each piece of information consisting of terminal interface address information indicating the time point at which the terminal interface section sends and receives the internal signal, and input/output signal identification information indicating to the terminal interface section whether the internal signal is a data signal or a control signal is divided into a frame or multiframe. a memory for storing information corresponding to each bit in the memory, a memory reading means for reading out each piece of information in the memory at the bit rate of the line and in a multi-frame time period, and storing several types of multi-frame synchronization patterns, a synchronization pattern output means for outputting a specific multi-frame synchronization pattern specified by the synchronization pattern type information read from the memory; and a received signal received from the line according to the multi-frame synchronization instruction information read from the memory. a phase synchronization switching means for switching whether or not to perform multi-frame phase synchronization control; and when the phase synchronization switching means is switched to a side that performs multi-frame phase synchronization, the logical path number information read from the memory; phase synchronization means for performing multiframe synchronization control of a received signal received from the line using the logical path head instruction information and the specific multiframe synchronization pattern outputted by the synchronization pattern output means; synchronization pattern inserting means for inserting bits of the specific multi-frame synchronization pattern outputted by the synchronization pattern output means into a predetermined position of a transmission frame according to logical path number information and the logical path head instruction information; and reading from the memory. polarity conversion means for converting the polarity of the internal signal with respect to the corresponding bit of the signal on the line according to the signal polarity information; A time division multiplexing device comprising: squelch means for applying a squelch corresponding to each bit of a received signal received from the line according to the squelch instruction information read from the line.