JPH02165786A - Picture signal recorder or picture signal reproducing device - Google Patents

Abstract

PURPOSE:To correctly restore an original picture signal by alternately outputting two types of sampling data, which are respectively sampled and obtained in the rising timing and the falling timing of a sampling pulse using the same sampling clock, in each prescribed period. CONSTITUTION:Two types of sampling data to be outputted from A/D converters 6 and 7 are to be alternately outputted in each field period by a switch 8. Namely, from each A/D converter, the sampling data offset for a 1/2 picture element are outputted from every other line. In other words, the data are outputted from the A/D converter 6 for the first line, outputted from the A/D converter 7 for the second line, outputted from the A/D converter 6 again, and so forth. Thus, when resampling at reproducing time is to be executed, the same resampling clock can be used, accurate resampling can be executed, and the original picture signal can be restored correctly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal recording or reproducing apparatus for recording and reproducing image signals via a recording medium.

[Prior Art] Conventionally, there is a still video (hereinafter referred to as Sv) system as a recording and reproducing device for still image signals. This Sv system converts current TV signals into FM 2-inch magnetic disks.
It modulates and records. The image resolution achieved by this system is only comparable to that of current TV systems. However, in systems that handle still images, such as the Sv system, the final output may be printed out by a printer. In this case, the problem is that the image quality (particularly the resolution) is lower than that of silver halide photography.

On the other hand, recently HDTV (formerly GH Definition)
New TV systems are being considered, such as HDTV (HDTV), which has about 1,000 scanning lines, about twice as many as the current NTSC system, and a commensurate amount of horizontal signal bandwidth. have. Therefore, even in the Sv system, the 1000x
It has become essential to develop a still image recording and reproducing system with an image quality of about 1000 pixels (when a square screen is taken out).

In view of this situation, the Sv system has adopted a high-band (broadband) recording format for the recording medium. However, when viewed as an Sv system, while maintaining compatibility with conventional systems to a certain extent, We must aim for higher image quality.

Therefore, as a method to improve image quality while maintaining compatibility with conventional systems, the applicant proposed the CHSV method (C
Compatible High Definition
SV) can be considered.

An outline of the CHSV method will be described below.

First, a method for recording a luminance (Y) signal based on the CHSV method will be described. FIG. 3 shows sample points of the Y signal recorded based on the CHSV method. The sample points of the Y signal are sub-sampled, for example, at a sampling period T5 so as to be arranged offset as shown in the figure.

There are 650 sample points in a row (1300/2), and -
There are 500 (1000/2) in the row. And A 1 and A 2 in the figure.

The sample values included in the line .・
..., all sample values are recorded using a total of four tracks. Furthermore, recording is performed on each track in accordance with the format of the conventional Sv system.

Next, the reproduction method will be described. FIG. 4 shows a reproduction process based on the CHSV method. A signal reproduced by a magnetic head 1502 from a magnetic disk 1501 which is a recording medium is amplified by a reproduction amplifier 1503 and then input to an S■ reproduction process circuit 1504. . Here, separation of the luminance signal Y and color difference line sequential signal C, FM demodulation, de-emphasis, etc. are performed, and a reproduced Y signal and a reproduced C signal are output. Then, those two signals are γ-inverted in a γ-inverter 1506 or 1507, and L P F 15
0B or 1509, and then input to the image memory via an analog-to-digital (A/D) converter 1513 or 1514, respectively.
The sampling clocks in converters 1513 and 1514 are obtained by extracting a pilot signal that has been frequency multiplexed in advance from the signal reproduced from the magnetic disk 1501 by a band pass filter (BPF) 1505 during recording, and extracting the pilot signal from the signal reproduced from the magnetic disk 1501 by a synchronization separation circuit 1510. This clock is generated by the sampling clock generation circuits 1511 and 1512 using the synchronized and separated synchronization signals.

The above process is performed on four tracks on the magnetic disk 1501, and the A/D converters 151:l, 151
The sample data output from 4 is sent to the address generator 15.
17 and 1518 are stored in the address on the image memory 1515. and 1 image memory 1515
The image processing circuit 15 uses the sample data stored in
After performing interpolation processing etc. using 16, the high component of the Y signal (Y
, l), low frequency component of y signal (YL), color difference signal (Co,
Co) in a separated state, Y L, C*,
CB is supplied to the matrix circuit 1519 as shown in the figure,
After being converted into three primary color signals (Ri, , Gc, , BL),
The high frequency component (Y□) of the Y signal is added to adders 1520 and 1521.
．． 1522 and digital analog (D
/A) Converted to an analog signal by converters 1523, 1524, and 1525.

It is output as a KGB signal.

The above is the reproduction process, but the analog transmission of sample values performed in the primary CHSV system will now be described.

FIG. 5 shows a conceptual diagram of a CHSV transmission system.

As shown in the figure, the input analog signal is sampled at a period T. Then, the sample value is band-limited, FM modulated, and recorded on a magnetic disk. Then, the signal reproduced from the magnetic disk is FM demodulated, band-limited, resampled, and a sample value signal as shown in FIG. 5 is output.

In this analog transmission of sample values, it is a very important factor that the sampling pulse is transmitted without fluctuation in the time axis. FIG. 6 shows an explanatory diagram for explaining the importance of the time axis of the sampling pulse. Consider the case where a sample value sequence obtained by sampling one period T as shown in FIG. 6(a) is recorded and reproduced. The transmission line consisting of FM modulation/demodulation and electromagnetic conversion system exhibits LPF characteristics, and the transmission line output signal.

The signal becomes as shown in figure (b).If this signal is resampled with a sampling pulse that has the same period T as the input sampling pulse as shown in figure (C) and has the correct phase, the figure ( The original input sample value sequence can be restored as shown in d).

However, if the reproduced sampling pulse is out of phase as shown in FIG. 2(e), a sample value sequence as shown in FIG. 2(f) is output, and the sample value sequence is not reproduced correctly and ringing occurs. Furthermore, it goes without saying that the data will not be played back correctly even if the sampling period is different.

Therefore, during reproduction, a resampling pulse with the correct frequency (period) and correct phase is required. There is also one more condition for completely transmitting sample values. This is because the transmission path characteristics are linear phase (flat group delay) and the amplitude characteristics are symmetrical roll-off characteristics centered on the frequency f, (=I8).
The characteristics shown in the figure are required.

Incidentally, in order to generate the resampling clock pulse, the following configuration has already been proposed by the applicant of the present application. FIG. 8 shows the configuration of a resampling clock pulse generation circuit in the CHSV method. Phase Locked Loop
) circuit, and a phase correction circuit that corrects the phase of the resampled clock pulse. The PLL circuit divides a pilot signal containing a jitter component extracted from a reproduced signal into a VCO (voltage controlled oscillator) 83 and a frequency dividing circuit 85 to 1.
and a two-phase comparator 81, and outputs a resampling clock that follows jitter generated during reproduction by the PLL circuit. Further, the phase correction circuit 87 uses a variable delay line so that the phase reference point in the phase reference signal added to the image signal and recorded during recording matches the phase of the resampling clock which is the output of the PLL circuit. Correct the phase of the sampling clock.

This phase correction circuit 87 will be described in some detail. 9th
The configuration of the phase correction circuit is shown in the figure. In the comparator circuit 91 of the same figure, a reproduced Y signal, a synchronization signal (for example, a horizontal synchronization signal) synchronously separated from the reproduced Y signal, and a reproduced signal generated from the PLL circuit. A resampling clock that follows the generated jitter component is input. And this comparison circuit 9
1, the following processing is performed. The sample value obtained by the resampling clock output from the PLL circuit near the phase reference point of the phase reference signal added during recording in the input reproduced Y signal, and the sample value obtained by the resampling clock output from the PLL circuit when adding the phase reference signal during recording. Compare the amplitude center level of the defined phase reference signal. FIG. 1O is a diagram showing the positional relationship between the phase reference signal and the phase reference point. In order to extract sample values near this phase reference point, the falling edge of the pulse of the input horizontal synchronization signal is used as the reset point, and the sampling point that is considered to be closest to the phase reference point is included and the width is one sample. A gate pulse having a pulse interval is generated, and sampling is performed only when the gate pulse is ON. The timing is shown in FIG.

Compare the two signal levels obtained as described above,
The level difference is input as a phase control signal to the variable delay line 92, and the delay amount is changed to correct the phase of the resampling clock. Incidentally, the variable delay line 92 is 2, for example, C
The amount of delay is changed by changing the power supply voltage of an IC as a buffer of a MOS integrated circuit.

In this way, a resampling clock is generated in phase synchronization with the reproduced image signal to perform correct resampling.

[Problems to be Solved by the Invention] By the way, in the CHSV method described above, the sample point arrangement of the Y signal is offset by a local pixel for each line as shown in Figure 3, so the phase added at the time of recording is The reference signal is used for each line, that is, for each field, only for a period corresponding to the station pixel interval.

It must be added with a shift, and the PL on the playback side
The resampling clock output from the L circuit is a pulse with a duty of 5 oz, so in order to shift the rise of the resampling clock pulse by a station pixel, resampling is performed for each field as shown in Figure 2. By inverting the clock, the rise of the pulse must be shifted by the amount of the local pixel. At this time, in the configuration shown in FIG. 2, an inverter 22 is used to invert the resampling clock.

The inverter has a delay of about 10 to 20 μsec, and there is a time difference between the inverted output and the non-inverted output of the resampling clock that is switched and outputted from the switch 23 every field period, and the A/D converter 21 outputs the resampling clock every field period. In addition, if a buffer or the like having the same delay characteristics as the inverter 22 that forms the inverted output is used for the non-inverted output of the re-sampling clock, Although there are methods to reduce the time difference between the inverted output and the non-inverted output, it is still very difficult to eliminate the time difference due to variations in the elements that make up the inverter 22 and changes in environmental conditions such as temperature changes. . This also applies to the sampling clock that controls sampling during recording.

This invention was made in order to solve this problem, and an object of the present invention is to provide an image signal recording and reproducing device that can perform accurate sampling for two image signals and can correctly restore a single original image signal. shall be.

[Means for Solving the Problems] In order to achieve the above object, an image signal recording or reproducing apparatus of the present invention is an apparatus for recording or reproducing an image signal via a recording medium, and is capable of recording or reproducing an image signal via a recording medium. a sampling clock pulse generation means for generating a sampling clock pulse that is phase-synchronized with the input image signal; and an image signal that is input at the rising timing of the sampling clock pulse generated by the sampling clock pulse generation means. a first sampling means for sampling and outputting the image signal; a second sampling means for sampling and outputting the input image signal at the falling timing of the sampling clock pulse generated by the sampling clock pulse generation means; The apparatus is equipped with switching output means for switching and outputting the output of the first sampling means and the output of the second sampling means at predetermined intervals.

[Operation] With the above configuration, the input image signal can be accurately offset sampled every predetermined period.

[Embodiment] FIG. 1 is a block diagram showing a phase correction circuit in a resampling clock pulse generation circuit as the main configuration of an embodiment of the present invention. In addition, in FIG. 1, the ninth
Components similar to those in the figures are given the same numbers and detailed explanations will be omitted.

In FIG. 1, Y signal input terminal 1. Synchronous signal input terminal 2. The reproduced Y signal, synchronization signal, and resampling clock are respectively supplied from the resampling clock input terminal 3 to the phase correction circuit constituted by the comparison circuit 91 and variable delay line 92 shown in FIG. The phase of the resampling clock is corrected in the same manner as shown in the figure, and the resampling clock outputted from the phase correction circuit with correct frequency and phase is the A/D converter 1513 corresponding to the A/D converter 1513 in FIG. The signals are input to the D converter 6.7 without any time difference. In addition, the A/D converter 6.7 also receives the reproduced Y signal input from the Y signal input terminal 1.
The A/D converter 6 resamples the reproduced Y signal at the rising edge of the input resampling clock pulse, and the A/D converter 7 resamples the reproduced Y signal at the rising edge of the input resampling clock pulse. The configuration is such that the reproduced Y signal is resampled at the downstream timing. If this is done, the signal input to the A/D converter 6.7 will be the same.

Since the sampling clock pulse is a pulse with a duty of 50%, the A/D converter 6.7 outputs sampling data that are accurately shifted from each other by the amount of the collar pixel. Then, if the two types of sampling data output from the A/D converter 6.7 are alternately output for each field period by the switch 8, the C
In the HSV system, the 1st line is from the A/D converter 6, the 2nd line is from the A/D converter 7, the 3rd line is from the A/D converter 6 again, and the 4th line is from the A/D converter. :ff From converter 7... By configuring a configuration such as 0 or more in which sample data with sample points offset by wing pixels for each line is output, the replay during playback can be improved. The same resampling clock can be used when sampling, allowing accurate resampling during playback.

It should be noted that, of course, the above-mentioned embodiment is based on the assumption that sampling is performed with correct pixel offset during recording, but the input image signal can be sampled using a sampling clock formed using a similar configuration during recording. You can do it as well.

[Effects of the Invention] As explained above, according to the present invention, when sampling an image signal during recording or playback, the same sampling clock is used and the rising timing and falling timing of the sampling pulse are By performing sampling and alternately outputting the sampling data obtained by sampling at the two types of timing at predetermined intervals, accurate sampling can be performed for one image signal, and one original image signal can be correctly output. Can be restored.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of resampling clock generation for conventional station pixel offset sampling, and FIG. 3 is a block diagram showing the main configuration of an embodiment of the present invention.
A diagram showing the sample point arrangement of the Y signal in the SV method, Figure 4 is a diagram showing the configuration of the reproduction process in the CHSV method, Figure 5 is a system diagram of analog transmission of sample values, and Figure 6 is the sampling clock and output signal. Diagram showing the relationship between
The figure shows the transmission line LPF characteristics of analog transmission of sample values, Figure 8 is a block diagram of the resampling clock generation circuit in the CHSV method, Figure 9 is a block diagram of the phase correction circuit, and Figure 10 is a diagram of the image signal FIG. 11 is a diagram showing the positional relationship between the phase reference signal and the phase reference point, and FIG. 11 is a diagram showing the time relationship between the three-sided body position, the resampling clock pulse, and the sampling gate pulse during reproduction. In the figure. l: Y signal input terminal 2: Synchronous signal input terminal 3: Resampling clock input terminal 6.7: A/D: ff inverter 8: Switch 91: Comparison circuit 92: Variable delay line agent Patent attorney 1) Haru Kitatake Figure CH5V shows the δ'r72Y signal line, 9 arrangement figure Sunal damage 7702° J(21st image dimension>Ant ri°'C)less l(- axis 1st 2nd vL brightness) Figure Figure

Claims (1)

[Claims] An apparatus for recording or reproducing an image signal via a recording medium, the apparatus comprising: a sampling clock pulse generating means for inputting an image signal and generating a sampling clock pulse phase-synchronized with the input image signal; and the sampling clock a first sampling means for sampling and outputting an input image signal at the rising timing of the sampling clock pulse generated by the pulse generating means; and a first sampling means for sampling and outputting the input image signal at the falling timing of the sampling clock pulse generated by the sampling clock pulse generating means; , a second sampling means for sampling and outputting an input image signal, and a switching output means for switching and outputting the output of the first sampling means and the output of the second sampling means every predetermined period. An image signal recording or reproducing device characterized by comprising: