JPH02161555A - Data resending controlling system - Google Patents

Abstract

PURPOSE:To quickly transfer a packet to another processor by including two buffers for storing packets in a bus interface circuit, and at the time of receiving the information of reception impossibility, storing the succeeding packet in the other buffer and alternately sending the packets to a system bus. CONSTITUTION:A priority sending means 500 in a bus interface circuit 3 sends a packet stored in a transmission buffer 200 to a system bus 4. At the time of receiving packet reception impossibility information from a bus interface circuit 3' to which the packet transmitted a packet to be transmitted to a different bus interface circuit 3'' is stored in a transmission buffer 400 and the packets stored in the buffers 200, 400 are alternately sent to the bus 4. Thereby, the succeeding packet can be sent to another circuit 3'' in parallel with the resending of a packet to the circuit 3' and the packet can be quickly transferred to another processor 100.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an improvement in a data retransmission control method in a distributed processing device in which a plurality of processors transmit and receive packets via a bus interface circuit and a system bus. In order to make it possible to transfer subsequent packets addressed to other processors as quickly as possible even if the processor is In a distributed processing device that transmits and receives packets via a system bus, the bus interface circuit includes a first transmit buffer and a second transmit buffer that accumulate packets to be transmitted to the system bus, and a first transmit buffer that stores packets to be transmitted to the system bus. When the accumulated first packet is transmitted to the system bus and a first packet unreceivable notification returned from the bus interface circuit on the receiving side to which the first packet is transmitted is received,
The second packet to be transmitted to a bus interface circuit different from the destination bus interface circuit of the first packet is stored in the second transmission buffer, and the second packet and the first packet are alternately transmitted to the system bus. The transmitter is configured to include a transmitting means.

[Industrial application field]

The present invention relates to a distributed processing device, and more particularly to an improvement in a data retransmission control method in a distributed processing device in which a plurality of processors transmit and receive packets via a bus interface circuit and a system bus.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional distributed processing device,
FIG. 5 is a diagram illustrating the packet/node transmission process in FIG. 4.

4 and 5, - main processors (M
A bus interface circuit (Bl) 3 (main processor (MPR) 1) and a plurality of slave processors (SPR) 2 (each slave processor (SPR) is referred to as 2-1.2-2) The hash interface circuit (Bl) corresponding to the subprocessor (SPR) 2 is called 31
-1 and 2-2 corresponding bus interface circuit (
The BIs 3-21 and 3-22) are connected to the system bus 4, and packetized data is mutually transmitted and received via the system bus 4.

The right to use system bus 4 is granted by the system bus allocation circuit (S
BA) 5, and the system bus allocation circuit (SB
A) 5 sequentially allocates usage rights to the main processor (MPR) 1 and slave processor (SPR) 2 that request use of the system bus 4.

In addition, in FIG. 4, the slave processor (SPR) 2-1
Only the transmission-related configuration is shown for the bus interface circuit (Bl) 3-21 corresponding to the main processor (MP).
Bus interface circuit (Bl) 3- corresponding to R) 1
1 shows only the reception-related configuration, and the configuration of other bus interface circuits (Br) 3-22 is omitted.

Now, any slave processor (SPR) (for example 2-1) sends a request to transfer data d1 to the main processor (MPR) 1 via the control line 7 to the bus interface circuit (B).
I) When transmitted to 3-21, the bus interface circuit (
Bl) 3-21, a microprocessor (MP
U) 310 is a direct memory access control circuit (DM
C) 320 to control the slave processor (SPR) 2-1
Destination number a indicating main processor (MPR) 1 from .

Bucket buffer (PB) 33 via data line 6
Then, the transmission data d is transferred to the packet buffer (PB) via the data line 6 (step S1 in FIG. 5).
330 (step S2).

Next, the microprocessor (MPU) 310 adds the destination number a to the transmission data d, stored in the packet buffer (PB) 330, and assembles the packet pI (
In step S3), when the right to use the system bus 4 is assigned by the system bus allocation circuit (SBA) 5 (step S4), after being transmitted to the data bus 41 in the system bus 4 (step S5), the number of times n of packets p is transmitted is n. (Initial value is “0”) is updated by adding “1” (Step S6
).

The packet p+ sent to the data bus 41 is sent to the main processor (MPR) 1 and other slave processors (SPR).
Each bus interface circuit (Bl) 3 corresponding to 2-2
The received data is stored in the reception register (RCR) 31 of .

The address-number circuit (AMC) 32 in each bus interface circuit (BI) 3 holds the processor number assigned to the corresponding main processor (MPR) 1 or slave processor (SPR) 2, and (R
The destination number a1 given to the packet pI stored in CR) 31 is compared with each processor number.

In the bus interface circuit (Bl) 3-1 corresponding to the main processor (MPR) 1, an address-number circuit (
When the AMC) 32 detects a match between the two, it selects the free data buffer (DB) 34 and transfers it to the free data buffer (DB).
) 34, the direct memory access control circuit (DMC) 33 is activated and the reception register (RC
R) Remove the destination number a from the packets stored in 31 and select the remaining data d from the data buffer (D
B) 34, the transmission side bus interface circuit (B) is transferred via the status line 42 in the system bus 4.
I) A normal transfer completion notification signal r0 is returned to 3-21, but if the selection of an empty data buffer (DB) 34 ends unsuccessfully, the signal r0 is sent back to the sending side bus interface circuit (BI) 3 via the status line 42. -21, the data buffer full notification signal rb is returned.

In the bus interface circuit (Bl) 3-21,
Microprocessor (MPU) 310 connects status line 4
2, the notification signal (ro or rb) is received and analyzed (step S7), and if it is determined to be a normal transfer completion notification signal r0 (step S8), the packet buffer (PB) 330 is released (step S9). , prepare for sending the next packet.

On the other hand, if it is determined that the returned notification signal is the data buffer full notification signal rb (step S8), after confirming that the number of times n of packet pI transmission is less than a predetermined retransmission limit value N (step 510), step The retransmission of packet p1 after S4 is repeated.

Note that as a result of retransmission, if the number of transmissions n reaches the retransmission limit value N (step 510), the microprocessor (MP
U) 310 releases the packet buffer (PB) 330 (step S9) and ends the process of transmitting the packet I-pl.

[Problem to be solved by the invention]

As is clear from the above explanation, in a conventional distributed processing device, the bus interface circuit (BI) 3-1 on the receiving side receives data buffer blockage for the bucket )p+ sent by the bus interface circuit (B1) 3-21. When the notification signal r is returned, the retransmission of the packet p1 is repeated within the range of the retransmission limit value N until the normal transfer end notification signal r0 is returned from the receiving side bus interface circuit (Bl) 3-1. , and in the meantime, the next paga l-1)2
There was also the problem that the transfer was not possible and the transfer was kept on standby.

Note that a plurality of slave processors (SPR) 2 are connected to the main processor (
When attempting to transfer packets to MPR) 1 at the same time and repeating retransmission after receiving the data buffer full notification signal rb, the data buffer (DB) 34 becomes congested and the normal transfer completion notification is not sent for any length of time. The signal r0 cannot be received and retransmission is repeated.

In such a state, if the data buffer (DB) 34 is connected to another bus interface circuit (BI) (
For example, even after the next bucket (pg) transferred to 3-22), the transmission timing will be significantly delayed.

SUMMARY OF THE INVENTION An object of the present invention is to enable subsequent packets addressed to other processors to be transferred as early as possible even if retransmission of a packet addressed to one processor is requested.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 100 is a processor, 3.3.3'' is a bus interface circuit, and 4 is a system bus, which constitute a distributed processing device.

200 and 400 are first and second transmission buffers provided within the bus interface circuit 3 according to the present invention.

500 is a priority transmission means provided in the bus interface circuit 3 according to the present invention.

[Effect]

The priority transmission means 500 transmits the first packet accumulated in the first transmission buffer 200 to the system bus 4, and prevents reception of the first packet returned from the destination bus interface circuit 3° of the first packet. When the notification is received, the first packet transmission destination bus interface circuit 3
A second packet to be transmitted to a different bus interface circuit 3'' is stored in a second transmission buffer 500, and the second packet and the first packet are alternately transmitted to the system bus 4.

Therefore, even if a packet is retransmitted, subsequent packets transmitted to other bus interface circuits are
It becomes possible to transmit the packet in parallel with the retransmission of the previous packet, and the transmission delay of subsequent packets can be significantly improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a distributed processing apparatus according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating the bucket transmission process in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the processor 100 in FIG. 1 includes a main processor (MPR) 1 and a slave processor (MPR) 1.
A bus interface circuit (BI) 3 corresponding to the slave processor (SPR) 2 is shown as a bus interface circuit (BI) 3 on the sending side in FIG.
Bus interface circuit (BI) corresponding to MPR) 1
3 is shown as a receiving side bus interface circuit 3,
The hash interface circuit (Bl) 3 corresponding to the slave processor (SPR) 2 includes a packet buffer (PB) 330 and a priority packet buffer (PPB) as the first transmission buffer 200 and second transmission buffer 400 in FIG. 331 is provided, and a priority transmission control unit (PS) is provided as priority transmission means-6-00 in FIG.
C), 311 is provided within the microprocessor (MPU) 310.

In FIGS. 2 and 3, an arbitrary slave processor (S
PR) (for example, 2-2), the main processor (MPR) 1
When a request to transfer data d is generated, the corresponding bus interface circuit (Bl) 3-21 transfers the data d to the fifth
Packet I)+ (hereinafter referred to as previous packet p+) is assembled by the same process as steps S1 to S3 in the figure, and when the right to use the system bus 4 is granted by the system bus allocation circuit (SBA) 5 (step S4)
, the previous packet 9+ is sent to the data bus 41 to update the number of transmissions n (steps S5 and S6 in FIG. 5), and an empty data buffer ( DB)3
4 is successful and a normal transfer end notification signal r0 is returned via the status line 42 (steps S7 and S8 in FIG. 5), the bucket buffer (PB) 3
30 (step S9 in Fig. 5), the next packet (
Prepare for the transmission of the next packet pz (hereinafter referred to as the next packet pz).

7. Receiving side bus interface D'1 (BI) 3-1
If the selection of the free data buffer (DB) 34 is unsuccessful and the data buffer completion notification signal r is returned via the status line 42 (step S8 in FIG. 5), the sending side bus Interface session 1 (B
l) Microprocessor (MPU) 310 in 3-21
starts the priority transmission control unit (PSC) 311.

The activated priority transmission control unit (PSC) 311 transfers the destination number a2 of the next packet p2 from the corresponding slave processor (SPR) 2-1 to the priority packet by controlling the die reflex I/memory access control circuit (DMC) 320. Buffer (
PPB) 331 and analyze it. Figure 3 Step 5
ll), if it is found that the destination number a1 is the same as the destination number a1 of the previous packet p1 (step 512), the next packet p2
Even if it is transmitted with priority, the bus interface circuit (Bl) 3- on the receiving side is similar to the previous packet 1)+.
Since the data buffer based notification signal r is returned from 1, priority transmission of the next Paqueso)pz is not performed, and Paqueso)pI
li! that the number of transmissions n is less than a predetermined retransmission limit value N. After approval (step 513), step S4
Subsequent retransmission of the previous packet p1 is repeated.

On the other hand, if the result of the analysis of the destination number a2u of the next packet pz (step 5ll) is found to be different from the destination number a of the previous packet pI (step 512), the priority transmission control unit (PSC) 311 ) pz is determined to be worth sending with priority, and the slave processor (SPR) 2-1
After controlling the direct memory access control circuit (DMC) 320 to transfer the next transmission data d2 to the priority packet buffer (PPB) 331 (step 51
4) Assemble the next packet p2 with the destination number a2 that has already been transferred to the priority packet buffer (PPB) 331 (step 515), and transmit it to the data bus 41 using the same process as the previous packet p (step 516). When it is determined that the normal transfer end notification signal r0 has been returned from the interface circuit (Bl) (for example, 3-22) via the status line 42 (step 517), the priority packet buffer (PPB) 331 is released and the subsequent packets are After preparing for priority transmission (step 518), step S
By executing steps S4 and subsequent steps in FIG. 5 again via Step 13, the previous packet p is retransmitted.

On the other hand, a data buffer base notification signal r is sent via the status line 42 from the bus interface circuit (BI) 3-22 on the receiving side of the next packet p2.

If it is determined that the packet buffer (P
B) Retransmit the previous packet p+ stored in 330 to the data bus 41 using the same process as described above.Step 51
9) As a result of retransmission, the receiving side bus interface circuit (
If the normal transfer end notification signal r0 is returned from Bl) 3-22 (step 520), or if the data buffer based notification signal r5 is returned from the bus interface circuit (Bl) 3-22 (step 520), and When the number of transmissions n1 of the previous packet p+ reaches the retransmission limit value N (step 521), the packet buffer (PB) 33
0 is released, and thereafter the priority packet buffer (PPB) 331 that stores the packet pz is treated as the packet buffer (PB) 330, and the released packet buffer (PB) 330 is used as the priority packet buffer (PPB) 331 instead. After replacing the packet buffer (PB) 3 (step 522), by executing steps S4 and subsequent steps in FIG. 5 again, a new packet buffer (PB) 3
In addition to repeating the transmission of the next packet pz stored in 30, priority transmission of the subsequent packet is attempted.

As is clear from the above explanation, according to the present embodiment, when the previous bucket) pt is in the retransmission state, the previous bucket) pI
Since it is possible to transmit the next packet pz and subsequent packets alternately with the retransmission of pI, it is possible to prevent transmission delays after the next bucket pg due to retransmission of the previous bucket pI.

It should be noted that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the priority transmission means 500 is not limited to the priority transmission control section (PSC) 311 shown in the figure, and may include many others. Although the following modifications are considered, the effects of the present invention remain unchanged in either case.

It goes without saying that the configuration of the distributed processing device to which the present invention is applied is not limited to that shown in the drawings.

〔Effect of the invention〕

As described above, according to the present invention, in the distributed processing device, even when a packet becomes retransmitted, subsequent packets to be transmitted to other bus interface circuits can be transmitted in parallel with the retransmission of the packet, Packet transmission delay can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a distributed processing device according to an embodiment of the present invention, FIG. 3 is a diagram illustrating the packet transmission process in FIG. 2, and FIG. FIG. 5 is a diagram showing an example of a conventional distributed processing device, and is a diagram illustrating the packet transmission process in FIG. 4. In the figure, 1 is the main processor (MPR), 2 is the slave processor (SPR), 3.3', 3f' are the bus interface circuits (Bl), 4 is the system bus, 5 is the system bus allocation circuit (SBA), 6 340 is a direct memory access control circuit (DMC), 34 is a data buffer (DB), 35 and 310 are microprocessors (MPU), 100 is a processor, 200 is a first transmission buffer, 311 is a priority transmission control unit ( P.S.
C), 330 is the packet buffer (PB), 331 is the priority buffer sofa (PPB), and 400 is the second invention's magic map. painful process chart

Claims (1)

[Scope of Claims] A plurality of processors (100) are connected to a system bus (4) via bus interface circuits (3, 3', 3''), and each of the processors (100) is connected to each of the bus interface circuits. (3) and a distributed processing device that transmits and receives packets via a system bus (4), the bus interface circuit (3) including a first transmission buffer that stores packets to be transmitted to the system bus (4). (200) and a second transmission buffer (400), transmitting the first packet accumulated in the first transmission buffer (200) to the system bus (4), and transmitting the first packet to the transmission destination bus. When receiving the notification that the first packet cannot be received returned from the interface circuit (3'), the bus interface circuit (3') different from the destination bus interface circuit (3') of the first packet
priority transmission means (500) for storing second packets to be transmitted to the system bus (4) in the second transmission buffer (400) and alternately transmitting the second packets and the first packets to the system bus (4); ) is provided.