JPH0215957B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a decoder circuit, particularly a ROM (read only
This invention relates to a row address decoder circuit for selecting a word line of a memory.

(2) Technical background To read data stored in a ROM, it is first necessary to select one word line specified by a row address. A row address decoder (hereinafter also simply referred to as a decoder) performs this. This decoder mainly consists of a group of series-connected transistors that function as NAND gates, and each bit A ₀ , A ₁ . . . A _o of the row address is applied to the control gate of each transistor. However, with such a configuration, for example, in a decoder that selects 128 (=2 ⁷ ) word lines, seven series-connected transistors must be provided for each word line, which requires high integration. It will be difficult to achieve this goal.

For this purpose, a decoder provided with a so-called pre-decoding section has been proposed. By using this predecoding section, the number of transistors in the NAND gate transistor group can be reduced. In other words, the pre-decode section converts the row address consisting of A ₀ , A ₁ , A _o bits into A ₀ , A ₁ , A ₂ ,
A ₃ , A ₄ , A ₅ ... (. represents AND logic) are converted into outputs and applied to the control gate of the transistor in the form of a combination of these, so the number of transistors can be reduced by the amount of the combination. can.
The present invention refers to a decoder having such a pre-decoding section and a main decoding section connected thereto.

(3) Prior Art and Problems FIG. 1 is a circuit diagram showing the configuration of a general row address decoder including a pre-decoding section and a main decoding section. However, only the basic configuration inside the decoder is extracted and drawn. A ₀ , A ₁ , A ₂ ...A ₇ are the bits of the row address mentioned above, and (A ₀ ,
There are 128 combinations from _A1 , _A2 ... _A7 ) to ( ₀ , ₁ , ₂ ... ₇ ). In the figure, numeral 11 is a pre-decoding section, and 12 is a main decoding section, which are connected to one word line WL via an inverter 13. The example in this figure shows a case where the word line WL is selected when all of A ₀ to A ₇ are "H" (high). For other word lines, for example (A ₀ , ₁ ,
_A2 … ₇ ) etc. When all A ₀ to _{A 7} are “H”, the drive transistors 14, 15, 16, 17 connected in series in the main decoding section 12
are all turned on, and the potential of node _N1 is “L”
(low), and the word line is connected via the inverter 13.
Raise the potential of WL (“H”) to set it to the selected state.
(The transistors marked with a circle in the figure are P-channel transistors, and the others are N-channel transistors.) As shown in this figure, drive transistors 14 to 1
Since the transistor 7 inputs the combinations of A ₀ and A ₁ , A ₂ and A ₃ . . . to its control gate, the number of transistors constituting the transistors 14 to 17 is reduced. Such an AND combination A ₀・
The predecoding section 11 generates A ₁ , A ₂ , A _{3 .} . . , and has a configuration that employs so-called AND logic. Note that the configuration that uses AND logic for A ₄ , A ₅ , A ₆ , and A ₇ is also completely the same, so a description thereof will be omitted.

By the way, to conclude, such a conventional decoder has two problems: firstly, the word line is incorrectly selected, and secondly, the number of transistors used is not yet sufficiently reduced. This second problem is an inevitable result of adopting such a configuration, and cannot be solved unless the circuit configuration is basically changed. On the other hand, the first problem arises for the following reason. Whether the word line WL is selected or not depends on the first
This is determined depending on whether the node _N1 in the figure becomes completely "L" or completely "H". However, such a complete “L” or “H” is a node.
It cannot be guaranteed that it will appear in N ₁ . This is due to the parasitic capacitance that exists in the nodes N ₂ , N ₃ , and N ₄ , and the potential of the node N ₁ changes depending on whether or not there is charge accumulated in the parasitic capacitance. . For example, while the illustrated word line WL is unselected (i.e., node _N1 should be at "H"), nodes _N2 , _N3 , and _N4 are brought to "L" by a previous memory access. Assuming that the lower three transistors 15, 16, and 17 of the series-connected transistor 14 are on,
Next, before the address changes, clock CK falls and transistor 18 turns on to precharge node _N1 . After that, in response to the switching of addresses _A0 to _A7 , if only transistor 17 is turned on and the other transistors 14, 15, and 16 are turned off, nodes _N2 , _N3 , and _N4 are at "L". Due to the heat, the charge accumulated in node N ₁ is transferred to the node
It is released to N ₂ , N ₃ , and N ₄ , and the level of node N ₁ is lowered, making it impossible to maintain a perfect "H" level.
In this case, in the worst case, there is a possibility that the node _N1 is led to the "L" side and the word line WL that should be unselected is selected via the inverter 13.

(4) Object of the invention The object of the present invention is to propose a decoder circuit that can solve the above problems.

(5) Structure of the Invention In accordance with the above object, the present invention comprises a common drive transistor controlled by one bit in a group of bits constituting a row address, and a common drive transistor connected to this and based on all remaining bits in the group of bits. and a drive transistor selected in series, and turn off the common drive transistor (connected to ground) and turn on all gates constituting the drive transistor every falling period of the clock that drives the row address decoder. This is characterized in that so-called pre-charging is performed on all nodes on the path through which each word line is to be driven.

More specifically, the decoder circuit of the present invention includes a predecode section, a main decode section, and a clock generation circuit that generates a clock signal for a predetermined period when switching addresses. m) A first pre-decode signal that outputs a first pre-decode signal in accordance with a combination of bit (n, m are natural numbers) address signals, and fixes the first pre-decode signal to a constant logic level in accordance with the clock signal. A second predecode signal is output in response to a combination of one group of logic gates and an address signal of m bits other than the (n-m) bits, and the second predecode signal is output in response to the clock signal. a second logic gate that fixes the predecode signal to a fixed logic level different from the first predecode signal; the main decode section includes a load transistor connected to the first power supply and controlled by the clock signal; , a drive transistor connected to the load transistor and controlled by the first predecode signal; and a common drive transistor connected between the drive transistor and a second power supply and controlled by the second predecode signal. and a connection point between the load transistor and the drive transistor is an output terminal, and the output terminal and the connection point between the drive transistor and the common drive transistor are precharged by generation of the clock signal. It is something.

Further, the decoder circuit of the present invention is characterized in that a plurality of the drive transistors are connected in series and in common to the common drive transistor, and a plurality of drive transistors are commonly connected in series to one drive transistor. It is characterized by:

(6) Examples of the invention The present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of a row address decoder according to the present invention. In this figure,
21 and 22 correspond to the pre-decoding section 11 and main decoding section 12 in FIG. 1, respectively. CG is a clock generation circuit. Word line WL from inverter 13 becomes one word line within memory array MA. In memory array MA, memory cells MC are provided at the intersections of word lines WL and bit lines BL. First, the predecoding section 21
Regarding this, the gate configuration of the predecoding section 11 shown in FIG. 1 differs in the following points. In other words, it not only uses simple AND logic, but also uses NOR logic when the clock CK is inverted. Figure 3 shows the pre-decoding section 2 in Figure 2.
1 is an equivalent logic diagram of the top stage 21-1 in FIG.
However, the stage 21-2 arranged below also has exactly the same equivalent logic. As shown in Figure 3, the AND output of address bits _A0 and _A1 is
The inverted clock and NOR are taken and applied to the main decoding section 22 via the next stage inverter.

Returning to FIG. 2, the predecode section 21 is further provided with a section 21' that performs a NOR logic between address bit _A6 and an inverted clock, and this is also different from the predecode section 11 of FIG. The NOR output of address bit _A6 and the inverted clock is applied to common drive transistor 22-4, which will be described below, as its control gate input. Next, regarding the main decoding section 22, its configuration is quite different from that of the main decoding section 12 shown in FIG. For example, when the main decoder 22 receives as input a row address of 128 words, that is, a 7-bit structure consisting of address bits _A0 to _A6 ,
A plurality of drive transistors 22-1 in the first stage, each having control gate inputs _{A0.A1 , 0.A1 , A0.1 and 0.1 ,} and address bits _A2 and _A3.
Similar combinations (A ₂・A ₃ , ₂・A ₃ ,
a plurality of drive transistors 22-2 in the second stage, each having a control gate input of _A2.3 , _2.3 ), and a _third stage having a similar combination of address bits _{A4 and A5} as each control gate input. A plurality of drive transistors 22-3 and the aforementioned common drive transistor 22-4 are stacked in multiple stages.
The structure as a whole forms an inverted pyramid. Fourth
This figure is a circuit diagram clearly showing that the main decoding section 22 of FIG. 2 has an inverted pyramid structure as a whole. The reason for this inverted pyramid structure is that a single common drive transistor 22-4 applies predetermined control (described later) to all drive transistors between the load transistor 22-C and the common drive transistor 22-4. This is because it is necessary, and on the other hand, the first stage drive transistor 22-
1 are collectively handled in common and in series by one transistor among the second stage drive transistors 22-2, and further, the second stage drive transistors 22-2 are collectively handled by one transistor in the second stage drive transistors 22-2. This is because one transistor among the third-stage drive transistors 22-3 takes charge in common, and the entire drive transistor 22-4 takes charge in common and in series. ,
It becomes possible to considerably reduce the number of transistors that have to be used. The inverted pyramid structure in FIG. 4 is shown for a multi-stage drive transistor with address bit _A6 in FIG. 2 as the control gate input and the common drive transistor 22-4 as the apex. Although not shown, the inverted address bit ₆ of address bit A ₆
There is also a multi-stage drive transistor in which the common drive transistor (the transistor corresponding to 22-4) is the apex with the control gate input being . In any case, according to this example, 128 word lines can be driven, and from the inverted pyramid structure of FIG. 4, 64 word lines can be driven. Each word line is taken out by the p-channel load transistor (clock CK) in the first stage drive transistor 22-1 in FIG.
(on/off) indicated by WL below.

The decoder circuit shown in FIG. 2 has the following characteristics: First, every time the clock CK falls (“L”), that is, every time the address change of the row address is performed,
Only the common drive transistor 22-4 is turned off, and the drive transistors 22-1, 22-2, 22-3 and the p-channel transistor 22-C are turned on to uniformly hold all nodes _N1 to _N4 at "H". be. In the configuration of FIG. 1, it is not certain what logic level the nodes N ₂ to _{N 4} are held at, and for this reason, the logic level of the node N ₁ fluctuates.
This resulted in incorrect selection. However, in the configuration shown in FIG. 2, all of the first-stage drive transistors 22-1 to third-stage drive transistors 22-3 are open during a predetermined time when switching addresses, and only the lowest-stage common drive transistor 22-4 is closed. and p
- The channel clock gate 22-C is fully opened, and all nodes _N1 to _N4 are uniformly raised to the "H" level. This is done immediately before each word line selection, regardless of the type of address used during the previous access. As a result, any unselected word line is reliably unselected (“L”). When any one word line is selected, the first
One gate connected to the selected word line in the stage drive transistor 22-1, and each second and third stage drive transistor 2 related to the selected row address.
One transistor in transistors 2-2 and 22-3 and the common drive transistor 22-4 are turned on, ensuring that node _N1 and nodes _N2 to _N4 of the word line are pulled to the logic "L" level.

Looking at the predecoding section 21 in FIG. 2,
Regardless of the row address, all signal lines _L1 input from the pre-decoding section 21 to the main decoding section 22 are input at the timing when the clock CK falls due to the inverted clock introduced into the pre-decoding section 21. , becomes logic "H". However, at that timing, only the signal line _L2 becomes logic "L".

FIG. 5 is a waveform diagram for explaining an example of the operation of the decoder circuit of FIG. 2. In this figure, columns (1) to (5) are the clock CK, row address A, and signal line, respectively.
The level for _L1 , the level for signal line _L2 , and the level for word line WL are shown, respectively. When clock CK falls at time t1 ((1)
column) becomes "H" and the level on the signal line _L1 is set to "H" (column (3)) (this applies to all signal lines _L1 ). At this time, an address change occurs in the row address in synchronization with the switching of the clock CK, and the row address A is supplied (column (2)).
When the clock CK falls, the inverted clock ("H") acts on the circuit 21' (NAND) and brings the signal line _L2 to the "L" level (column (4)). Thus, the period from time t1 to t2 is
This is a so-called pre-charge period for _N1 to _N4 . After that, when looking at the selected word line WL based on the row address A, the clock
At the rising edge of CK, address bit _A6 and other applicable bits _A5 to _A0 are selected, the level of signal line _L2 is inverted to "H" (column (4)), and the level of signal line _L1 related to the selection is inverted to "H" (column (4)). The level remains “H” (column (3)). Thus, the node related to the selected word line WL
_N1 and nodes _N2 to _N4 are pulled down to the "L" level. This level reduction is a grand
This is done in the form of charge discharge to GND, so after a slight time delay (Δt), the selected word line WL
The level of is inverted to "H" and becomes a selected state.

Next, suppose that the clock CK falls with an address irregular period a after time t3, and the next address change occurs. Similarly, during this period, the pre-charge described above is performed. This time, it is assumed that the row address A deselects the word line. During this precharge period, the signal line _L2 becomes "L", the common drive transistor 22-4 is turned off, and the load transistor 22-C is turned on by the clock CK, so that the nodes _N1 ,
N ₂ , N ₃ , N ₄ all become “H”, and the word line WL
becomes “L”. Since the signal line _L1 is no longer selected at the current row address A, it switches to the "L" level after time t4 (column (3)). Therefore, the node _N1 of the word line remains at "H" level. Therefore, the level of the word line remains "L" and becomes unselected (column (5)).

(7) Effects of the Invention As explained above, according to the present invention, a decoder circuit that can eliminate erroneous selection and use fewer transistors than before is realized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a general decoder circuit including a pre-decoding section and a main decoding section, FIG. 2 is a circuit diagram showing an embodiment of the decoder circuit based on the present invention, and FIG. An equivalent logic diagram of the uppermost stage 21-1 in the predecoding unit 21 of FIG. 2,
4 is a circuit diagram that clearly shows that the main decoding section 22 of FIG. 2 has an inverted pyramid structure as a whole, and FIG. 5 is a waveform diagram for explaining an example of the operation of the decoder circuit of FIG. 2. . 13... Inverter, 21... Pre-decoding section, 22... Main decoding section, 22-1, 22
-2, 22-3...drive transistor, 22-4
...Common drive transistor, 22-C...Load transistor, CG...Clock generation circuit, MC...
...Memory cell, A ₀ , A ₁ ... A ₆ ... Row address bit.

Claims (1)

[Claims] 1. A pre-decoding section, a main decoding section, and a clock generation circuit that generates a clock signal for a predetermined period when switching addresses; a first predecode signal that outputs a first predecode signal in response to a combination of address signals (m is a natural number), and fixes the first predecode signal to a constant logic level in response to the clock signal;
outputs a second predecode signal in response to a combination of a group of logic gates and an address signal of m bits other than the (n-m) bits, and outputs the second predecode signal in response to the clock signal. a second logic gate fixed at a constant logic level different from the first predecode signal, and the main decode section includes a load transistor connected to the first power supply and controlled by the clock signal. , a drive transistor connected to the load transistor and controlled by the first predecode signal; and a common drive transistor connected between the drive transistor and a second power supply and controlled by the second predecode signal. and a connection point between the load transistor and the drive transistor is an output terminal, and the output terminal and the connection point between the drive transistor and the common drive transistor are precharged by generation of the clock signal. decoder circuit. 2. The decoder circuit according to claim 1, wherein a plurality of said drive transistors are commonly connected in series to said common drive transistor. 3. The decoder circuit according to claim 2, wherein a plurality of drive transistors are commonly connected in series to one drive transistor.