JPH02158136A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To make capacity Cbc between a base and a collector and emitter resistance Re small in view of structure by forming the mask to decide an emitter region and an emitter electrode by self-alignment of the mask to decide a collector contact region and a collector region and the mask to decide an external base region. CONSTITUTION:A collector contact layer 22, which contains an n-type impurity, a collector layer 23, a base layer 24, which contains a p-type impurity, an emitter layer 25, and an emitter contact layer 26 are grown in order by film growth on a semiinsulating substrate 21. And on this emitter contact layer 26, a mask 41 is formed and oxygen ions are implanted deep from the surface so as to form an insulating region 31. Subsequently, an external base layer 32 is formed, and a mask 42 is formed slenderly crossing the mask 41 right angles, and the not-covered part is removed by dry etching. Subsequently, oxygen ions are implanted shallowly to the vicinity of the base layer 24 so as to form an insulating region 33. Furthermore, the mask 42 is removed, and with the residual part of the mask 41 as a mask 43 the vicinities of the emitter layer 25 and the emitter contact layer 26 are removed by wet etching. Hereby, Cbc, which greatly contributes to high frequency advancement, and Re can be minimized in structure.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing bipolar transistors.

Conventional technology The trend in semiconductor devices is toward higher density integration and faster speeds.

High frequency. In bipolar transistors, one of the basic performance factors when considering higher frequencies is the maximum oscillation frequency f aax. fmax is generally expressed by the following formula.

(f wax)” -fT/ (8gRbCbc)・
(1) Here, rT is the maximum cutoff frequency, and includes a term related to the emitter resistance Re, and as Re increases, fT decreases. Rb is a base resistance, and Cbc is a base-collector capacitance. Therefore, reduction of Cbc is necessary for increasing the frequency in bipolar transistors.

Recently, heterojunction bipolar transistors using gallium arsenide, which has faster electron mobility than silicon, have been attracting attention as high-frequency devices. In a heterojunction bipolar transistor, a semiconductor having a larger forbidden band width than a base semiconductor is used as an emitter, and a Teheterojunction is formed between the emitter and the base. This reduces carrier injection from the base side to the emitter side, so there is an advantage that a sufficient current amplification factor can be obtained even if the base is made thin and highly concentrated for higher frequencies. Conventional heterojunction bipolar transistors reduce Cbc by insulating the collector layer under the extrinsic base region, which is extracted from the intrinsic base region directly under the emitter region, by ion implantation and eliminating the junction capacitance in that region. was reduced.

In addition, since the crystallinity of the external base region deteriorates due to the ion implantation and the resistance increases, impurity ions are further implanted into the external base region to increase carriers,
It was reducing resistance. An example is shown in FIG.

A collector contact region 2 containing a high concentration of n-type impurities is formed on a semiconductor substrate 1. Collector region containing n-type impurity 3. Intrinsic base region containing a high concentration of p-type impurities4. In order to form a heterojunction, an emitter region 5 containing an n-type impurity and an emitter contact film region 6 containing a high concentration of n-type impurities, which are made of a semiconductor having a bandgap larger than that of the base region, are sequentially formed. , an external base region 12 in which p-type impurities are ion-implanted to reduce resistance, and an insulating region 1 in which carriers are reduced by ion implantation in the collector layer directly under the external base region 12.
1 is formed, and an element isolation region 13 insulated by ion implantation is formed around the periphery. Further, a collector electrode 7 is in ohmic contact with the collector contact region 2, the external base region 12, and the emitter contact region 6, respectively. For example, an IEEE electron device in which a base electrode 8 and an emitter electrode 9 are formed.
Letters vol.1. BDL-5, 310 (1984).

Problems to be Solved by the Invention However, in the above configuration, since the collector contact region for leading out the collector electrode exists under the insulating region, the external base region and the collector contact are still directly under the external base region. There is a stray capacitance like a parallel plate capacitor with area tpi. Furthermore, when the p-type impurity ion-implanted into the external base region diffuses downward, Cbc increases. Therefore, there is a structural limit to the reduction of Cbc, which poses a problem in increasing the frequency of transistors.

The present invention greatly improves the above problems, and by eliminating the stray capacitance directly under the external base region, Cb
It is an object of the present invention to provide a method for manufacturing a bipolar transistor that structurally minimizes c and Re.

Means for Solving the Problems In order to solve the above problems, the method for manufacturing a bipolar transistor of the present invention includes forming, from the substrate side, at least a collector contact layer serving as a collector contact region and a collector contact layer serving as a collector region on a semi-insulating substrate. a base layer serving as an extrinsic base region and an intrinsic base region, and an emitter layer serving as an emitter region; forming a first mask on the multilayer film; and forming a first mask on the multilayer film; A step of insulating the collector contact layer and the periphery of the collector layer by ion implantation from the surface of the multilayer film using a mask to form a collector contact region and a collector region, and covering a part of the first mask. forming a second mask, removing a portion of the first mask that is not covered by the second mask, and using the second mask to cover the periphery of the base layer. A step of insulating the surface of the multilayer film by ion implantation to form an extrinsic base region and an intrinsic base region; a step of removing the second mask and using the remainder of the first mask as a third mask; removing the periphery of the emitter layer using a third mask to form an emitter region;
The method is characterized by comprising a step of inverting the third mask to form an emitter electrode.

Operation The method for manufacturing a bipolar transistor having the above structure includes self-alignment of the first mask that defines the collector contact region and the collector region, and the second mask that defines the external base region, and the third mask that defines the emitter region and the emitter electrode. Since a mask is formed, the collector contact region and the collector region and the external base region can be formed without effectively overlapping each other, and Cbc contributes greatly to higher frequencies.
However, it is possible to form a transistor that is structurally minimal. Furthermore, since the emitter electrode is formed by an inversion method, Re can be minimized structurally, and the present invention can be used even in a fine emitter region, so that the high frequency characteristics are further improved.

Example An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows gallium arsenide-based np in an embodiment of the present invention.
FIG. 2 is a configuration diagram showing a method for manufacturing an n-type bipolar transistor. Figure 1(a), Figure 2(a), Figure 3(a), Figure 4(a), and Figure 5(a) are configuration diagrams when looking at the transistor from above, and Figure 1(b). ), Figure 2(b), Figure 3(c), Figure 4(c), Figure 5Φ) are A-A in Figure 1(a).
Figure 1 (C), Figure 2 (C), Figure 3 (C), Figure 4 (C), Figure 5 (C) are cross-sectional views along Figure 1 (a).
) is a sectional view taken along line BB'. First, a collector contact layer 22 containing a high concentration of n-type impurities is formed on a semi-insulating substrate 21 of gallium arsenide, which will serve as a collector contact region. Collector layer 23 containing n-type impurities and serving as a collector region. Hess layer 24 containing a high concentration of p-type impurities and serving as an extrinsic base region and an intrinsic base region
．． Emitter layer 25 containing n-type impurities and serving as an emitter region. Then, an emitter contact 1126 containing a high concentration of n-type impurity, which will become an emitter contact region, is formed in order by film growth, and the emitter contact J126
A first mask 41 is formed using a silicon oxide film or the like on the surface, and oxygen ions or the like are deeply implanted from the surface around the collector contact layer 22 and the collector N23.
A first insulating region 31 is formed. Subsequently, in order to reduce the external base resistance, beryllium or the like is implanted to form an external base layer 32 (FIG. 1(a)).

(b), (C)). Next, a second mask 42 is formed using aluminum or the like to be elongated so as to span over the first mask 41, and a portion of the first mask 41 that is not covered by the second mask 42 is dry-treated. Remove by etching. Subsequently, oxygen ions are shallowly implanted from the surface into at least the periphery of the base layer 24 to form a second insulating region 33.
(Fig. 2(a), (b), (c)). Furthermore, the second mask 42 is removed and the first mask 4 is removed.
The remaining portion of 1 is used as a third mask 43. Using this third mask 43, the periphery of the emitter 1i25 and the emitter contact layer 26 is removed by wet etching (Fig. 3(a), (b), (C)). Collector contact 112 with mask 41
2 and the collector layer 23, and an external base region from the external base layer 32 using the second mask 42, and the first mask 41 and the second mask 42. An emitter region is formed from the emitter layer 26 using the third mask 43 formed by self-alignment. Next, after recovering the crystallinity of the ion-implanted part by heat treatment, a resist is applied to the surface, and the third mask 4 is etched by dry etching.
3, the third mask 43 is removed by wet etching to form a fourth mask 44 (see FIG. 4).
a).

(2), (C)) An emitter electrode 29 is formed on the emitter contact region 26 by a lift-off method using the fourth mask 44. Finally, a collector electric bridge 27. is placed on the collector contact region 22. Above external base area 3
A base electrode 28 is formed on each of the base electrodes 2 and 2, and the npn type bipolar transistor in this example is completed (fifth
Figures (a), (b), (C)).

The arrangement of the collector electrode and the base electrode in the above manufacturing method can be arranged in various combinations depending on the shapes of the first mask and the second mask. Furthermore, since the first insulating region is formed at a deeper position than the base layer,
There is no particular need to perform ion implantation to reduce external base resistance.

The above manufacturing method can also be used for a heterojunction bipolar transistor with better high-frequency characteristics; in this case, a semiconductor having a larger forbidden band width than the semiconductor used for the base layer during film growth may be used for the emitter layer. Furthermore, it can also be applied to pnp type transistors.

Effects of the Invention As described above, the method for manufacturing a bipolar transistor having the structure of the present invention is achieved by self-aligning the first mask that defines the collector contact region and the collector region and the second mask that defines the external base region. , form a third mask that defines the emitter region and emitter electrode, so
The collector contact region and the collector region and the external base region can be formed without effectively overlapping each other, and a transistor can be formed in which Cbc, which greatly contributes to higher frequencies, is minimized in terms of structure.

Furthermore, since the emitter electrode is formed by an inversion method, Re can be minimized structurally, and the present invention can be used even in a fine emitter region, so that the high frequency characteristics are further improved. Furthermore, since both the first insulating region and the second insulating region serve as isolation between elements, the transistor can be manufactured with fewer steps than in conventional manufacturing methods.

[Brief explanation of the drawing]

1 to 5 are block diagrams showing a method of manufacturing a transistor according to an embodiment of the present invention, and FIG. 6 is a sectional view showing the structure of a conventional transistor. 21... Semi-insulating substrate, 22... Collector contact layer, 23... Collector layer, 24
・Old...Base layer, 25...Emitter layer, 26
- Old... Emitter contact layer, 27... Collector electrode, 28 - Old... Base electrode, 29...
Emitter electrode, 31...first insulating region, 32.
...External base layer, 33...Second termination H6
Area 11, 41...First mask, 42...
...Second mask, 43...Third mask, 4
4...Fourth mask. Name of agent: Patent attorney Shigetaka Awano Actual figure 2I/-IP! f! Body F machine 22 --- Collector electrode 7 4 23...-Kodanoi! Parable 4 z5-1 work ξy91 3t-1 work ξy91

Claims (3)

[Claims] (1) On a semi-insulating substrate, from the substrate side, at least a collector contact layer serving as a collector contact region, a collector layer serving as a collector region, a base layer serving as an extrinsic base region and an intrinsic base region, and an emitter serving as an emitter region. forming a first mask on the multilayer film, and using the first mask to remove the collector contact layer and the periphery of the collector layer from the surface of the multilayer film. A step of insulating by ion implantation to form a collector contact region and a collector region, and a second mask covering a part of the first mask and a part other than the first mask continuing from the part. a step of removing a portion of the first mask that is not covered by the second mask, and a step of removing ions from the surface of the multilayer film around the base layer using the second mask. implanting isolation to form an extrinsic base region and an intrinsic base region; removing the second mask and using the remainder of the first mask as a third mask;
A bipolar transistor comprising the steps of: removing the periphery of the emitter layer using the third mask to form an emitter region; and forming an emitter electrode by inverting the third mask. manufacturing method. 2. The method for manufacturing a bipolar transistor according to claim 1, further comprising the step of using, for the emitter layer, a semiconductor having a wider forbidden band width than the semiconductor used for the base layer. (3) Manufacturing the bipolar transistor according to claim (2), which comprises the step of implanting ions from the surface of the multilayer film around the base layer using a first mask to reduce the resistance of the external base region. Method.