JPH0215728U - - Google Patents

Info

Publication number
JPH0215728U
JPH0215728U JP1988093295U JP9329588U JPH0215728U JP H0215728 U JPH0215728 U JP H0215728U JP 1988093295 U JP1988093295 U JP 1988093295U JP 9329588 U JP9329588 U JP 9329588U JP H0215728 U JPH0215728 U JP H0215728U
Authority
JP
Japan
Prior art keywords
semiconductor chip
mounting portion
groove
view
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988093295U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988093295U priority Critical patent/JPH0215728U/ja
Publication of JPH0215728U publication Critical patent/JPH0215728U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Die Bonding (AREA)
JP1988093295U 1988-07-13 1988-07-13 Pending JPH0215728U (US07943777-20110517-C00090.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988093295U JPH0215728U (US07943777-20110517-C00090.png) 1988-07-13 1988-07-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988093295U JPH0215728U (US07943777-20110517-C00090.png) 1988-07-13 1988-07-13

Publications (1)

Publication Number Publication Date
JPH0215728U true JPH0215728U (US07943777-20110517-C00090.png) 1990-01-31

Family

ID=31317741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988093295U Pending JPH0215728U (US07943777-20110517-C00090.png) 1988-07-13 1988-07-13

Country Status (1)

Country Link
JP (1) JPH0215728U (US07943777-20110517-C00090.png)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07201893A (ja) * 1995-01-31 1995-08-04 Sony Corp 半導体装置
JP2014186244A (ja) * 2013-03-25 2014-10-02 Stanley Electric Co Ltd Memsデバイス
WO2020117431A3 (en) * 2018-12-07 2020-07-30 Google Llc Integrated circuit substrate for containing liquid adhesive bleed-out

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156753A (ja) * 1984-12-27 1986-07-16 Toshiba Corp 半導体装置の外囲器
JPS61212043A (ja) * 1985-03-18 1986-09-20 Hitachi Ltd 半導体実装基板
JPS62241355A (ja) * 1986-04-14 1987-10-22 Hitachi Ltd 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156753A (ja) * 1984-12-27 1986-07-16 Toshiba Corp 半導体装置の外囲器
JPS61212043A (ja) * 1985-03-18 1986-09-20 Hitachi Ltd 半導体実装基板
JPS62241355A (ja) * 1986-04-14 1987-10-22 Hitachi Ltd 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07201893A (ja) * 1995-01-31 1995-08-04 Sony Corp 半導体装置
JP2014186244A (ja) * 2013-03-25 2014-10-02 Stanley Electric Co Ltd Memsデバイス
WO2020117431A3 (en) * 2018-12-07 2020-07-30 Google Llc Integrated circuit substrate for containing liquid adhesive bleed-out
US10818567B2 (en) 2018-12-07 2020-10-27 Google Llc Integrated circuit substrate for containing liquid adhesive bleed-out
US11264295B2 (en) 2018-12-07 2022-03-01 Google Llc Integrated circuit substrate for containing liquid adhesive bleed-out

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