JPH02156564A - Manufacture of semiconductor storage device - Google Patents
Manufacture of semiconductor storage deviceInfo
- Publication number
- JPH02156564A JPH02156564A JP63311111A JP31111188A JPH02156564A JP H02156564 A JPH02156564 A JP H02156564A JP 63311111 A JP63311111 A JP 63311111A JP 31111188 A JP31111188 A JP 31111188A JP H02156564 A JPH02156564 A JP H02156564A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon oxide
- film
- electrode
- layer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000003860 storage Methods 0.000 title claims description 5
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 239000003990 capacitor Substances 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract description 15
- 239000010703 silicon Substances 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 230000004888 barrier function Effects 0.000 abstract description 13
- 230000008021 deposition Effects 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 13
- 239000000969 carrier Substances 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 208000032376 Lung infection Diseases 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- WQGWDDDVZFFDIG-UHFFFAOYSA-N pyrogallol Chemical compound OC1=CC=CC(O)=C1O WQGWDDDVZFFDIG-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高信頼性で高密度な半導体記憶装置の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a highly reliable and high density semiconductor memory device.
従来の技術
第2図(a)に示すように、不純物導入されたポリシリ
コンやシリコン基板等の容量電極10とシリコン窒化膜
9を直接接触させて二つの容量電極10間に電圧差を加
えると、MOSダイナミックメモノの蓄積容量はシリコ
ン窒化膜9のキャリアに対するバリア高さが低いので、
容量電極10からのキャリアの動きは16に示されるよ
うになりキャリアが注入されやすくなって、リーク電流
を増すことになる。BACKGROUND ART As shown in FIG. 2(a), when a capacitive electrode 10 made of impurity-doped polysilicon or a silicon substrate is brought into direct contact with a silicon nitride film 9 and a voltage difference is applied between the two capacitive electrodes 10, a voltage difference is applied between the two capacitive electrodes 10. , the storage capacitance of the MOS dynamic memo is due to the low barrier height of the silicon nitride film 9 against carriers.
The movement of carriers from the capacitor electrode 10 is as shown in 16, and carriers are more likely to be injected, resulting in an increase in leakage current.
これを抑えるため、従来第2図(b)に示すように容量
電極10とシリコン窒化膜9の間にバリア高さがシリコ
ン窒化膜9に比べて高いバリアシリコン酸化膜11を挟
むことが行われ、前記シリコン酸化膜11の形成方法と
して、(i)シリコン基板またはポリシリコンの熱酸化
によるもの(ii )減圧窒化膜堆積炉に入れる際の大
気中での自然酸化膜をそのまま利用するものなどが用い
られてきた。In order to suppress this, conventionally a barrier silicon oxide film 11 having a higher barrier height than the silicon nitride film 9 is sandwiched between the capacitor electrode 10 and the silicon nitride film 9 as shown in FIG. 2(b). The method for forming the silicon oxide film 11 includes (i) thermal oxidation of a silicon substrate or polysilicon, and (ii) use of a natural oxide film in the atmosphere when placed in a reduced pressure nitride film deposition furnace. has been used.
従来の方法であれば、面方位の異なる幾つかの面を有す
るシリコン基板上に容量絶縁膜としてシリコン酸化膜を
形成する場合、前記シリコン酸化膜11の膜厚にバラツ
キが生じる。典型的には第3図(a)に示すトレンチ形
容量である。この場合、シリコン基板1に掘られた溝に
は異なる面方位を有する面6,7.8が存在するが、こ
れを従来の方法でシリコン酸化膜を形成すると第3図(
a)に示すように、バリアシリコン酸化膜13が各面方
位を有する所で異なる膜厚となる。その後シリコン窒化
膜3を堆積した後、その表層にシリコン酸化114を形
成し、ポリシリコン電極5を形成した場合、この三層絶
縁膜では良好な絶縁耐圧が得られない。In the conventional method, when a silicon oxide film is formed as a capacitor insulating film on a silicon substrate having several planes with different plane orientations, variations occur in the thickness of the silicon oxide film 11. A typical example is a trench-type capacitor shown in FIG. 3(a). In this case, there are planes 6, 7.8 with different plane orientations in the trench dug in the silicon substrate 1, but if a silicon oxide film is formed using the conventional method, this is shown in FIG.
As shown in a), the thickness of the barrier silicon oxide film 13 differs depending on the plane orientation. If silicon nitride film 3 is then deposited and then silicon oxide 114 is formed on its surface layer to form polysilicon electrode 5, good dielectric strength cannot be obtained with this three-layer insulating film.
また、第2図(b)に示すようにポリシリコン12上に
容量絶縁膜としてシリコン酸化膜を形成する場合〈スタ
ック型容量〉、面方位の違いによる膜厚差に加えて、粒
界での増速酸化15が起こりバリアシリコン酸化膜14
の膜厚バラツキが更に大きくなる。同様に三層絶縁膜を
形成した場合、バリアシリコン酸化膜14の膜厚バラツ
キのため、前記三層絶縁膜の絶縁耐圧を劣化させる。In addition, when a silicon oxide film is formed as a capacitor insulating film on polysilicon 12 (stack type capacitor) as shown in FIG. 2(b), in addition to the difference in film thickness due to the difference in plane orientation, Accelerated oxidation 15 occurs and barrier silicon oxide film 14
The film thickness variation becomes even larger. Similarly, when a three-layer insulating film is formed, the withstand voltage of the three-layer insulating film deteriorates due to variations in the thickness of the barrier silicon oxide film 14.
発明が解決しようとする課題
しかし、かかる構成によれば、バリアシリコン酸化膜(
下地シリコン酸化膜)の膜厚バラツキが三層絶縁膜の絶
縁耐圧を劣化させるという問題があった。Problems to be Solved by the Invention However, according to such a configuration, the barrier silicon oxide film (
There was a problem in that variations in the thickness of the underlying silicon oxide film degraded the dielectric strength of the three-layer insulating film.
本発明は、上述の問題点に鑑みて試されたもので、バリ
アシリコン酸化膜厚を均一化し、三層絶縁膜が良好な絶
縁耐圧を有する半導体記憶装置の本発明は上述の課組を
解決するため、自然酸化膜を成長させずに堆積酸化膜で
三層絶縁膜の下地シリコン酸化膜を形成させるという構
成を備えたものである。The present invention has been tried in view of the above-mentioned problems, and the present invention of a semiconductor memory device in which the barrier silicon oxide film thickness is made uniform and the three-layer insulating film has good dielectric strength voltage solves the above-mentioned problems. Therefore, the structure is such that a base silicon oxide film of a three-layer insulating film is formed using a deposited oxide film without growing a natural oxide film.
作用
本発明は上述の構成によって、下地シリコン酸化膜が堆
積によって形成されるために膜厚のバラツキがな(、三
層絶縁膜は良好な絶縁耐圧を有することが可能となる。According to the present invention, with the above-described structure, the base silicon oxide film is formed by deposition, so there is no variation in film thickness (and the three-layer insulating film can have a good dielectric strength voltage).
実施例
第1図(a)、 (b)はそれぞれ本発明の一実施例に
よるトレンチ型容量およびスタック型容量の構造を示す
断面図である。まず第1図(a)を用いて、本発明のト
レンチ型容量について説明する。Embodiment FIGS. 1(a) and 1(b) are cross-sectional views showing the structures of a trench type capacitor and a stack type capacitor, respectively, according to an embodiment of the present invention. First, the trench type capacitor of the present invention will be explained using FIG. 1(a).
シリコン基板1に掘られた溝(トレンチ)内部には高濃
度に不純物を導入し、前記トレンチにはトレンチエッチ
の時に異なる面方位を有する面6.7.8が存在する。Impurities are introduced at a high concentration into the interior of a trench dug in the silicon substrate 1, and surfaces 6, 7, and 8 having different surface orientations exist in the trench during trench etching.
前記溝を有するシリコン基板1上にバリアシリコン酸化
膜を形成する際、自然酸化膜を完全に除去した後減圧C
VD法によりCVDシリコン酸化膜2を堆積する。この
時、CVDシリコン酸化膜2形成条件は、300℃以下
の低温で減圧CVD炉に挿入し、10To r r以下
に減圧した後、昇温して50A以下の例えば30AのC
VDシリコン酸化膜2を形成する。When forming a barrier silicon oxide film on the silicon substrate 1 having the grooves, after completely removing the natural oxide film, a reduced pressure C.
A CVD silicon oxide film 2 is deposited by the VD method. At this time, the conditions for forming the CVD silicon oxide film 2 are that it is inserted into a low-pressure CVD furnace at a low temperature of 300° C. or lower, the pressure is reduced to 10 Torr or lower, and then the temperature is raised to 50 A or lower, for example, 30 A.
A VD silicon oxide film 2 is formed.
300℃以下であれば、シリコン基板1上に形成される
自然酸化膜は十分薄(、生じる膜厚バラツキは無視でき
る。また1 0To r r以下であれば昇温しても同
様に、自然酸化膜は十分薄(、生じる膜厚バラツキは無
視できる。本発明によれば、CVDシリコン酸化膜2は
いかなる面方位を有する面においても膜厚は均一となる
。この上に6OAのシリコン窒化膜3をCVD法により
堆積し、その表層に例えば850℃のパイロ雰囲気中で
30分間処理してシリコン酸化膜4を形成し、約0.4
μmのポリシリコン電極5を形成した場合、この三層絶
縁膜は良好な絶縁耐圧を有する。If the temperature is below 300°C, the natural oxide film formed on the silicon substrate 1 will be sufficiently thin (the resulting film thickness variations can be ignored. Also, if the temperature is below 10 Torr, the natural oxide film formed on the silicon substrate 1 will remain thin even if the temperature is raised). The film is sufficiently thin (the resulting film thickness variation can be ignored. According to the present invention, the CVD silicon oxide film 2 has a uniform film thickness on any plane having any surface orientation. On top of this, a 6OA silicon nitride film 3 is formed. is deposited by the CVD method, and the surface layer is treated for 30 minutes in a pyro atmosphere at 850°C to form a silicon oxide film 4, with a thickness of about 0.4
When the polysilicon electrode 5 with a thickness of .mu.m is formed, this three-layer insulating film has a good dielectric strength.
次に第2図(b)を用いて、本発明のスタック型容量に
ついて説明する。Next, the stacked capacitor of the present invention will be explained using FIG. 2(b).
シリコン基板1上に形成され、高濃度に不純物が導入さ
れたポリシリコン電極12上にバリアシリコン酸化膜を
形成する際、自然酸化膜を完全に除去した後、減圧CV
D法によりCVDシリコン酸化膜2を堆積し、その堆積
条件は上記の堆積条件と同様である。本発明によれば、
面方位の違いよる膜厚差および粒界での増速酸化が起こ
らないため、CVDシリコン酸化膜2は均一に形成でき
る。その後、同様な工程により形成された三層絶縁膜は
良好な絶縁耐圧を有する。When forming a barrier silicon oxide film on the polysilicon electrode 12 formed on the silicon substrate 1 and doped with impurities at a high concentration, after completely removing the natural oxide film, low pressure CVD is applied.
A CVD silicon oxide film 2 is deposited by the D method, and the deposition conditions are similar to those described above. According to the invention,
The CVD silicon oxide film 2 can be formed uniformly because there is no difference in film thickness due to the difference in plane orientation and no accelerated oxidation occurs at grain boundaries. Thereafter, a three-layer insulating film formed through similar steps has good dielectric strength.
なお本実施例ではCVDシリコン酸化膜2の堆積条件は
上記した条件に限らず、シリコン基板1またはポリシリ
コン電極12上に自然酸化膜が生じないでCVDシリコ
ン酸化膜が形成できる方法であれば良いことは言うまで
もない。In this embodiment, the deposition conditions for the CVD silicon oxide film 2 are not limited to those described above, and any method may be used as long as the CVD silicon oxide film can be formed without forming a natural oxide film on the silicon substrate 1 or the polysilicon electrode 12. Needless to say.
発明の効果
以上の説明から明らかなように、本発明は自然酸化膜を
成長させずに堆積酸化膜で三層絶縁膜の下地バリアシリ
コン酸化膜を形成することによって、極めて簡易な処理
で下地シリコン酸化膜の膜厚バラツキがなく、DRAM
蓄積容量絶縁膜の実効的信頼性を向上させることができ
る。このことは工業的に実用的価値が高い。Effects of the Invention As is clear from the above explanation, the present invention forms a base barrier silicon oxide film for a three-layer insulating film using a deposited oxide film without growing a native oxide film. DRAM with no variation in oxide film thickness
The effective reliability of the storage capacitor insulating film can be improved. This has high practical value industrially.
第1図(a)、 (b)はそれぞれ本発明の一実施例に
よるトレンチ型容量およびスタック型容量の構造を示す
断面図、第2図(a)、 (b)は容量を形成する誘電
体膜として、それぞれシリコン窒化膜および三層絶縁膜
を用いた時のバンド図、第3図(a)、 (b)はそれ
ぞれ従来のトレンチ型容量およびスタック型容量の構造
を示す断面図である。
1・・・・・・シリコン基板、2・・・・・・CVDシ
リコン酸化膜、3・・・・・・シリコン窒化膜、4・・
・・・・シリコン酸化膜、5・・・・・・ポリシリコン
電極(上層)、6゜7.8・・・・・・異なる面方位の
面、12・・・・・・ポリシリコン電極(下層)。
代理人の氏名 弁理士 粟野重孝 ほか1名l −・
2−・−
3−・・
4−・=
5−・−
シリコン暮柄
CVOシリコ″/肺化膿
シリコン富化類
シリコン酸化層
ゴリシリコン電W1(J:l)
?−シリコン讐1t1.順
10−一容量を穀FIGS. 1(a) and (b) are cross-sectional views showing the structures of a trench type capacitor and a stacked type capacitor according to an embodiment of the present invention, respectively, and FIGS. 2(a) and (b) are dielectrics forming the capacitor. Band diagrams are shown when a silicon nitride film and a three-layer insulating film are used as the film, respectively, and FIGS. 3(a) and 3(b) are cross-sectional views showing the structures of a conventional trench-type capacitor and a conventional stack-type capacitor, respectively. 1...Silicon substrate, 2...CVD silicon oxide film, 3...Silicon nitride film, 4...
...Silicon oxide film, 5...Polysilicon electrode (upper layer), 6°7.8...Face with different surface orientation, 12...Polysilicon electrode ( Underlayer). Name of agent: Patent attorney Shigetaka Awano and 1 other person l −・ 2−・− 3−・・ 4−・= 5−・− Silicon dead handle CVO silico''/Pulmonary suppuration silicon enriched silicon oxide layer Gorisilicon Den W1 (J:l) ?-Silicon enemy 1t1.Order 10-1 volume of grain
Claims (1)
コンに高濃度に不純物を導入して電荷蓄積容量の第1の
電極を形成する工程と、前記半導体基板あるいは前記ポ
リシリコン表面に成長した自然酸化膜を除去し、前記半
導体基板あるいは前記ポリシリコン上にCVD法を用い
てシリコン酸化膜を堆積し、前記シリコン酸化膜上にシ
リコン窒化膜を堆積する工程と、前記シリコン窒化膜の
上層を酸化して形成されたシリコン酸化膜上に電荷蓄積
容量の第2の電極を形成する工程からなる半導体記憶装
置の製造方法。A step of introducing impurities at a high concentration into a semiconductor substrate or polysilicon formed on the semiconductor substrate to form a first electrode of a charge storage capacitor, and a step of forming a natural oxide film grown on the surface of the semiconductor substrate or the polysilicon. a step of depositing a silicon oxide film on the semiconductor substrate or the polysilicon using a CVD method, depositing a silicon nitride film on the silicon oxide film, and oxidizing the upper layer of the silicon nitride film. A method for manufacturing a semiconductor memory device comprising the step of forming a second electrode of a charge storage capacitor on a silicon oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63311111A JPH02156564A (en) | 1988-12-08 | 1988-12-08 | Manufacture of semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63311111A JPH02156564A (en) | 1988-12-08 | 1988-12-08 | Manufacture of semiconductor storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02156564A true JPH02156564A (en) | 1990-06-15 |
Family
ID=18013279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63311111A Pending JPH02156564A (en) | 1988-12-08 | 1988-12-08 | Manufacture of semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02156564A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05326842A (en) * | 1991-12-28 | 1993-12-10 | Nec Corp | Semiconductor device and manufacture thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6085555A (en) * | 1983-10-18 | 1985-05-15 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS6317544A (en) * | 1986-07-10 | 1988-01-25 | Seiko Instr & Electronics Ltd | Semiconductor device |
-
1988
- 1988-12-08 JP JP63311111A patent/JPH02156564A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6085555A (en) * | 1983-10-18 | 1985-05-15 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS6317544A (en) * | 1986-07-10 | 1988-01-25 | Seiko Instr & Electronics Ltd | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05326842A (en) * | 1991-12-28 | 1993-12-10 | Nec Corp | Semiconductor device and manufacture thereof |
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