JPH02154577A - Video signal processor - Google Patents

Video signal processor

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Publication number
JPH02154577A
JPH02154577A JP88307988A JP30798888A JPH02154577A JP H02154577 A JPH02154577 A JP H02154577A JP 88307988 A JP88307988 A JP 88307988A JP 30798888 A JP30798888 A JP 30798888A JP H02154577 A JPH02154577 A JP H02154577A
Authority
JP
Japan
Prior art keywords
output
signal
delay means
component
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP88307988A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Yamamoto
義之 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP88307988A priority Critical patent/JPH02154577A/en
Publication of JPH02154577A publication Critical patent/JPH02154577A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To contrive the effective use of two delay means by extracting a differential component from 3 signals, retarded signals by 1st and 2nd delay times and an original signal, using the component for a contour correction means when the level is large and using the component for a noise reduction means when the level is smaller. CONSTITUTION:When a signal including a noise component is inputted, outputs of 1st and 2nd means 2, 3 are (b), (c), the output of a 1st adder is (d), and the output of a 1st subtractor 6 is (e) and the output of a limiter 13 is a waveform (h) being the result of extracting a noise component of the flat part of the input signal. When the coefficient K1 of a coefficient circuit 14 is set properly, a signal (i) being the result of reducing the noise component remarkably is obtained at the output of the 2nd subtractor 15. Moreover, a waveform (j) being the result of extracting a difference component near the contour is obtained at the output of a slicer 16 and a signal in which the noise component of a flat part is remarkably reduced and pre-shoot and overshoot having a time interval T are added from the 2nd adder 8 is obtained by setting properly the coefficient K2 of the circuit 7. Thus, two delay means are used effectively.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、磁気録画再生装置等において、画質2 ヘー
ノ 向上手段として利用される映像信号処理装置に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device used as means for improving image quality in a magnetic recording/reproducing device or the like.

従来の技術 従来より、遅延手段を用いた画質向上手段として輪郭補
正手段あるいはノイズ低減手段が広く用いられている。
2. Description of the Related Art Conventionally, contour correction means or noise reduction means have been widely used as means for improving image quality using delay means.

第3図に従来の映像信号処理装置の一例のブロック図を
示す。
FIG. 3 shows a block diagram of an example of a conventional video signal processing device.

第3図において、入力端子1に入力された信号は、第1
の遅延手段2を介して第2の遅延手段3と、edB増幅
器4に供給される。第2の遅延手段3の出力は第1の加
算器6で入力端子1に入力された信号と加算される。
In FIG. 3, the signal input to input terminal 1 is
The signal is supplied to the second delay means 3 and the edB amplifier 4 via the delay means 2 . The output of the second delay means 3 is added to the signal input to the input terminal 1 in the first adder 6.

edB増幅器の出力は、減算器6に供給されて、第1の
加算器5の出力との差成分が係数回路7に供給されて所
定のレベルに変換された後、第2の加算器8で第1の遅
延手段2の出力と加算されて出力端子9に出力される。
The output of the edB amplifier is supplied to a subtracter 6, and the difference component from the output of the first adder 5 is supplied to a coefficient circuit 7 and converted to a predetermined level. It is added to the output of the first delay means 2 and output to the output terminal 9.

ここで減算器6の出力は、第1の遅延手段2の出力と入
力端子1に入力された信号との差成分と、第1の遅延手
段2の出力と第2の遅延手段3の出力との差成分とを加
算3 ・・−7 した信号と同じものである。
Here, the output of the subtracter 6 is the difference component between the output of the first delay means 2 and the signal input to the input terminal 1, and the output of the first delay means 2 and the output of the second delay means 3. This is the same signal obtained by adding the difference components of 3...-7.

第4図に、第3図に示した従来例の動作を説明するため
の波形図を示す。簡単のため第1の遅延手段2と第2の
遅延手段3の遅延時間は同一値Tであるとする。
FIG. 4 shows a waveform diagram for explaining the operation of the conventional example shown in FIG. 3. For the sake of simplicity, it is assumed that the delay times of the first delay means 2 and the second delay means 3 are the same value T.

入力端子1に第4図aに示す信号が入力された場合、第
1の遅延手段2および第2の遅延手段3の出力はそれぞ
れ第4図すおよびCのようになる。
When the signal shown in FIG. 4a is input to the input terminal 1, the outputs of the first delay means 2 and the second delay means 3 are as shown in FIG. 4A and C, respectively.

したがって第1の加算器5の出力は第4図dのようにな
り、減算器6の出力は第4図eのようになる。さらに係
数回路7の係数Kを適当に設定する(第4図ではに夕0
.4)ことによって出力端子9には第4図fのように、
共に時間幅Tを有するプリシュートとオーバーシュート
を付加した波形を得ることができる。すなわち、第3図
に示した従来例は輪郭補正手段である。
Therefore, the output of the first adder 5 is as shown in FIG. 4d, and the output of the subtracter 6 is as shown in FIG. 4e. Furthermore, the coefficient K of the coefficient circuit 7 is set appropriately (in FIG.
.. 4) As a result, the output terminal 9 has the following as shown in Fig. 4f.
A waveform to which preshoot and overshoot are added, both of which have a time width T, can be obtained. That is, the conventional example shown in FIG. 3 is a contour correction means.

ここで、時間幅Tは通常数百n sec (ナノ秒)に
設定するが、これを1水平走査期間(1H)あるいは1
フレ一ム期間に設定することによって、さらに効果のあ
る輪郭補正を行うこともある。
Here, the time width T is usually set to several hundred nanoseconds (nanoseconds), but this is set to one horizontal scanning period (1H) or one horizontal scanning period (1H).
By setting the frame period, more effective contour correction may be performed.

第5図に、従来の映像信号処理装置の他の例を示す。FIG. 5 shows another example of a conventional video signal processing device.

第5図において、入力端子1に入力された信号は、遅延
手段11を介して第1の減算器12に供給されて、入力
信号と遅延手段11の出力との差成分が得られてリミッ
タ回路13に供給される。
In FIG. 5, the signal input to the input terminal 1 is supplied to the first subtracter 12 via the delay means 11, and the difference component between the input signal and the output of the delay means 11 is obtained and the limiter circuit 13.

リミッタ回路13で差成分のうち大振幅成分が制限され
た上、係数回路14で所定のレベルに変換された後、第
2の減算器15で入力信号から減算されて出力端子9に
出力される。
The large amplitude component of the difference component is limited by the limiter circuit 13, converted to a predetermined level by the coefficient circuit 14, and then subtracted from the input signal by the second subtracter 15 and output to the output terminal 9. .

第6図に、第5図に示した従来例の動作を説明するため
の波形図を示す。遅延手段11の遅延時間をTとする。
FIG. 6 shows a waveform diagram for explaining the operation of the conventional example shown in FIG. Let T be the delay time of the delay means 11.

入力端子1に第6図aに示すようなノイズ成分を含む信
号が入力された場合、遅延手段11の出力は第6図すの
ようになり、減算器12の出力は第6図qのようになる
。したがってリミッタ回路13の出力は第6図りのよう
になり、さらに係数回路14の係数Kを適当に設定する
(第5図ではに〜0.5)ことによって、出力端子9に
は第6図51\−7 fのように平坦部のノイズ成分を大幅に低減した波形を
得ることができる。すなわち、第5図に示した従来例は
ノイズ低減手段である。
When a signal containing a noise component as shown in FIG. 6a is input to the input terminal 1, the output of the delay means 11 is as shown in FIG. 6, and the output of the subtracter 12 is as shown in FIG. 6q. become. Therefore, the output of the limiter circuit 13 becomes as shown in Fig. 6, and by setting the coefficient K of the coefficient circuit 14 appropriately (to 0.5 in Fig. 5), the output terminal 9 becomes as shown in Fig. 6. It is possible to obtain a waveform such as \-7f in which the noise component in the flat part is significantly reduced. That is, the conventional example shown in FIG. 5 is a noise reduction means.

発明が解決しようとする課題 以上に述べた従来の技術を組み合わせて使用する場合に
、必要とする遅延手段や加減算器の数が多くなり高価な
ものになる。捷た遅延手段はそれ自身がS/N 劣化の
原因となる場合もある。
Problems to be Solved by the Invention When the above-mentioned conventional techniques are used in combination, the number of delay means and adders/subtracters required increases, making the system expensive. A broken delay means itself may cause S/N deterioration.

本発明は前記問題点に鑑み、2個の遅延手段を用いて輪
郭補正とノイズ低減を良好に行うことができる映像信号
処理装置を提供するものである。
In view of the above problems, the present invention provides a video signal processing device that can perform contour correction and noise reduction satisfactorily using two delay means.

課題を解決するための手段 前記問題点を解決するために本発明の映像信号処理装置
は、入力信号を第1の遅延時間だけ遅延する第1の遅延
手段と、前記第1の遅延手段の出力信号をさらに第2の
遅延時間だけ遅延する第2の遅延手段と、前記第1の遅
延手段の出力信号と前記入力信号との差成分を取り出す
第1の減算器と、前記第1の遅延手段の出力信号と前記
第2の遅延手段の出力信号との差成分を取り出す第2の
6 ページ 減算器と、前記第1の減算器の出力信号と前記第2の減
算器の出力信号を加算する加算器と、前記加算器の出力
レベ/L/全判別して前記レベルに応じた極性と比率で
前記減算器の出力信号を前記第1の遅延手段生検の出力
信号に混合する混合手段とを具備するような構成とした
ものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the video signal processing device of the present invention includes a first delay means for delaying an input signal by a first delay time, and an output of the first delay means. a second delay means for further delaying the signal by a second delay time; a first subtracter for extracting a difference component between the output signal of the first delay means and the input signal; and the first delay means. a second 6-page subtracter for extracting a difference component between the output signal of the output signal and the output signal of the second delay means; and a second 6-page subtracter for adding the output signal of the first subtracter and the output signal of the second subtractor. an adder; and a mixing means for determining the output level/L/total of the adder and mixing the output signal of the subtracter with the output signal of the biopsy of the first delay means in a polarity and ratio according to the level. The configuration is such that it includes the following.

作  用 本発明は前述したような構成によって、第1の遅延時間
だけ遅延した信号とさらに第2の遅延時間だけ遅延した
信号と元の信号との3つの信号から差成分を取り出して
、そのレベルが大きいときには輪郭補正手段として働き
、かつそのレベルが小さいときにはノイズ低減手段とし
て働くので、2個の遅延手段を有効に利用することがで
きる。
Effect: With the above-described configuration, the present invention extracts the difference component from three signals: the signal delayed by the first delay time, the signal further delayed by the second delay time, and the original signal, and calculates the level of the difference component. When the level is large, it works as a contour correction means, and when its level is small, it works as a noise reduction means, so the two delay means can be used effectively.

実施例 以下本発明による映像信号処理装置の実施例について図
面を参照しながら説明する。
Embodiments Hereinafter, embodiments of a video signal processing apparatus according to the present invention will be described with reference to the drawings.

第1図に本発明の一実施例のブロック図を示す。FIG. 1 shows a block diagram of an embodiment of the present invention.

第1図において、入力端子1に入力された信号は、第1
の遅延手段2を介して第2の遅延手段3と67′\−・ dB増幅器4に供給される。第2の遅延手段3の出力は
第1の加算器5で入力端子1に入力された信号と加算さ
れる。edB増幅器の出力は第1の減算器6に供給され
て、第1の加算器5の出力との差成分が取り出されて、
リミッタ13とスライサ16に供給される。リミッタ1
3[おいて、所定のレベル値よりも小さい信号が取り出
されて係数回路14を介して第2の減算器16に供給さ
れて、第1の遅延手段の出力から減算される。寸だ、ス
ライサ16において、所定のレベル値よりも大きい信号
が取り出されて係数回路7を介して第2の加算器8に供
給されて、第2の減算器15の出力から減算されて出力
端子9に出力される。
In FIG. 1, the signal input to input terminal 1 is
The signal is supplied to the second delay means 3 and the 67'\-.dB amplifier 4 via the delay means 2. The output of the second delay means 3 is added to the signal input to the input terminal 1 in the first adder 5. The output of the edB amplifier is supplied to the first subtracter 6, and the difference component from the output of the first adder 5 is extracted.
It is supplied to a limiter 13 and a slicer 16. Limiter 1
3, a signal smaller than a predetermined level value is extracted and supplied to the second subtracter 16 via the coefficient circuit 14, where it is subtracted from the output of the first delay means. In the slicer 16, a signal larger than a predetermined level value is extracted and supplied to the second adder 8 via the coefficient circuit 7, where it is subtracted from the output of the second subtracter 15 and sent to the output terminal. 9 is output.

第2図に、第1図に示した一実施例の動作を説明するた
めの波形図を示す。簡単のため、第1の遅延手段2と第
2の遅延手段3の遅延時間は同一値Tであるとする。
FIG. 2 shows a waveform diagram for explaining the operation of the embodiment shown in FIG. 1. For simplicity, it is assumed that the delay times of the first delay means 2 and the second delay means 3 are the same value T.

入力端子1に第2図aに示すようにノイズ成分を含んだ
信号が入力された場合、第1の遅延手段2および第2の
遅延手段3の出力はそれぞれ第2図すおよびCのように
なる。したがって第1の加算器6の出力は第2図dのよ
うになり、第1の減算器6の出力は第2図eのようにな
る。したがってリミッタ13の出力は第2図りのように
入力信号の平坦部分のノイズ成分を取り出したような波
形となり、係数回路14の係数に1 を適当に設定する
ことによって、第2の減算器15の出力には第2図iの
ように入力信号の平坦部分のノイズ成分を大幅に低減し
た信号が得られる。
When a signal containing a noise component is input to the input terminal 1 as shown in Fig. 2a, the outputs of the first delay means 2 and the second delay means 3 are as shown in Fig. 2A and C, respectively. Become. Therefore, the output of the first adder 6 is as shown in FIG. 2d, and the output of the first subtracter 6 is as shown in FIG. 2e. Therefore, the output of the limiter 13 has a waveform that extracts the noise component of the flat part of the input signal as shown in the second figure. By appropriately setting the coefficient of the coefficient circuit 14 to 1, the output of the second subtracter 15 is At the output, a signal with significantly reduced noise components in the flat portion of the input signal is obtained, as shown in FIG. 2i.

またスライサ16の出力は第2図jのように入力信号の
平坦部分のノイズ成分が除去されてかつ輪郭近傍の差成
分を取り出したような波形となり、係数回路7の係数に
2を適当に設定することによって第2の加算器8の出力
すなわち出力端子9には第2図fのように共に時間幅T
を有するプリシュートとオーバーシュートが付加されか
つ平坦部のノイズ成分を大幅に低減した信号を得ること
ができる。
In addition, the output of the slicer 16 has a waveform in which the noise component in the flat part of the input signal has been removed and the difference component near the contour has been extracted, as shown in FIG. As a result, the output of the second adder 8, that is, the output terminal 9, has a time width T as shown in FIG.
It is possible to obtain a signal in which a preshoot and an overshoot are added, and the noise component in the flat portion is significantly reduced.

発明の効果 以上述べたように本発明によれば、2個の遅延9 ′\
−7 手段を用いるだけで、輪郭補正手段とノイズ低減手段の
両方を良好に行うことができる映像信号処理装置を実現
できる。
Effects of the Invention As described above, according to the present invention, two delays 9'\
-7 By simply using the means, it is possible to realize a video signal processing device that can effectively perform both the contour correction means and the noise reduction means.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による映像信号処理装置の一実施例を示
すブロック図、第2図は第1図の動作を説明するための
波形図、第3図は従来の映像信号処理装置を示すブロッ
ク図、第4図は第3図の動作を説明するための波形図、
第5図は従来の映像信号処理装置を示すブロック図、第
6図は第5図の動作を説明するための波形図である。 1・・・・・・入力端子、2,3,11・・・・・・遅
延手段、4・・・・・・増幅器、5,8・・・・・・加
算器、6,12゜15・・・・・・減算器、7,14・
・・・・・係数回路、9・・・・・・出力端子、13・
・・・・・リミッタ、16・・・・・・スライサ。 代理人の氏名 弁理士 粟 野 重 孝 ほか1名第1
図 第 図 →←−−T E’03図 竺 一フ 図 →←+←T
FIG. 1 is a block diagram showing an embodiment of a video signal processing device according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a block diagram showing a conventional video signal processing device. Figure 4 is a waveform diagram for explaining the operation of Figure 3,
FIG. 5 is a block diagram showing a conventional video signal processing device, and FIG. 6 is a waveform diagram for explaining the operation of FIG. 5. 1... Input terminal, 2, 3, 11... Delay means, 4... Amplifier, 5, 8... Adder, 6, 12゜15・・・・・・Subtractor, 7, 14・
... Coefficient circuit, 9 ... Output terminal, 13.
...Limiter, 16...Slicer. Name of agent: Patent attorney Shigetaka Awano and 1 other person 1st
Figure →←--T E'03 Figure 1-page →←+←T

Claims (1)

【特許請求の範囲】[Claims] 入力信号を第1の遅延時間だけ遅延する第1の遅延手段
と、前記第1の遅延手段の出力信号をさらに第2の遅延
時間だけ遅延する第2の遅延手段と、前記第1の遅延手
段の出力信号と前記入力信号との差成分を取り出す第1
の減算器と、前記第1の遅延手段の出力信号から前記第
2の遅延手段の出力信号との差成分を取り出す第2の減
算器と、前記第1の減算器の出力信号と前記第2の減算
器の出力信号を加算する加算器と、前記加算器の出力信
号のレベルを判別して前記レベルに応じた極性と比率で
前記減算器の出力信号を前記第1の遅延手段の出力信号
に混合する混合手段とを具備することを特徴とする映像
信号処理装置。
a first delay means for delaying the input signal by a first delay time; a second delay means for further delaying the output signal of the first delay means by a second delay time; and the first delay means. A first step for extracting a difference component between the output signal of the input signal and the input signal.
a second subtracter that extracts a difference component between the output signal of the second delay means and the output signal of the first delay means; an adder that adds the output signals of the subtracters; and an adder that determines the level of the output signal of the adder and adds the output signal of the subtracter to the output signal of the first delay means with a polarity and ratio according to the level. 1. A video signal processing device comprising: a mixing means for mixing.
JP88307988A 1988-12-06 1988-12-06 Video signal processor Pending JPH02154577A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP88307988A JPH02154577A (en) 1988-12-06 1988-12-06 Video signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP88307988A JPH02154577A (en) 1988-12-06 1988-12-06 Video signal processor

Publications (1)

Publication Number Publication Date
JPH02154577A true JPH02154577A (en) 1990-06-13

Family

ID=17975553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP88307988A Pending JPH02154577A (en) 1988-12-06 1988-12-06 Video signal processor

Country Status (1)

Country Link
JP (1) JPH02154577A (en)

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