JPH02154446A - Automated designing of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce unnecessary empty regions and reinforce countermeasures against latch-up by automatically placing a cell as well as a semiconductor substrate potential supply cell to a logic function. CONSTITUTION:Designing regulation conditions are input and then needed logic function cells 101 - 121 are placed in several stages to realize the target function. Then, the logic function cells 101 - 121 are distributed up to the regulation range of given designing regulation conditions (width and height of integrated circuit). Then, the obtained result is evaluated and then replacement and distribution of logic function cell are repasted until the designing regulation conditions and evaluation items are satisfied. After that, automatic placement is completed by placing cells 201 - 206 supplying potential to a semiconductor substrate at a region generated by distributing the logic function cell. This reduces empty region and reinforces measures against latch-up.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a cell that supplies a potential to a semiconductor substrate of a semiconductor integrated circuit. The present invention relates to an automatic design method of a semiconductor device that is automatically arranged together with a semiconductor device (Cell).

2. Description of the Related Art In recent years, automatic design (automatic placement and wiring) using computers has come to be used in the design of semiconductor integrated circuits, which are becoming larger in scale.

A conventional automatic design method will be explained below.

FIG. 4 is a flowchart 1 for automatically arranging logic function cells to be used in conventional automatic design. The operation of the automatic placement method in automatic design configured as shown in this flowchart will be described below.

First, in the section on inputting design constraints, students are made aware of the constraints of a semiconductor integrated circuit that will be realized through automatic design.

The constraint conditions here refer to the size of the automatically designed semiconductor integrated circuit, that is, limitations on areas such as width and height. Next, the logic function cells 101 to 121 necessary to realize the desired function are divided into multiple stages and arranged without any gaps, as shown in FIG. Evaluate the results obtained in this way, and if the design conditions are satisfied and the evaluation items (j1 value of wiring length, etc.) are satisfied, automatic placement is completed; if not, evaluation is completed. Re-arrange the layout until you are satisfied.

Problems to be Solved by the Invention However, in the conventional configuration described above, for example, when the width of a semiconductor integrated circuit to be realized by automatic design is fixed to a certain value, the width may vary depending on the number and width of logical function blocks. However, there was a problem in that a large empty area was left in some parts.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide an automatic semiconductor device design method that can not only reduce the free area but also strengthen latch-up countermeasures.

Means for Solving the Problems To achieve this objective, the automatic design method of the present invention:
It is characterized by automatically arranging cells that supply a potential to a semiconductor substrate together with basic logic function cells for realizing a target semiconductor integrated circuit.

Effect: With this configuration, it is possible to reduce the vacant area and to strengthen the latch-up countermeasures by using the cells that supply potential to the semiconductor substrate.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 3.

FIG. 1 is a flowchart of automatic placement of a method for automatically designing a semiconductor device according to an embodiment of the present invention. The operation of the automatic placement method of the automatic semiconductor device design method of this embodiment shown in this flowchart will be described below.

First, design constraints are input, and then the logic function cells necessary to realize the desired function are divided into multiple stages and arranged with gaps.Next, given design IU constraints (
Logic function cells are distributed to the limited range of the integrated circuit (radius 2 height). Then, the obtained results are evaluated, and the rearrangement and distribution of logic function cells are repeated until the design constraints and evaluation items are satisfied. Thereafter, automatic placement is completed by placing cells that supply potential to the semiconductor substrate in the area created by dispersing the logic function cells.

FIG. 2 shows the final placement results in this example. As is clear from FIG. 2, the logic function cells 101 to 121 are arranged in multiple stages, and the cells 201 to 206 that supply a potential to the semiconductor substrate are arranged between them. As a result, a large empty area as in the conventional example shown in FIG. 5 does not occur.

FIGS. 3(a) and 3(b) are a plan view showing an enlarged part of FIG. N area 301
and N ten area 302) let Vool::,P
The regions (P- region 401.P+ region 402) are connected to GND.

In addition, if the design constraints do not specify areas such as width and height, and the area is determined based on the placement results of logical function cells, calculate the area from the placement results and extend the logical function cells up to the calculated area. Perform dispersion. Thereafter, automatic placement is completed by placing semiconductor substrate potential supply cells in the vacant areas created by dispersing the logic function cells.

As described above, according to this embodiment, by distributing the logic function cells that have been deactivated within the design constraint range and arranging the semiconductor substrate potential supply cells in the resulting area, wasted free space is reduced. At the same time, by strengthening the supply of potential to the semiconductor substrate, measures against latch-up can be strengthened.

Effects of the Invention By automatically arranging semiconductor substrate potential supply cells together with logic function cells, the present invention can reduce wasted free space and strengthen latch-up countermeasures. An excellent automatic semiconductor device design method that can achieve the effect of dispersing the concentration of wiring between logic function cells after placement by distributing it to the limited range of design constraints. It is.

[Brief explanation of the drawing]

FIG. 1 is a diagram that does not show flowchart 1 of an automatic design method for a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing automatic placement results in the same embodiment, and FIGS. b
) are a plan view and a sectional view showing the main parts of FIG. 2, FIG. 4 is a flowchart of the conventional automatic design method, and FIG. 5 is a diagram showing the automatic arrangement result of the conventional example. 101-121...Logic function cells, 201-2
06...Semiconductor substrate potential supply cell. Name of agent: Patent attorney Shigetaka Awano Idiot 1 Figure

Claims (2)

[Claims] (1) Logic function cells that realize basic logic functions in a defined shape are arranged adjacently in multiple stages within a defined area, and then the logic function cells are distributed to the limit of the area. . A method for automatically designing a semiconductor device, characterized in that cells that supply a potential to a semiconductor substrate are automatically placed in empty areas created by dispersion. (2) The method for automatically designing a semiconductor device according to claim 1, wherein the determined area is an area that has been optimized by repeatedly arranging logic function cells.